diff --git a/gcc/config.gcc b/gcc/config.gcc
index f0958e1c959..951b92b2028 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -532,7 +532,7 @@ riscv*)
 	extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o riscv-v.o riscv-vsetvl.o"
 	extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
 	d_target_objs="riscv-d.o"
-	extra_headers="riscv_vector.h"
+	extra_headers="riscv_vector.h riscv_scalar_crypto.h"
 	target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.cc"
 	target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.h"
 	;;
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 14d18edbe62..f076ba35832 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -189,7 +189,7 @@
   [(set (match_operand:X 0 "register_operand" "=r")
         (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
                             (match_operand:X 2 "register_operand" "r")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "<insn>n\t%0,%2,%1"
   [(set_attr "type" "bitmanip")
    (set_attr "mode" "<X:MODE>")])
@@ -203,7 +203,7 @@
 			       (const_int 0)))
 		(match_operand:DI 2 "register_operand")))
    (clobber (match_operand:DI 3 "register_operand"))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   [(set (match_dup 3) (ashiftrt:DI (match_dup 1) (const_int 63)))
    (set (match_dup 0) (and:DI (not:DI (match_dup 3)) (match_dup 2)))])
 
@@ -211,7 +211,7 @@
   [(set (match_operand:X 0 "register_operand" "=r")
         (not:X (xor:X (match_operand:X 1 "register_operand" "r")
                       (match_operand:X 2 "register_operand" "r"))))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "xnor\t%0,%1,%2"
   [(set_attr "type" "bitmanip")
    (set_attr "mode" "<X:MODE>")])
@@ -277,7 +277,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(rotatert:SI (match_operand:SI 1 "register_operand" "r")
 		     (match_operand:QI 2 "arith_operand" "rI")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "ror%i2%~\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -285,7 +285,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(rotatert:DI (match_operand:DI 1 "register_operand" "r")
 		     (match_operand:QI 2 "arith_operand" "rI")))]
-  "TARGET_64BIT && TARGET_ZBB"
+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
   "ror%i2\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -293,7 +293,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(sign_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "r")
 				     (match_operand:QI 2 "register_operand" "r"))))]
-  "TARGET_64BIT && TARGET_ZBB"
+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
   "rorw\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -301,7 +301,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(rotate:SI (match_operand:SI 1 "register_operand" "r")
 		   (match_operand:QI 2 "register_operand" "r")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "rol%~\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -309,7 +309,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(rotate:DI (match_operand:DI 1 "register_operand" "r")
 		   (match_operand:QI 2 "register_operand" "r")))]
-  "TARGET_64BIT && TARGET_ZBB"
+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
   "rol\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -317,7 +317,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r")
 				   (match_operand:QI 2 "register_operand" "r"))))]
-  "TARGET_64BIT && TARGET_ZBB"
+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
   "rolw\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -332,7 +332,7 @@
 (define_insn "bswap<mode>2"
   [(set (match_operand:X 0 "register_operand" "=r")
         (bswap:X (match_operand:X 1 "register_operand" "r")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "rev8\t%0,%1"
   [(set_attr "type" "bitmanip")])
 
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
new file mode 100644
index 00000000000..048db920bb6
--- /dev/null
+++ b/gcc/config/riscv/crypto.md
@@ -0,0 +1,133 @@
+;; Machine description for RISC-V Scalar Cryptography extensions.
+;; Copyright (C) 2023 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_c_enum "unspec" [
+    ;; ZBKB unspecs
+    UNSPEC_BREV8
+    UNSPEC_ZIP
+    UNSPEC_UNZIP
+    UNSPEC_PACK
+    UNSPEC_PACKH
+    UNSPEC_PACKW
+
+    ;; ZBKC unspecs
+    UNSPEC_CLMUL
+    UNSPEC_CLMULH
+
+    ;; ZBKX unspecs
+    UNSPEC_XPERM8
+    UNSPEC_XPERM4
+
+
+])
+
+;; ZBKB extension
+(define_insn "riscv_brev8_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_BREV8))]
+  "TARGET_ZBKB"
+  "brev8\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_zip"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
+                  UNSPEC_ZIP))]
+  "TARGET_ZBKB && !TARGET_64BIT"
+  "zip\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_unzip"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
+                  UNSPEC_UNZIP))]
+  "TARGET_ZBKB && !TARGET_64BIT"
+  "unzip\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_pack_<X:mode><HISI:mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:HISI 1 "register_operand" "r")
+                  (match_operand:HISI 2 "register_operand" "r")]
+                  UNSPEC_PACK))]
+  "TARGET_ZBKB"
+  "pack\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_packh_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:QI 1 "register_operand" "r")
+                  (match_operand:QI 2 "register_operand" "r")]
+                  UNSPEC_PACKH))]
+  "TARGET_ZBKB"
+  "packh\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_packw"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:HI 1 "register_operand" "r")
+                  (match_operand:HI 2 "register_operand" "r")]
+                  UNSPEC_PACKW))]
+  "TARGET_ZBKB && TARGET_64BIT"
+  "packw\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+;; ZBKC extension
+
+(define_insn "riscv_clmul_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")]
+                  UNSPEC_CLMUL))]
+  "TARGET_ZBKC"
+  "clmul\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_clmulh_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")]
+                  UNSPEC_CLMULH))]
+  "TARGET_ZBKC"
+  "clmulh\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+;; ZBKX extension
+
+(define_insn "riscv_xperm4_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")]
+                  UNSPEC_XPERM4))]
+  "TARGET_ZBKX"
+  "xperm4\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_xperm8_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")]
+                  UNSPEC_XPERM8))]
+  "TARGET_ZBKX"
+  "xperm8\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+
+
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index ded91e17554..e9c2d92f0d3 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -100,6 +100,12 @@ AVAIL (zero32,  TARGET_ZICBOZ && !TARGET_64BIT)
 AVAIL (zero64,  TARGET_ZICBOZ && TARGET_64BIT)
 AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT)
 AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT)
+AVAIL (crypto_zbkb32, TARGET_ZBKB && !TARGET_64BIT)
+AVAIL (crypto_zbkb64, TARGET_ZBKB && TARGET_64BIT)
+AVAIL (crypto_zbkc32, TARGET_ZBKC && !TARGET_64BIT)
+AVAIL (crypto_zbkc64, TARGET_ZBKC && TARGET_64BIT)
+AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT)
+AVAIL (crypto_zbkx64, TARGET_ZBKX && TARGET_64BIT)
 AVAIL (always,     (!0))
 
 /* Construct a riscv_builtin_description from the given arguments.
@@ -152,6 +158,7 @@ AVAIL (always,     (!0))
   RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D
 
 static const struct riscv_builtin_description riscv_builtins[] = {
+  #include "riscv-crypto.def"
   #include "riscv-cmo.def"
 
   DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
diff --git a/gcc/config/riscv/riscv-crypto.def b/gcc/config/riscv/riscv-crypto.def
new file mode 100644
index 00000000000..40fbb9e43cb
--- /dev/null
+++ b/gcc/config/riscv/riscv-crypto.def
@@ -0,0 +1,46 @@
+/* Builtin functions for RISC-V Scalar Cryptography extensions.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+// ZBKB
+RISCV_BUILTIN (pack_sihi, "pack", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_HI_HI, crypto_zbkb32),
+RISCV_BUILTIN (pack_disi, "pack", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_SI_SI, crypto_zbkb64),
+
+RISCV_BUILTIN (packh_si, "packh", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_QI_QI, crypto_zbkb32),
+RISCV_BUILTIN (packh_di, "packh", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_QI_QI, crypto_zbkb64),
+
+RISCV_BUILTIN (packw, "packw", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_HI_HI, crypto_zbkb64),
+
+RISCV_BUILTIN (zip, "zip_32", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32),
+RISCV_BUILTIN (unzip, "unzip_32", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32),
+
+RISCV_BUILTIN (brev8_si, "brev8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32),
+RISCV_BUILTIN (brev8_di, "brev8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zbkb64),
+
+// ZBKC
+RISCV_BUILTIN (clmul_si, "clmul", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkc32),
+RISCV_BUILTIN (clmul_di, "clmul", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkc64),
+RISCV_BUILTIN (clmulh_si, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkc32),
+RISCV_BUILTIN (clmulh_di, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkc64),
+
+// ZBKX
+RISCV_BUILTIN (xperm4_si, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32),
+RISCV_BUILTIN (xperm4_di, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64),
+RISCV_BUILTIN (xperm8_si, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32),
+RISCV_BUILTIN (xperm8_di, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64),
+
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index c8adc5af5d2..c424a82dcbd 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -242,6 +242,7 @@
 ;; bitmanip	bit manipulation instructions
 ;; rotate   rotation instructions
 ;; atomic   atomic instructions
+;; crypto   cryptography instructions
 ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler.
 ;; rdvlenb     vector byte length vlenb csrr read
 ;; rdvl        vector length vl csrr read
@@ -333,7 +334,7 @@
   "unknown,branch,jump,call,load,fpload,store,fpstore,
    mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
    fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate,
-   atomic,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
+   atomic,crypto,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
    vldux,vldox,vstux,vstox,vldff,vldr,vstr,
    vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,
    vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,
@@ -3092,3 +3093,4 @@
 (include "generic.md")
 (include "sifive-7.md")
 (include "vector.md")
+(include "crypto.md")
diff --git a/gcc/config/riscv/riscv_scalar_crypto.h b/gcc/config/riscv/riscv_scalar_crypto.h
new file mode 100644
index 00000000000..76c0a4f0436
--- /dev/null
+++ b/gcc/config/riscv/riscv_scalar_crypto.h
@@ -0,0 +1,106 @@
+/* RISC-V Scalar Cryptography Extension intrinsics include file.
+   Copyright (C) 2022-2023 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef _RISCV_SCALAR_CRYPTO_H
+#define _RISCV_SCALAR_CRYPTO_H
+#endif	//	_RISCV_SCALAR_CRYPTO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(__riscv_xlen) && !defined(RVKINTRIN_EMULATE)
+#warning "Target is not RISC-V. Enabling insecure emulation."
+#define RVKINTRIN_EMULATE 1
+#endif
+
+//	intrinsics via compiler builtins
+#include <stdint.h>
+#define _RVK_INTRIN_IMPL(s) __builtin_riscv_##s
+
+
+//	set type if not already set
+#if !defined(RVKINTRIN_RV32) && !defined(RVKINTRIN_RV64)
+#if __riscv_xlen == 32
+#define RVKINTRIN_RV32
+#elif __riscv_xlen == 64
+#define RVKINTRIN_RV64
+#else
+#error "__riscv_xlen not valid."
+#endif
+#endif
+
+//	Mappings to implementation
+
+//	=== (mapping)	Zbkb:	Bitmanipulation instructions for Cryptography
+
+#ifdef RVKINTRIN_RV32
+static inline int32_t __riscv_pack(int16_t rs1, int16_t rs2)
+	{ return _RVK_INTRIN_IMPL(pack)(rs1, rs2); }			//	PACK
+
+static inline int32_t __riscv_packh(int8_t rs1, int8_t rs2)
+	{ return _RVK_INTRIN_IMPL(packh)(rs1, rs2); }			//	PACKH
+#endif
+
+#ifdef RVKINTRIN_RV64
+static inline int64_t __riscv_pack(int32_t rs1, int32_t rs2)
+	{ return _RVK_INTRIN_IMPL(pack)(rs1, rs2); }			//	PACK
+
+static inline int64_t __riscv_packh(int8_t rs1, int8_t rs2)
+	{ return _RVK_INTRIN_IMPL(packh)(rs1, rs2); }			//	PACKH
+
+static inline int64_t __riscv_packw(int16_t rs1, int16_t rs2)
+	{ return _RVK_INTRIN_IMPL(packw)(rs1, rs2); }			//	PACKW
+
+#endif
+
+static inline long __riscv_brev8(long rs1)
+	{ return _RVK_INTRIN_IMPL(brev8)(rs1); }				//	BREV8 (GREVI)
+
+#ifdef RVKINTRIN_RV32
+static inline int32_t __riscv_zip(int32_t rs1)
+	{ return _RVK_INTRIN_IMPL(zip_32)(rs1); }				//	ZIP (SHFLI)
+
+static inline int32_t __riscv_unzip(int32_t rs1)
+	{ return _RVK_INTRIN_IMPL(unzip_32)(rs1); }				//	UNZIP (UNSHFLI)
+#endif
+
+//	=== (mapping)	Zbkc:	Carry-less multiply instructions
+
+static inline long __riscv_clmul(long rs1, long rs2)
+	{ return _RVK_INTRIN_IMPL(clmul)(rs1, rs2); }		//	CLMUL
+
+static inline long __riscv_clmulh(long rs1, long rs2)
+	{ return _RVK_INTRIN_IMPL(clmulh)(rs1, rs2); }		//	CLMULH
+
+//	=== (mapping)	Zbkx:	Crossbar permutation instructions
+
+
+static inline long __riscv_xperm8(long rs1, long rs2)
+	{ return _RVK_INTRIN_IMPL(xperm8_64)(rs1, rs2); }		//	XPERM8
+
+static inline long __riscv_xperm4(long rs1, long rs2)
+	{ return _RVK_INTRIN_IMPL(xperm4_64)(rs1, rs2); }		//	XPERM4
+
+
diff --git a/gcc/testsuite/gcc.target/riscv/zbkb32.c b/gcc/testsuite/gcc.target/riscv/zbkb32.c
new file mode 100644
index 00000000000..c37492ae32b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkb32.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zbkb -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include "riscv_scalar_crypto.h"
+
+int32_t foo1(int16_t rs1, int16_t rs2)
+{
+    return __riscv_pack(rs1, rs2);
+}
+
+int32_t foo2(int8_t rs1, int8_t rs2)
+{
+    return __riscv_packh(rs1, rs2);
+}
+
+int32_t foo3(int32_t rs1)
+{
+    return __riscv_brev8(rs1);
+}
+
+int32_t foo4(int32_t rs1)
+{
+    return __riscv_zip(rs1);
+}
+
+int32_t foo5(int32_t rs1)
+{
+    return __riscv_unzip(rs1);
+}
+
+/* { dg-final { scan-assembler-times "pack\t" 1 } } */
+/* { dg-final { scan-assembler-times "packh" 1 } } */
+/* { dg-final { scan-assembler-times "brev8" 1 } } */
+/* { dg-final { scan-assembler-times "zip" 2 } } */
+/* { dg-final { scan-assembler-times "unzip" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkb64.c b/gcc/testsuite/gcc.target/riscv/zbkb64.c
new file mode 100644
index 00000000000..e7771f73394
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkb64.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zbkb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+#include "riscv_scalar_crypto.h"
+
+int64_t foo1(int32_t rs1, int32_t rs2)
+{
+    return __riscv_pack(rs1, rs2);
+}
+
+int64_t foo2(int8_t rs1, int8_t rs2)
+{
+    return __riscv_packh(rs1, rs2);
+}
+
+int64_t foo3(int16_t rs1, int16_t rs2)
+{
+    return __riscv_packw(rs1, rs2);
+}
+
+int64_t foo4(int64_t rs1, int64_t rs2)
+{
+    return __riscv_brev8(rs1);
+}
+/* { dg-final { scan-assembler-times "pack\t" 1 } } */
+/* { dg-final { scan-assembler-times "packh" 1 } } */
+/* { dg-final { scan-assembler-times "packw" 1 } } */
+/* { dg-final { scan-assembler-times "brev8" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkc32.c b/gcc/testsuite/gcc.target/riscv/zbkc32.c
new file mode 100644
index 00000000000..f1b538f1441
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkc32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zbkc -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+#include "riscv_scalar_crypto.h"
+
+int32_t foo1(int32_t rs1, int32_t rs2)
+{
+    return __riscv_clmul(rs1, rs2);
+}
+
+int32_t foo2(int32_t rs1, int32_t rs2)
+{
+    return __riscv_clmulh(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "clmul\t" 1 } } */
+/* { dg-final { scan-assembler-times "clmulh" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/zbkc64.c b/gcc/testsuite/gcc.target/riscv/zbkc64.c
new file mode 100644
index 00000000000..6493a83c57a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkc64.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zbkc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+#include "riscv_scalar_crypto.h"
+
+int64_t foo1(int64_t rs1, int64_t rs2)
+{
+    return __riscv_clmul(rs1, rs2);
+}
+
+int64_t foo2(int64_t rs1, int64_t rs2)
+{
+    return __riscv_clmulh(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "clmul\t" 1 } } */
+/* { dg-final { scan-assembler-times "clmulh" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkx32.c b/gcc/testsuite/gcc.target/riscv/zbkx32.c
new file mode 100644
index 00000000000..5196e97e5e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkx32.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zbkx -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include "riscv_scalar_crypto.h"
+
+int32_t foo3(int32_t rs1, int32_t rs2)
+{
+    return __riscv_xperm8(rs1, rs2);
+}
+
+int32_t foo4(int32_t rs1, int32_t rs2)
+{
+    return __riscv_xperm4(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "xperm8" 1 } } */
+/* { dg-final { scan-assembler-times "xperm4" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/zbkx64.c b/gcc/testsuite/gcc.target/riscv/zbkx64.c
new file mode 100644
index 00000000000..7bc09bd77be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkx64.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zbkx -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include "riscv_scalar_crypto.h"
+
+int64_t foo1(int64_t rs1, int64_t rs2)
+{
+    return __riscv_xperm8(rs1, rs2);
+}
+
+int64_t foo2(int64_t rs1, int64_t rs2)
+{
+    return __riscv_xperm4(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "xperm8" 1 } } */
+/* { dg-final { scan-assembler-times "xperm4" 1 } } */
