diff mbox series

RISC-V: Add vmsgt vx C++ tests

Message ID 20230213083334.291298-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Add vmsgt vx C++ tests |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai Feb. 13, 2023, 8:33 a.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vmsgt_vx_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vmsgt_vx_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vmsgt_vx_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vmsgt_vx_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vmsgt_vx_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vmsgt_vx_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vmsgtu_vx_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vmsgtu_vx_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vmsgtu_vx_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vmsgtu_vx_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vmsgtu_vx_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vmsgtu_vx_rv64-3.C: New test.

---
 .../riscv/rvv/base/vmsgt_vx_m_rv32-1.C        | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_m_rv32-2.C        | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_m_rv32-3.C        | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_m_rv64-1.C        | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_m_rv64-2.C        | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_m_rv64-3.C        | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_mu_rv32-1.C       | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_mu_rv32-2.C       | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_mu_rv32-3.C       | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_mu_rv64-1.C       | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_mu_rv64-2.C       | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_mu_rv64-3.C       | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_rv32-1.C          | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_rv32-2.C          | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_rv32-3.C          | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_rv64-1.C          | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_rv64-2.C          | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_rv64-3.C          | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_m_rv32-1.C       | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_m_rv32-2.C       | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_m_rv32-3.C       | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_m_rv64-1.C       | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_m_rv64-2.C       | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_m_rv64-3.C       | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_mu_rv32-1.C      | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_mu_rv32-2.C      | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_mu_rv32-3.C      | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_mu_rv64-1.C      | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_mu_rv64-2.C      | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_mu_rv64-3.C      | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_rv32-1.C         | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_rv32-2.C         | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_rv32-3.C         | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_rv64-1.C         | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_rv64-2.C         | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_rv64-3.C         | 160 ++++++++++++++++++
 36 files changed, 5706 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv64-3.C
diff mbox series

Patch

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-1.C
new file mode 100644
index 00000000000..2b1d0b36aad
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-1.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgt(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-2.C
new file mode 100644
index 00000000000..51842b4a935
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-2.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgt(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-3.C
new file mode 100644
index 00000000000..597029d2755
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-3.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgt(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-1.C
new file mode 100644
index 00000000000..c4687da1539
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgt(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-2.C
new file mode 100644
index 00000000000..7f070530554
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgt(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-3.C
new file mode 100644
index 00000000000..5de806fda8a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgt(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-1.C
new file mode 100644
index 00000000000..3e03eb5eb9d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-1.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgt_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-2.C
new file mode 100644
index 00000000000..809b1285c33
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-2.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgt_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-3.C
new file mode 100644
index 00000000000..7fced6f88ad
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-3.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgt_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-1.C
new file mode 100644
index 00000000000..139956209cd
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgt_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-2.C
new file mode 100644
index 00000000000..60a37a161a3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgt_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-3.C
new file mode 100644
index 00000000000..29fae139d45
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgt_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv32-1.C
new file mode 100644
index 00000000000..4eacf3bc76b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv32-1.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgt(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv32-2.C
new file mode 100644
index 00000000000..e9eb9896ed5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv32-2.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgt(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv32-3.C
new file mode 100644
index 00000000000..cb3d7828d82
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv32-3.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgt(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv64-1.C
new file mode 100644
index 00000000000..2fc7df04ead
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv64-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgt(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv64-2.C
new file mode 100644
index 00000000000..b449ddf3a14
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv64-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgt(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv64-3.C
new file mode 100644
index 00000000000..509962f68e4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv64-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgt(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-1.C
new file mode 100644
index 00000000000..a83bdb57990
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-1.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgtu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-2.C
new file mode 100644
index 00000000000..dc1cdb3a0ca
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-2.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgtu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-3.C
new file mode 100644
index 00000000000..87aa2ec59f3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-3.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgtu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-1.C
new file mode 100644
index 00000000000..7b4122ead8c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgtu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-2.C
new file mode 100644
index 00000000000..63f320fa296
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgtu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-3.C
new file mode 100644
index 00000000000..41179502d39
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgtu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-1.C
new file mode 100644
index 00000000000..d1f1853da59
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-1.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgtu_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-2.C
new file mode 100644
index 00000000000..186050309ae
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-2.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgtu_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-3.C
new file mode 100644
index 00000000000..46aa8efcec1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-3.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgtu_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-1.C
new file mode 100644
index 00000000000..8d4d694bcdf
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgtu_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-2.C
new file mode 100644
index 00000000000..f8c73f5cdd7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgtu_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-3.C
new file mode 100644
index 00000000000..9610d1ed98d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgtu_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv32-1.C
new file mode 100644
index 00000000000..fbcf1eb7197
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv32-1.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgtu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv32-2.C
new file mode 100644
index 00000000000..1006efce2cb
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv32-2.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgtu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv32-3.C
new file mode 100644
index 00000000000..6394f9fed30
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv32-3.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgtu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv64-1.C
new file mode 100644
index 00000000000..469422a8678
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv64-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgtu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv64-2.C
new file mode 100644
index 00000000000..f8ed4e3cd5b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv64-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgtu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv64-3.C
new file mode 100644
index 00000000000..a9ebba316bf
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv64-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgtu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */