diff mbox series

RISC-V: Add vmsgt vx C api tests

Message ID 20230213075149.270563-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Add vmsgt vx C api tests |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai Feb. 13, 2023, 7:51 a.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-1.c: New test.
        * gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-2.c: New test.
        * gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-3.c: New test.
        * gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-1.c: New test.
        * gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-2.c: New test.
        * gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-3.c: New test.
        * gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-1.c: New test.
        * gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-2.c: New test.
        * gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-3.c: New test.
        * gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-1.c: New test.
        * gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-2.c: New test.
        * gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-3.c: New test.
        * gcc.target/riscv/rvv/base/vmsgt_vx_rv32-1.c: New test.
        * gcc.target/riscv/rvv/base/vmsgt_vx_rv32-2.c: New test.
        * gcc.target/riscv/rvv/base/vmsgt_vx_rv32-3.c: New test.
        * gcc.target/riscv/rvv/base/vmsgt_vx_rv64-1.c: New test.
        * gcc.target/riscv/rvv/base/vmsgt_vx_rv64-2.c: New test.
        * gcc.target/riscv/rvv/base/vmsgt_vx_rv64-3.c: New test.
        * gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-1.c: New test.
        * gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-2.c: New test.
        * gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-3.c: New test.
        * gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-1.c: New test.
        * gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-2.c: New test.
        * gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-3.c: New test.
        * gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-1.c: New test.
        * gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-2.c: New test.
        * gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-3.c: New test.
        * gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-1.c: New test.
        * gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-2.c: New test.
        * gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-3.c: New test.
        * gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-1.c: New test.
        * gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-2.c: New test.
        * gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-3.c: New test.
        * gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-1.c: New test.
        * gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-2.c: New test.
        * gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-3.c: New test.

---
 .../riscv/rvv/base/vmsgt_vx_m_rv32-1.c        | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_m_rv32-2.c        | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_m_rv32-3.c        | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_m_rv64-1.c        | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_m_rv64-2.c        | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_m_rv64-3.c        | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_mu_rv32-1.c       | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_mu_rv32-2.c       | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_mu_rv32-3.c       | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_mu_rv64-1.c       | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_mu_rv64-2.c       | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_mu_rv64-3.c       | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_rv32-1.c          | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_rv32-2.c          | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_rv32-3.c          | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_rv64-1.c          | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_rv64-2.c          | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgt_vx_rv64-3.c          | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_m_rv32-1.c       | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_m_rv32-2.c       | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_m_rv32-3.c       | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_m_rv64-1.c       | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_m_rv64-2.c       | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_m_rv64-3.c       | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_mu_rv32-1.c      | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_mu_rv32-2.c      | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_mu_rv32-3.c      | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_mu_rv64-1.c      | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_mu_rv64-2.c      | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_mu_rv64-3.c      | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_rv32-1.c         | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_rv32-2.c         | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_rv32-3.c         | 157 +++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_rv64-1.c         | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_rv64-2.c         | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgtu_vx_rv64-3.c         | 160 ++++++++++++++++++
 36 files changed, 5706 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-3.c
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-1.c
new file mode 100644
index 00000000000..a33a900a96b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-1.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf8_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf4_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf2_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m1_b8_m(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m2_b4_m(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m4_b2_m(mask,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m8_b1_m(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf4_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf2_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m1_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m2_b8_m(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m4_b4_m(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m8_b2_m(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32mf2_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m1_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m2_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m4_b8_m(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m8_b4_m(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m1_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m2_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m4_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m8_b8_m(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-2.c
new file mode 100644
index 00000000000..d99479028f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-2.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf8_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf4_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf2_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m1_b8_m(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m2_b4_m(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m4_b2_m(mask,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m8_b1_m(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf4_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf2_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m1_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m2_b8_m(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m4_b4_m(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m8_b2_m(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32mf2_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m1_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m2_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m4_b8_m(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m8_b4_m(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m1_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m2_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m4_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m8_b8_m(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-3.c
new file mode 100644
index 00000000000..82e0e1f674a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-3.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf8_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf4_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf2_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m1_b8_m(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m2_b4_m(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m4_b2_m(mask,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m8_b1_m(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf4_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf2_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m1_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m2_b8_m(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m4_b4_m(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m8_b2_m(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32mf2_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m1_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m2_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m4_b8_m(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m8_b4_m(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m1_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m2_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m4_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m8_b8_m(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-1.c
new file mode 100644
index 00000000000..9d05730ab0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-1.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf8_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf4_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf2_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m1_b8_m(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m2_b4_m(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m4_b2_m(mask,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m8_b1_m(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf4_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf2_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m1_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m2_b8_m(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m4_b4_m(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m8_b2_m(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32mf2_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m1_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m2_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m4_b8_m(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m8_b4_m(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m1_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m2_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m4_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m8_b8_m(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-2.c
new file mode 100644
index 00000000000..c49d6a939ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-2.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf8_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf4_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf2_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m1_b8_m(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m2_b4_m(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m4_b2_m(mask,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m8_b1_m(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf4_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf2_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m1_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m2_b8_m(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m4_b4_m(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m8_b2_m(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32mf2_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m1_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m2_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m4_b8_m(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m8_b4_m(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m1_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m2_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m4_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m8_b8_m(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-3.c
new file mode 100644
index 00000000000..8b2990734f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-3.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf8_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf4_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf2_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m1_b8_m(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m2_b4_m(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m4_b2_m(mask,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m8_b1_m(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf4_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf2_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m1_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m2_b8_m(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m4_b4_m(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m8_b2_m(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32mf2_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m1_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m2_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m4_b8_m(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m8_b4_m(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m1_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m2_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m4_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m8_b8_m(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-1.c
new file mode 100644
index 00000000000..4d36b676850
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-1.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_vx_i8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf8_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf4_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf2_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i8m1_b8_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m1_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i8m2_b4_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m2_b4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i8m4_b2_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m4_b2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgt_vx_i8m8_b1_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m8_b1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf4_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf2_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i16m1_b16_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m1_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i16m2_b8_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m2_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i16m4_b4_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m4_b4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i16m8_b2_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m8_b2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32mf2_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i32m1_b32_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m1_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i32m2_b16_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m2_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i32m4_b8_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m4_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i32m8_b4_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m8_b4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i64m1_b64_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m1_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i64m2_b32_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m2_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i64m4_b16_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m4_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i64m8_b8_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m8_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-2.c
new file mode 100644
index 00000000000..cc405aadae3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-2.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_vx_i8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf8_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf4_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf2_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i8m1_b8_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m1_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i8m2_b4_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m2_b4_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i8m4_b2_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m4_b2_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgt_vx_i8m8_b1_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m8_b1_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf4_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf2_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i16m1_b16_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m1_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i16m2_b8_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m2_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i16m4_b4_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m4_b4_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i16m8_b2_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m8_b2_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32mf2_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i32m1_b32_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m1_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i32m2_b16_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m2_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i32m4_b8_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m4_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i32m8_b4_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m8_b4_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i64m1_b64_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m1_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i64m2_b32_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m2_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i64m4_b16_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m4_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i64m8_b8_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m8_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-3.c
new file mode 100644
index 00000000000..4492f6fea4b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-3.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_vx_i8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf8_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf4_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf2_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i8m1_b8_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m1_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i8m2_b4_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m2_b4_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i8m4_b2_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m4_b2_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgt_vx_i8m8_b1_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m8_b1_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf4_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf2_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i16m1_b16_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m1_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i16m2_b8_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m2_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i16m4_b4_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m4_b4_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i16m8_b2_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m8_b2_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32mf2_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i32m1_b32_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m1_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i32m2_b16_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m2_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i32m4_b8_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m4_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i32m8_b4_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m8_b4_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i64m1_b64_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m1_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i64m2_b32_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m2_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i64m4_b16_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m4_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i64m8_b8_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m8_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-1.c
new file mode 100644
index 00000000000..58c7cdbb7da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-1.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_vx_i8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf8_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf4_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf2_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i8m1_b8_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m1_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i8m2_b4_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m2_b4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i8m4_b2_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m4_b2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgt_vx_i8m8_b1_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m8_b1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf4_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf2_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i16m1_b16_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m1_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i16m2_b8_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m2_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i16m4_b4_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m4_b4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i16m8_b2_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m8_b2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32mf2_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i32m1_b32_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m1_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i32m2_b16_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m2_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i32m4_b8_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m4_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i32m8_b4_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m8_b4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i64m1_b64_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m1_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i64m2_b32_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m2_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i64m4_b16_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m4_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i64m8_b8_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m8_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-2.c
new file mode 100644
index 00000000000..eacccb47525
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-2.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_vx_i8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf8_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf4_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf2_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i8m1_b8_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m1_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i8m2_b4_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m2_b4_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i8m4_b2_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m4_b2_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgt_vx_i8m8_b1_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m8_b1_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf4_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf2_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i16m1_b16_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m1_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i16m2_b8_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m2_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i16m4_b4_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m4_b4_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i16m8_b2_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m8_b2_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32mf2_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i32m1_b32_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m1_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i32m2_b16_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m2_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i32m4_b8_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m4_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i32m8_b4_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m8_b4_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i64m1_b64_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m1_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i64m2_b32_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m2_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i64m4_b16_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m4_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i64m8_b8_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m8_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-3.c
new file mode 100644
index 00000000000..c0075d89043
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-3.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_vx_i8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf8_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf4_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf2_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i8m1_b8_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m1_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i8m2_b4_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m2_b4_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i8m4_b2_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m4_b2_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgt_vx_i8m8_b1_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m8_b1_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf4_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf2_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i16m1_b16_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m1_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i16m2_b8_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m2_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i16m4_b4_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m4_b4_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i16m8_b2_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m8_b2_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32mf2_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i32m1_b32_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m1_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i32m2_b16_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m2_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i32m4_b8_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m4_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i32m8_b4_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m8_b4_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i64m1_b64_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m1_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i64m2_b32_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m2_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i64m4_b16_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m4_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i64m8_b8_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m8_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv32-1.c
new file mode 100644
index 00000000000..b2ae2f10bdb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv32-1.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf8_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf4_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m1_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m2_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m4_b2(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m8_b1(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf4_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m1_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m2_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m4_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m8_b2(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32mf2_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m1_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m4_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m8_b4(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m1_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m4_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m8_b8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv32-2.c
new file mode 100644
index 00000000000..76503cb224f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv32-2.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf8_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf4_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m1_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m2_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m4_b2(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m8_b1(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf4_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m1_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m2_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m4_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m8_b2(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32mf2_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m1_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m4_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m8_b4(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m1_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m4_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m8_b8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv32-3.c
new file mode 100644
index 00000000000..dfc838f8031
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv32-3.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf8_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf4_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m1_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m2_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m4_b2(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m8_b1(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf4_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m1_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m2_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m4_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m8_b2(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32mf2_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m1_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m4_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m8_b4(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m1_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m4_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m8_b8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgt\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv64-1.c
new file mode 100644
index 00000000000..094bcb691aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv64-1.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf8_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf4_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m1_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m2_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m4_b2(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m8_b1(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf4_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m1_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m2_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m4_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m8_b2(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32mf2_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m1_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m4_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m8_b4(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m1_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m4_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m8_b8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv64-2.c
new file mode 100644
index 00000000000..1027b78e408
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv64-2.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf8_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf4_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m1_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m2_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m4_b2(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m8_b1(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf4_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m1_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m2_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m4_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m8_b2(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32mf2_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m1_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m4_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m8_b4(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m1_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m4_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m8_b8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv64-3.c
new file mode 100644
index 00000000000..288ef7f086b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv64-3.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgt_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf8_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf4_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8mf2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m1_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m2_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m4_b2(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgt_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i8m8_b1(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf4_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16mf2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m1_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m2_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m4_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgt_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i16m8_b2(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32mf2_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m1_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m4_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgt_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i32m8_b4(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgt_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m1_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgt_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgt_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m4_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgt_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmsgt_vx_i64m8_b8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgt\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-1.c
new file mode 100644
index 00000000000..8659fe612b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-1.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf8_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf4_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf2_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m1_b8_m(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m2_b4_m(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m4_b2_m(mask,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgtu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m8_b1_m(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf4_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf2_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m1_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m2_b8_m(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m4_b4_m(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m8_b2_m(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32mf2_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m1_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m2_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m4_b8_m(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m8_b4_m(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m1_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m2_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m4_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m8_b8_m(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-2.c
new file mode 100644
index 00000000000..6812193d412
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-2.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf8_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf4_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf2_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m1_b8_m(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m2_b4_m(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m4_b2_m(mask,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgtu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m8_b1_m(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf4_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf2_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m1_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m2_b8_m(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m4_b4_m(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m8_b2_m(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32mf2_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m1_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m2_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m4_b8_m(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m8_b4_m(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m1_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m2_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m4_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m8_b8_m(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-3.c
new file mode 100644
index 00000000000..648d0b75da0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-3.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf8_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf4_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf2_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m1_b8_m(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m2_b4_m(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m4_b2_m(mask,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgtu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m8_b1_m(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf4_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf2_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m1_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m2_b8_m(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m4_b4_m(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m8_b2_m(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32mf2_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m1_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m2_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m4_b8_m(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m8_b4_m(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m1_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m2_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m4_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m8_b8_m(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-1.c
new file mode 100644
index 00000000000..47d8c0af638
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-1.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf8_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf4_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf2_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m1_b8_m(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m2_b4_m(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m4_b2_m(mask,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgtu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m8_b1_m(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf4_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf2_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m1_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m2_b8_m(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m4_b4_m(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m8_b2_m(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32mf2_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m1_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m2_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m4_b8_m(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m8_b4_m(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m1_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m2_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m4_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m8_b8_m(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-2.c
new file mode 100644
index 00000000000..ef1c6867245
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-2.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf8_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf4_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf2_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m1_b8_m(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m2_b4_m(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m4_b2_m(mask,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgtu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m8_b1_m(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf4_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf2_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m1_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m2_b8_m(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m4_b4_m(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m8_b2_m(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32mf2_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m1_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m2_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m4_b8_m(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m8_b4_m(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m1_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m2_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m4_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m8_b8_m(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-3.c
new file mode 100644
index 00000000000..97e7d20a509
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-3.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf8_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf4_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf2_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m1_b8_m(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m2_b4_m(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m4_b2_m(mask,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgtu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m8_b1_m(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf4_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf2_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m1_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m2_b8_m(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m4_b4_m(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m8_b2_m(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32mf2_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m1_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m2_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m4_b8_m(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m8_b4_m(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m1_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m2_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m4_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m8_b8_m(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-1.c
new file mode 100644
index 00000000000..3e7389d9e9b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-1.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_vx_u8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf8_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf4_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf2_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u8m1_b8_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m1_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u8m2_b4_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m2_b4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u8m4_b2_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m4_b2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgtu_vx_u8m8_b1_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m8_b1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf4_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf2_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u16m1_b16_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m1_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u16m2_b8_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m2_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u16m4_b4_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m4_b4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u16m8_b2_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m8_b2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32mf2_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u32m1_b32_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m1_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u32m2_b16_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m2_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u32m4_b8_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m4_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u32m8_b4_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m8_b4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u64m1_b64_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m1_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u64m2_b32_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m2_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u64m4_b16_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m4_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u64m8_b8_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m8_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-2.c
new file mode 100644
index 00000000000..37863416038
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-2.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_vx_u8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf8_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf4_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf2_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u8m1_b8_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m1_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u8m2_b4_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m2_b4_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u8m4_b2_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m4_b2_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgtu_vx_u8m8_b1_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m8_b1_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf4_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf2_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u16m1_b16_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m1_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u16m2_b8_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m2_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u16m4_b4_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m4_b4_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u16m8_b2_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m8_b2_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32mf2_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u32m1_b32_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m1_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u32m2_b16_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m2_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u32m4_b8_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m4_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u32m8_b4_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m8_b4_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u64m1_b64_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m1_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u64m2_b32_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m2_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u64m4_b16_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m4_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u64m8_b8_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m8_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-3.c
new file mode 100644
index 00000000000..8c3a5f7babd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-3.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_vx_u8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf8_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf4_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf2_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u8m1_b8_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m1_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u8m2_b4_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m2_b4_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u8m4_b2_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m4_b2_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgtu_vx_u8m8_b1_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m8_b1_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf4_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf2_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u16m1_b16_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m1_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u16m2_b8_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m2_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u16m4_b4_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m4_b4_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u16m8_b2_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m8_b2_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32mf2_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u32m1_b32_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m1_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u32m2_b16_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m2_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u32m4_b8_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m4_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u32m8_b4_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m8_b4_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u64m1_b64_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m1_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u64m2_b32_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m2_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u64m4_b16_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m4_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u64m8_b8_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m8_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-1.c
new file mode 100644
index 00000000000..957e123eee3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-1.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_vx_u8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf8_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf4_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf2_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u8m1_b8_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m1_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u8m2_b4_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m2_b4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u8m4_b2_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m4_b2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgtu_vx_u8m8_b1_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m8_b1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf4_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf2_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u16m1_b16_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m1_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u16m2_b8_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m2_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u16m4_b4_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m4_b4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u16m8_b2_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m8_b2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32mf2_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u32m1_b32_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m1_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u32m2_b16_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m2_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u32m4_b8_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m4_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u32m8_b4_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m8_b4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u64m1_b64_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m1_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u64m2_b32_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m2_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u64m4_b16_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m4_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u64m8_b8_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m8_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-2.c
new file mode 100644
index 00000000000..ccaeaca38b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-2.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_vx_u8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf8_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf4_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf2_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u8m1_b8_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m1_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u8m2_b4_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m2_b4_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u8m4_b2_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m4_b2_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgtu_vx_u8m8_b1_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m8_b1_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf4_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf2_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u16m1_b16_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m1_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u16m2_b8_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m2_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u16m4_b4_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m4_b4_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u16m8_b2_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m8_b2_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32mf2_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u32m1_b32_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m1_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u32m2_b16_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m2_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u32m4_b8_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m4_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u32m8_b4_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m8_b4_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u64m1_b64_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m1_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u64m2_b32_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m2_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u64m4_b16_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m4_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u64m8_b8_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m8_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-3.c
new file mode 100644
index 00000000000..85df38d79e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-3.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_vx_u8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf8_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf4_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf2_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u8m1_b8_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m1_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u8m2_b4_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m2_b4_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u8m4_b2_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m4_b2_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgtu_vx_u8m8_b1_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m8_b1_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf4_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf2_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u16m1_b16_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m1_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u16m2_b8_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m2_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u16m4_b4_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m4_b4_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u16m8_b2_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m8_b2_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32mf2_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u32m1_b32_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m1_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u32m2_b16_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m2_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u32m4_b8_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m4_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u32m8_b4_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m8_b4_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u64m1_b64_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m1_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u64m2_b32_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m2_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u64m4_b16_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m4_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u64m8_b8_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m8_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-1.c
new file mode 100644
index 00000000000..9f78c57575e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-1.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf8_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf4_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m1_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m2_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m4_b2(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgtu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m8_b1(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf4_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m1_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m2_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m4_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m8_b2(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32mf2_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m1_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m4_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m8_b4(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m1_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m4_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m8_b8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-2.c
new file mode 100644
index 00000000000..97d9795fe05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-2.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf8_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf4_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m1_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m2_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m4_b2(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgtu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m8_b1(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf4_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m1_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m2_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m4_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m8_b2(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32mf2_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m1_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m4_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m8_b4(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m1_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m4_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m8_b8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-3.c
new file mode 100644
index 00000000000..2f8fcdc4664
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-3.c
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf8_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf4_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m1_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m2_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m4_b2(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgtu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m8_b1(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf4_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m1_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m2_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m4_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m8_b2(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32mf2_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m1_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m4_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m8_b4(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m1_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m4_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m8_b8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-1.c
new file mode 100644
index 00000000000..ee460f7bcc7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-1.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf8_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf4_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m1_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m2_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m4_b2(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgtu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m8_b1(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf4_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m1_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m2_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m4_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m8_b2(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32mf2_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m1_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m4_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m8_b4(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m1_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m4_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m8_b8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-2.c
new file mode 100644
index 00000000000..1fcc96df9ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-2.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf8_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf4_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m1_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m2_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m4_b2(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgtu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m8_b1(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf4_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m1_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m2_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m4_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m8_b2(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32mf2_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m1_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m4_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m8_b4(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m1_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m4_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m8_b8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-3.c
new file mode 100644
index 00000000000..49ef94fd4f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-3.c
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgtu_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf8_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf4_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8mf2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m1_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m2_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m4_b2(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgtu_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u8m8_b1(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf4_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16mf2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m1_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m2_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m4_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgtu_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u16m8_b2(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32mf2_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m1_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m4_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgtu_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u32m8_b4(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgtu_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m1_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgtu_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgtu_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m4_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgtu_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmsgtu_vx_u64m8_b8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgtu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */