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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c15-20020a17090603cf00b0088bd62b1cbbsm2976956eja.192.2023.02.10.14.41.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 14:41:58 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Kito Cheng , Christoph Muellner , Palmer Dabbelt , Andrew Waterman , Vineet Gupta , Philipp Tomsich Subject: [RFC PATCH v1 05/10] RISC-V: Support noce_try_store_flag_mask as czero.eqz/czero.nez Date: Fri, 10 Feb 2023 23:41:45 +0100 Message-Id: <20230210224150.2801962-6-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> References: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757485868924836730?= X-GMAIL-MSGID: =?utf-8?q?1757485868924836730?= When if-conversion in noce_try_store_flag_mask starts the sequence off with an order-operator, our patterns for czero.eqz/nez will receive the result of the order-operator as a register argument; consequently, they can't know that the result will be either 1 or 0. To convey this information (and make czero.eqz/nez applicable), we wrap the result of the order-operator in a eq/ne against (const_int 0). This commit adds the split pattern to handle these cases. During if-conversion, if noce_try_store_flag_mask succeeds, we may see if (cur < next) { next = 0; } transformed into 27: r82:SI=ltu(r76:DI,r75:DI) REG_DEAD r76:DI 28: r81:SI=r82:SI^0x1 REG_DEAD r82:SI 29: r80:DI=zero_extend(r81:SI) REG_DEAD r81:SI This currently escapes the combiner, as RISC-V does not have a pattern to apply the 'slt' instruction to 'geu' verbs. By adding a pattern in this commit, we match such cases. gcc/ChangeLog: * config/riscv/predicates.md (anyge_operator): Define. (anygt_operator): Same. (anyle_operator): Same. (anylt_operator): Same. * config/riscv/riscv.md: Helpers for ge(u) & le(u). * config/riscv/zicond.md: Add split to wrap an an order-operator suitably for generating czero.eqz/nez gcc/testsuite/ChangeLog: * gcc.target/riscv/zicond-le-02.c: New test. * gcc.target/riscv/zicond-lt-03.c: New test. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/predicates.md | 12 +++++ gcc/config/riscv/riscv.md | 26 ++++++++++ gcc/config/riscv/zicond.md | 50 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zicond-le-02.c | 11 ++++ gcc/testsuite/gcc.target/riscv/zicond-lt-03.c | 16 ++++++ 5 files changed, 115 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-le-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-lt-03.c diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 034d088c656..6b6f867824e 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -204,6 +204,18 @@ (define_predicate "modular_operator" (define_predicate "equality_operator" (match_code "eq,ne")) +(define_predicate "anyge_operator" + (match_code "ge,geu")) + +(define_predicate "anygt_operator" + (match_code "gt,gtu")) + +(define_predicate "anyle_operator" + (match_code "le,leu")) + +(define_predicate "anylt_operator" + (match_code "lt,ltu")) + (define_predicate "order_operator" (match_code "eq,ne,lt,ltu,le,leu,ge,geu,gt,gtu")) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 7c632bb4d65..6f255a80379 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2668,6 +2668,19 @@ (define_insn "*sge_" [(set_attr "type" "slt") (set_attr "mode" "")]) +(define_split + [(set (match_operand:GPR 0 "register_operand") + (match_operator:GPR 1 "anyle_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "register_operand")]))] + "TARGET_ZICOND" + [(set (match_dup 0) (match_dup 4)) + (set (match_dup 0) (eq:GPR (match_dup 0) (const_int 0)))] + { + operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == LE ? LT : LTU, + mode, operands[3], operands[2]); + }) + (define_insn "*slt_" [(set (match_operand:GPR 0 "register_operand" "= r") (any_lt:GPR (match_operand:X 1 "register_operand" " r") @@ -2689,6 +2702,19 @@ (define_insn "*sle_" [(set_attr "type" "slt") (set_attr "mode" "")]) +(define_split + [(set (match_operand:GPR 0 "register_operand") + (match_operator:GPR 1 "anyge_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "register_operand")]))] + "TARGET_ZICOND" + [(set (match_dup 0) (match_dup 4)) + (set (match_dup 0) (eq:GPR (match_dup 0) (const_int 0)))] +{ + operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GE ? LT : LTU, + mode, operands[2], operands[3]); +}) + ;; ;; .................... ;; diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md index 19d0b35585b..9d1ce067150 100644 --- a/gcc/config/riscv/zicond.md +++ b/gcc/config/riscv/zicond.md @@ -48,3 +48,53 @@ (define_split if (!rtx_equal_p (operands[0], operands[2])) operands[4] = operands[0]; }) + +;; Make order operators digestible to the vt.maskc logic by +;; wrapping their result in a comparison against (const_int 0). + +;; "a >= b" is "!(a < b)" +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (neg:X (match_operator:X 1 "anyge_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "arith_operand")])) + (match_operand:X 4 "register_operand"))) + (clobber (match_operand:X 5 "register_operand"))] + "TARGET_ZICOND" + [(set (match_dup 5) (match_dup 6)) + (set (match_dup 0) (and:X (neg:X (eq:X (match_dup 5) (const_int 0))) + (match_dup 4)))] +{ + operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GE ? LT : LTU, + mode, operands[2], operands[3]); +}) + +;; "a > b" +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (neg:X (match_operator:X 1 "anygt_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "arith_operand")])) + (match_operand:X 4 "register_operand"))) + (clobber (match_operand:X 5 "register_operand"))] + "TARGET_ZICOND" + [(set (match_dup 5) (match_dup 1)) + (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 5) (const_int 0))) + (match_dup 4)))]) + +;; "a <= b" is "!(a > b)" +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (neg:X (match_operator:X 1 "anyle_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "arith_operand")])) + (match_operand:X 4 "register_operand"))) + (clobber (match_operand:X 5 "register_operand"))] + "TARGET_ZICOND" + [(set (match_dup 5) (match_dup 6)) + (set (match_dup 0) (and:X (neg:X (eq:X (match_dup 5) (const_int 0))) + (match_dup 4)))] +{ + operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == LE ? GT : GTU, + mode, operands[2], operands[3]); +}) diff --git a/gcc/testsuite/gcc.target/riscv/zicond-le-02.c b/gcc/testsuite/gcc.target/riscv/zicond-le-02.c new file mode 100644 index 00000000000..32844bc0278 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-le-02.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long le2 (long long a, long long b, long long c) +{ + return (a <= c) ? b : 0; +} + +/* { dg-final { scan-assembler-times "sgt\t" 1 } } */ +/* { dg-final { scan-assembler-times "czero.nez\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-lt-03.c b/gcc/testsuite/gcc.target/riscv/zicond-lt-03.c new file mode 100644 index 00000000000..1c4f0d6ba10 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-lt-03.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64 -mbranch-cost=4" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long sink (long long); + +long long lt3 (long long a, long long b) +{ + if (a < b) + b = 0; + + return sink(b); +} + +/* { dg-final { scan-assembler-times "slt\t" 1 } } */ +/* { dg-final { scan-assembler-times "czero.nez\t" 1 } } */