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Subject: [PATCH] RISC-V: Add vnclip C++ API tests Date: Fri, 10 Feb 2023 14:53:44 +0800 Message-Id: <20230210065344.222680-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757426077400121947?= X-GMAIL-MSGID: =?utf-8?q?1757426077400121947?= From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vnclip_vv-1.C: New test. * g++.target/riscv/rvv/base/vnclip_vv-2.C: New test. * g++.target/riscv/rvv/base/vnclip_vv-3.C: New test. * g++.target/riscv/rvv/base/vnclip_vv_mu-1.C: New test. * g++.target/riscv/rvv/base/vnclip_vv_mu-2.C: New test. * g++.target/riscv/rvv/base/vnclip_vv_mu-3.C: New test. * g++.target/riscv/rvv/base/vnclip_vv_tu-1.C: New test. * g++.target/riscv/rvv/base/vnclip_vv_tu-2.C: New test. * g++.target/riscv/rvv/base/vnclip_vv_tu-3.C: New test. * g++.target/riscv/rvv/base/vnclip_vv_tum-1.C: New test. * g++.target/riscv/rvv/base/vnclip_vv_tum-2.C: New test. * g++.target/riscv/rvv/base/vnclip_vv_tum-3.C: New test. * g++.target/riscv/rvv/base/vnclip_vv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vnclip_vv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vnclip_vv_tumu-3.C: New test. * g++.target/riscv/rvv/base/vnclip_vx-1.C: New test. * g++.target/riscv/rvv/base/vnclip_vx-2.C: New test. * g++.target/riscv/rvv/base/vnclip_vx-3.C: New test. * g++.target/riscv/rvv/base/vnclip_vx_mu-1.C: New test. * g++.target/riscv/rvv/base/vnclip_vx_mu-2.C: New test. * g++.target/riscv/rvv/base/vnclip_vx_mu-3.C: New test. * g++.target/riscv/rvv/base/vnclip_vx_tu-1.C: New test. * g++.target/riscv/rvv/base/vnclip_vx_tu-2.C: New test. * g++.target/riscv/rvv/base/vnclip_vx_tu-3.C: New test. * g++.target/riscv/rvv/base/vnclip_vx_tum-1.C: New test. * g++.target/riscv/rvv/base/vnclip_vx_tum-2.C: New test. * g++.target/riscv/rvv/base/vnclip_vx_tum-3.C: New test. * g++.target/riscv/rvv/base/vnclip_vx_tumu-1.C: New test. * g++.target/riscv/rvv/base/vnclip_vx_tumu-2.C: New test. * g++.target/riscv/rvv/base/vnclip_vx_tumu-3.C: New test. * g++.target/riscv/rvv/base/vnclipu_vv-1.C: New test. * g++.target/riscv/rvv/base/vnclipu_vv-2.C: New test. * g++.target/riscv/rvv/base/vnclipu_vv-3.C: New test. * g++.target/riscv/rvv/base/vnclipu_vv_mu-1.C: New test. * g++.target/riscv/rvv/base/vnclipu_vv_mu-2.C: New test. * g++.target/riscv/rvv/base/vnclipu_vv_mu-3.C: New test. * g++.target/riscv/rvv/base/vnclipu_vv_tu-1.C: New test. * g++.target/riscv/rvv/base/vnclipu_vv_tu-2.C: New test. * g++.target/riscv/rvv/base/vnclipu_vv_tu-3.C: New test. * g++.target/riscv/rvv/base/vnclipu_vv_tum-1.C: New test. * g++.target/riscv/rvv/base/vnclipu_vv_tum-2.C: New test. * g++.target/riscv/rvv/base/vnclipu_vv_tum-3.C: New test. * g++.target/riscv/rvv/base/vnclipu_vv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vnclipu_vv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vnclipu_vv_tumu-3.C: New test. * g++.target/riscv/rvv/base/vnclipu_vx-1.C: New test. * g++.target/riscv/rvv/base/vnclipu_vx-2.C: New test. * g++.target/riscv/rvv/base/vnclipu_vx-3.C: New test. * g++.target/riscv/rvv/base/vnclipu_vx_mu-1.C: New test. * g++.target/riscv/rvv/base/vnclipu_vx_mu-2.C: New test. * g++.target/riscv/rvv/base/vnclipu_vx_mu-3.C: New test. * g++.target/riscv/rvv/base/vnclipu_vx_tu-1.C: New test. * g++.target/riscv/rvv/base/vnclipu_vx_tu-2.C: New test. * g++.target/riscv/rvv/base/vnclipu_vx_tu-3.C: New test. * g++.target/riscv/rvv/base/vnclipu_vx_tum-1.C: New test. * g++.target/riscv/rvv/base/vnclipu_vx_tum-2.C: New test. * g++.target/riscv/rvv/base/vnclipu_vx_tum-3.C: New test. * g++.target/riscv/rvv/base/vnclipu_vx_tumu-1.C: New test. * g++.target/riscv/rvv/base/vnclipu_vx_tumu-2.C: New test. * g++.target/riscv/rvv/base/vnclipu_vx_tumu-3.C: New test. --- .../g++.target/riscv/rvv/base/vnclip_vv-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnclip_vv-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnclip_vv-3.C | 216 ++++++++++++++++++ .../riscv/rvv/base/vnclip_vv_mu-1.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vv_mu-2.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vv_mu-3.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vv_tu-1.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vv_tu-2.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vv_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vv_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vv_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vv_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vv_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vv_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vv_tumu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vnclip_vx-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnclip_vx-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnclip_vx-3.C | 216 ++++++++++++++++++ .../riscv/rvv/base/vnclip_vx_mu-1.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vx_mu-2.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vx_mu-3.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vx_tu-1.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vx_tu-2.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vx_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vx_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vx_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vx_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vx_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vx_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vnclip_vx_tumu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnclipu_vv-3.C | 216 ++++++++++++++++++ .../riscv/rvv/base/vnclipu_vv_mu-1.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vv_mu-2.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vv_mu-3.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vv_tu-1.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vv_tu-2.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vv_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vv_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vv_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vv_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vv_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vv_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vv_tumu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnclipu_vx-3.C | 216 ++++++++++++++++++ .../riscv/rvv/base/vnclipu_vx_mu-1.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vx_mu-2.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vx_mu-3.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vx_tu-1.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vx_tu-2.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vx_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vx_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vx_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vx_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vx_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vx_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vnclipu_vx_tumu-3.C | 111 +++++++++ 60 files changed, 7920 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tumu-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv-1.C new file mode 100644 index 00000000000..2c58ecb19be --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip(vint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint8mf4_t test___riscv_vnclip(vint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint8mf2_t test___riscv_vnclip(vint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint8m1_t test___riscv_vnclip(vint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint8m2_t test___riscv_vnclip(vint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint8m4_t test___riscv_vnclip(vint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint16mf4_t test___riscv_vnclip(vint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint16mf2_t test___riscv_vnclip(vint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint16m1_t test___riscv_vnclip(vint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint16m2_t test___riscv_vnclip(vint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint16m4_t test___riscv_vnclip(vint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint32mf2_t test___riscv_vnclip(vint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint32m1_t test___riscv_vnclip(vint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint32m2_t test___riscv_vnclip(vint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint32m4_t test___riscv_vnclip(vint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint8mf8_t test___riscv_vnclip(vbool64_t mask,vint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint8mf4_t test___riscv_vnclip(vbool32_t mask,vint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint8mf2_t test___riscv_vnclip(vbool16_t mask,vint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint8m1_t test___riscv_vnclip(vbool8_t mask,vint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint8m2_t test___riscv_vnclip(vbool4_t mask,vint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint8m4_t test___riscv_vnclip(vbool2_t mask,vint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint16mf4_t test___riscv_vnclip(vbool64_t mask,vint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint16mf2_t test___riscv_vnclip(vbool32_t mask,vint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint16m1_t test___riscv_vnclip(vbool16_t mask,vint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint16m2_t test___riscv_vnclip(vbool8_t mask,vint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint16m4_t test___riscv_vnclip(vbool4_t mask,vint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint32mf2_t test___riscv_vnclip(vbool64_t mask,vint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint32m1_t test___riscv_vnclip(vbool32_t mask,vint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint32m2_t test___riscv_vnclip(vbool16_t mask,vint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint32m4_t test___riscv_vnclip(vbool8_t mask,vint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv-2.C new file mode 100644 index 00000000000..06a73adfc6a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip(vint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint8mf4_t test___riscv_vnclip(vint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint8mf2_t test___riscv_vnclip(vint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint8m1_t test___riscv_vnclip(vint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint8m2_t test___riscv_vnclip(vint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint8m4_t test___riscv_vnclip(vint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint16mf4_t test___riscv_vnclip(vint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint16mf2_t test___riscv_vnclip(vint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint16m1_t test___riscv_vnclip(vint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint16m2_t test___riscv_vnclip(vint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint16m4_t test___riscv_vnclip(vint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint32mf2_t test___riscv_vnclip(vint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint32m1_t test___riscv_vnclip(vint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint32m2_t test___riscv_vnclip(vint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint32m4_t test___riscv_vnclip(vint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint8mf8_t test___riscv_vnclip(vbool64_t mask,vint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint8mf4_t test___riscv_vnclip(vbool32_t mask,vint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint8mf2_t test___riscv_vnclip(vbool16_t mask,vint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint8m1_t test___riscv_vnclip(vbool8_t mask,vint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint8m2_t test___riscv_vnclip(vbool4_t mask,vint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint8m4_t test___riscv_vnclip(vbool2_t mask,vint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint16mf4_t test___riscv_vnclip(vbool64_t mask,vint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint16mf2_t test___riscv_vnclip(vbool32_t mask,vint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint16m1_t test___riscv_vnclip(vbool16_t mask,vint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint16m2_t test___riscv_vnclip(vbool8_t mask,vint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint16m4_t test___riscv_vnclip(vbool4_t mask,vint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint32mf2_t test___riscv_vnclip(vbool64_t mask,vint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint32m1_t test___riscv_vnclip(vbool32_t mask,vint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint32m2_t test___riscv_vnclip(vbool16_t mask,vint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint32m4_t test___riscv_vnclip(vbool8_t mask,vint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv-3.C new file mode 100644 index 00000000000..1abfe22560d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip(vint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint8mf4_t test___riscv_vnclip(vint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint8mf2_t test___riscv_vnclip(vint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint8m1_t test___riscv_vnclip(vint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint8m2_t test___riscv_vnclip(vint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint8m4_t test___riscv_vnclip(vint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint16mf4_t test___riscv_vnclip(vint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint16mf2_t test___riscv_vnclip(vint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint16m1_t test___riscv_vnclip(vint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint16m2_t test___riscv_vnclip(vint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint16m4_t test___riscv_vnclip(vint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint32mf2_t test___riscv_vnclip(vint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint32m1_t test___riscv_vnclip(vint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint32m2_t test___riscv_vnclip(vint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint32m4_t test___riscv_vnclip(vint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint8mf8_t test___riscv_vnclip(vbool64_t mask,vint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint8mf4_t test___riscv_vnclip(vbool32_t mask,vint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint8mf2_t test___riscv_vnclip(vbool16_t mask,vint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint8m1_t test___riscv_vnclip(vbool8_t mask,vint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint8m2_t test___riscv_vnclip(vbool4_t mask,vint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint8m4_t test___riscv_vnclip(vbool2_t mask,vint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint16mf4_t test___riscv_vnclip(vbool64_t mask,vint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint16mf2_t test___riscv_vnclip(vbool32_t mask,vint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint16m1_t test___riscv_vnclip(vbool16_t mask,vint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint16m2_t test___riscv_vnclip(vbool8_t mask,vint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint16m4_t test___riscv_vnclip(vbool4_t mask,vint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint32mf2_t test___riscv_vnclip(vbool64_t mask,vint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint32m1_t test___riscv_vnclip(vbool32_t mask,vint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint32m2_t test___riscv_vnclip(vbool16_t mask,vint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint32m4_t test___riscv_vnclip(vbool8_t mask,vint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_mu-1.C new file mode 100644 index 00000000000..8e9371e4184 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint8mf4_t test___riscv_vnclip_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint8mf2_t test___riscv_vnclip_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint8m1_t test___riscv_vnclip_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint8m2_t test___riscv_vnclip_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint8m4_t test___riscv_vnclip_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint16mf4_t test___riscv_vnclip_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint16mf2_t test___riscv_vnclip_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint16m1_t test___riscv_vnclip_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint16m2_t test___riscv_vnclip_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint16m4_t test___riscv_vnclip_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint32mf2_t test___riscv_vnclip_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint32m1_t test___riscv_vnclip_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint32m2_t test___riscv_vnclip_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint32m4_t test___riscv_vnclip_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_mu-2.C new file mode 100644 index 00000000000..5cd6cf8c4d3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint8mf4_t test___riscv_vnclip_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint8mf2_t test___riscv_vnclip_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint8m1_t test___riscv_vnclip_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint8m2_t test___riscv_vnclip_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint8m4_t test___riscv_vnclip_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint16mf4_t test___riscv_vnclip_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint16mf2_t test___riscv_vnclip_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint16m1_t test___riscv_vnclip_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint16m2_t test___riscv_vnclip_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint16m4_t test___riscv_vnclip_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint32mf2_t test___riscv_vnclip_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint32m1_t test___riscv_vnclip_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint32m2_t test___riscv_vnclip_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint32m4_t test___riscv_vnclip_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_mu-3.C new file mode 100644 index 00000000000..7d75c63e429 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint8mf4_t test___riscv_vnclip_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint8mf2_t test___riscv_vnclip_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint8m1_t test___riscv_vnclip_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint8m2_t test___riscv_vnclip_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint8m4_t test___riscv_vnclip_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint16mf4_t test___riscv_vnclip_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint16mf2_t test___riscv_vnclip_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint16m1_t test___riscv_vnclip_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint16m2_t test___riscv_vnclip_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint16m4_t test___riscv_vnclip_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint32mf2_t test___riscv_vnclip_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint32m1_t test___riscv_vnclip_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint32m2_t test___riscv_vnclip_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint32m4_t test___riscv_vnclip_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tu-1.C new file mode 100644 index 00000000000..1a9e434af87 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_tu(vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint8mf4_t test___riscv_vnclip_tu(vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint8mf2_t test___riscv_vnclip_tu(vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint8m1_t test___riscv_vnclip_tu(vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint8m2_t test___riscv_vnclip_tu(vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint8m4_t test___riscv_vnclip_tu(vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint16mf4_t test___riscv_vnclip_tu(vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint16mf2_t test___riscv_vnclip_tu(vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint16m1_t test___riscv_vnclip_tu(vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint16m2_t test___riscv_vnclip_tu(vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint16m4_t test___riscv_vnclip_tu(vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint32mf2_t test___riscv_vnclip_tu(vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint32m1_t test___riscv_vnclip_tu(vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint32m2_t test___riscv_vnclip_tu(vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint32m4_t test___riscv_vnclip_tu(vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tu-2.C new file mode 100644 index 00000000000..6f25e11f7e3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_tu(vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint8mf4_t test___riscv_vnclip_tu(vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint8mf2_t test___riscv_vnclip_tu(vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint8m1_t test___riscv_vnclip_tu(vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint8m2_t test___riscv_vnclip_tu(vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint8m4_t test___riscv_vnclip_tu(vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint16mf4_t test___riscv_vnclip_tu(vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint16mf2_t test___riscv_vnclip_tu(vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint16m1_t test___riscv_vnclip_tu(vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint16m2_t test___riscv_vnclip_tu(vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint16m4_t test___riscv_vnclip_tu(vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint32mf2_t test___riscv_vnclip_tu(vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint32m1_t test___riscv_vnclip_tu(vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint32m2_t test___riscv_vnclip_tu(vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint32m4_t test___riscv_vnclip_tu(vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tu-3.C new file mode 100644 index 00000000000..714e06292aa --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_tu(vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint8mf4_t test___riscv_vnclip_tu(vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint8mf2_t test___riscv_vnclip_tu(vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint8m1_t test___riscv_vnclip_tu(vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint8m2_t test___riscv_vnclip_tu(vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint8m4_t test___riscv_vnclip_tu(vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint16mf4_t test___riscv_vnclip_tu(vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint16mf2_t test___riscv_vnclip_tu(vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint16m1_t test___riscv_vnclip_tu(vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint16m2_t test___riscv_vnclip_tu(vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint16m4_t test___riscv_vnclip_tu(vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint32mf2_t test___riscv_vnclip_tu(vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint32m1_t test___riscv_vnclip_tu(vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint32m2_t test___riscv_vnclip_tu(vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint32m4_t test___riscv_vnclip_tu(vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tum-1.C new file mode 100644 index 00000000000..1a9d37af7e6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint8mf4_t test___riscv_vnclip_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint8mf2_t test___riscv_vnclip_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint8m1_t test___riscv_vnclip_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint8m2_t test___riscv_vnclip_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint8m4_t test___riscv_vnclip_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint16mf4_t test___riscv_vnclip_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint16mf2_t test___riscv_vnclip_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint16m1_t test___riscv_vnclip_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint16m2_t test___riscv_vnclip_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint16m4_t test___riscv_vnclip_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint32mf2_t test___riscv_vnclip_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint32m1_t test___riscv_vnclip_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint32m2_t test___riscv_vnclip_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint32m4_t test___riscv_vnclip_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tum-2.C new file mode 100644 index 00000000000..63bfef2d0dc --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint8mf4_t test___riscv_vnclip_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint8mf2_t test___riscv_vnclip_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint8m1_t test___riscv_vnclip_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint8m2_t test___riscv_vnclip_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint8m4_t test___riscv_vnclip_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint16mf4_t test___riscv_vnclip_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint16mf2_t test___riscv_vnclip_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint16m1_t test___riscv_vnclip_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint16m2_t test___riscv_vnclip_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint16m4_t test___riscv_vnclip_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint32mf2_t test___riscv_vnclip_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint32m1_t test___riscv_vnclip_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint32m2_t test___riscv_vnclip_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint32m4_t test___riscv_vnclip_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tum-3.C new file mode 100644 index 00000000000..2442bdc8eb0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint8mf4_t test___riscv_vnclip_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint8mf2_t test___riscv_vnclip_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint8m1_t test___riscv_vnclip_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint8m2_t test___riscv_vnclip_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint8m4_t test___riscv_vnclip_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint16mf4_t test___riscv_vnclip_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint16mf2_t test___riscv_vnclip_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint16m1_t test___riscv_vnclip_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint16m2_t test___riscv_vnclip_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint16m4_t test___riscv_vnclip_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint32mf2_t test___riscv_vnclip_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint32m1_t test___riscv_vnclip_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint32m2_t test___riscv_vnclip_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint32m4_t test___riscv_vnclip_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tumu-1.C new file mode 100644 index 00000000000..7a0e435f3cf --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint8mf4_t test___riscv_vnclip_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint8mf2_t test___riscv_vnclip_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint8m1_t test___riscv_vnclip_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint8m2_t test___riscv_vnclip_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint8m4_t test___riscv_vnclip_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint16mf4_t test___riscv_vnclip_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint16mf2_t test___riscv_vnclip_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint16m1_t test___riscv_vnclip_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint16m2_t test___riscv_vnclip_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint16m4_t test___riscv_vnclip_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint32mf2_t test___riscv_vnclip_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint32m1_t test___riscv_vnclip_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint32m2_t test___riscv_vnclip_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint32m4_t test___riscv_vnclip_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tumu-2.C new file mode 100644 index 00000000000..1d2d0f770b5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint8mf4_t test___riscv_vnclip_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint8mf2_t test___riscv_vnclip_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint8m1_t test___riscv_vnclip_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint8m2_t test___riscv_vnclip_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint8m4_t test___riscv_vnclip_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint16mf4_t test___riscv_vnclip_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint16mf2_t test___riscv_vnclip_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint16m1_t test___riscv_vnclip_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint16m2_t test___riscv_vnclip_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint16m4_t test___riscv_vnclip_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint32mf2_t test___riscv_vnclip_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint32m1_t test___riscv_vnclip_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint32m2_t test___riscv_vnclip_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint32m4_t test___riscv_vnclip_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tumu-3.C new file mode 100644 index 00000000000..16e52a5c9c4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint8mf4_t test___riscv_vnclip_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint8mf2_t test___riscv_vnclip_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint8m1_t test___riscv_vnclip_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint8m2_t test___riscv_vnclip_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint8m4_t test___riscv_vnclip_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint16mf4_t test___riscv_vnclip_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint16mf2_t test___riscv_vnclip_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint16m1_t test___riscv_vnclip_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint16m2_t test___riscv_vnclip_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint16m4_t test___riscv_vnclip_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint32mf2_t test___riscv_vnclip_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint32m1_t test___riscv_vnclip_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint32m2_t test___riscv_vnclip_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint32m4_t test___riscv_vnclip_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclip\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx-1.C new file mode 100644 index 00000000000..c734c9f2573 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip(vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint8mf4_t test___riscv_vnclip(vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint8mf2_t test___riscv_vnclip(vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint8m1_t test___riscv_vnclip(vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint8m2_t test___riscv_vnclip(vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint8m4_t test___riscv_vnclip(vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint16mf4_t test___riscv_vnclip(vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint16mf2_t test___riscv_vnclip(vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint16m1_t test___riscv_vnclip(vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint16m2_t test___riscv_vnclip(vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint16m4_t test___riscv_vnclip(vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint32mf2_t test___riscv_vnclip(vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint32m1_t test___riscv_vnclip(vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint32m2_t test___riscv_vnclip(vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint32m4_t test___riscv_vnclip(vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,vl); +} + + +vint8mf8_t test___riscv_vnclip(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint8mf4_t test___riscv_vnclip(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint8mf2_t test___riscv_vnclip(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint8m1_t test___riscv_vnclip(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint8m2_t test___riscv_vnclip(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint8m4_t test___riscv_vnclip(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint16mf4_t test___riscv_vnclip(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint16mf2_t test___riscv_vnclip(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint16m1_t test___riscv_vnclip(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint16m2_t test___riscv_vnclip(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint16m4_t test___riscv_vnclip(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint32mf2_t test___riscv_vnclip(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint32m1_t test___riscv_vnclip(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint32m2_t test___riscv_vnclip(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + +vint32m4_t test___riscv_vnclip(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx-2.C new file mode 100644 index 00000000000..b6f36e944f0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip(vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint8mf4_t test___riscv_vnclip(vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint8mf2_t test___riscv_vnclip(vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint8m1_t test___riscv_vnclip(vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint8m2_t test___riscv_vnclip(vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint8m4_t test___riscv_vnclip(vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint16mf4_t test___riscv_vnclip(vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint16mf2_t test___riscv_vnclip(vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint16m1_t test___riscv_vnclip(vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint16m2_t test___riscv_vnclip(vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint16m4_t test___riscv_vnclip(vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint32mf2_t test___riscv_vnclip(vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint32m1_t test___riscv_vnclip(vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint32m2_t test___riscv_vnclip(vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint32m4_t test___riscv_vnclip(vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,31); +} + + +vint8mf8_t test___riscv_vnclip(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint8mf4_t test___riscv_vnclip(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint8mf2_t test___riscv_vnclip(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint8m1_t test___riscv_vnclip(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint8m2_t test___riscv_vnclip(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint8m4_t test___riscv_vnclip(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint16mf4_t test___riscv_vnclip(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint16mf2_t test___riscv_vnclip(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint16m1_t test___riscv_vnclip(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint16m2_t test___riscv_vnclip(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint16m4_t test___riscv_vnclip(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint32mf2_t test___riscv_vnclip(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint32m1_t test___riscv_vnclip(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint32m2_t test___riscv_vnclip(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + +vint32m4_t test___riscv_vnclip(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx-3.C new file mode 100644 index 00000000000..1147371a38c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip(vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint8mf4_t test___riscv_vnclip(vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint8mf2_t test___riscv_vnclip(vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint8m1_t test___riscv_vnclip(vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint8m2_t test___riscv_vnclip(vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint8m4_t test___riscv_vnclip(vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint16mf4_t test___riscv_vnclip(vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint16mf2_t test___riscv_vnclip(vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint16m1_t test___riscv_vnclip(vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint16m2_t test___riscv_vnclip(vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint16m4_t test___riscv_vnclip(vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint32mf2_t test___riscv_vnclip(vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint32m1_t test___riscv_vnclip(vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint32m2_t test___riscv_vnclip(vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint32m4_t test___riscv_vnclip(vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(op1,shift,32); +} + + +vint8mf8_t test___riscv_vnclip(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint8mf4_t test___riscv_vnclip(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint8mf2_t test___riscv_vnclip(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint8m1_t test___riscv_vnclip(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint8m2_t test___riscv_vnclip(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint8m4_t test___riscv_vnclip(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint16mf4_t test___riscv_vnclip(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint16mf2_t test___riscv_vnclip(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint16m1_t test___riscv_vnclip(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint16m2_t test___riscv_vnclip(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint16m4_t test___riscv_vnclip(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint32mf2_t test___riscv_vnclip(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint32m1_t test___riscv_vnclip(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint32m2_t test___riscv_vnclip(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + +vint32m4_t test___riscv_vnclip(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip(mask,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_mu-1.C new file mode 100644 index 00000000000..6489fe02e65 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint8mf4_t test___riscv_vnclip_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint8mf2_t test___riscv_vnclip_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint8m1_t test___riscv_vnclip_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint8m2_t test___riscv_vnclip_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint8m4_t test___riscv_vnclip_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint16mf4_t test___riscv_vnclip_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint16mf2_t test___riscv_vnclip_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint16m1_t test___riscv_vnclip_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint16m2_t test___riscv_vnclip_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint16m4_t test___riscv_vnclip_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint32mf2_t test___riscv_vnclip_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint32m1_t test___riscv_vnclip_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint32m2_t test___riscv_vnclip_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + +vint32m4_t test___riscv_vnclip_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_mu-2.C new file mode 100644 index 00000000000..3013f77a949 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint8mf4_t test___riscv_vnclip_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint8mf2_t test___riscv_vnclip_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint8m1_t test___riscv_vnclip_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint8m2_t test___riscv_vnclip_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint8m4_t test___riscv_vnclip_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint16mf4_t test___riscv_vnclip_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint16mf2_t test___riscv_vnclip_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint16m1_t test___riscv_vnclip_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint16m2_t test___riscv_vnclip_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint16m4_t test___riscv_vnclip_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint32mf2_t test___riscv_vnclip_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint32m1_t test___riscv_vnclip_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint32m2_t test___riscv_vnclip_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + +vint32m4_t test___riscv_vnclip_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_mu-3.C new file mode 100644 index 00000000000..e218c71ead8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint8mf4_t test___riscv_vnclip_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint8mf2_t test___riscv_vnclip_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint8m1_t test___riscv_vnclip_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint8m2_t test___riscv_vnclip_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint8m4_t test___riscv_vnclip_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint16mf4_t test___riscv_vnclip_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint16mf2_t test___riscv_vnclip_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint16m1_t test___riscv_vnclip_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint16m2_t test___riscv_vnclip_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint16m4_t test___riscv_vnclip_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint32mf2_t test___riscv_vnclip_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint32m1_t test___riscv_vnclip_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint32m2_t test___riscv_vnclip_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + +vint32m4_t test___riscv_vnclip_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_mu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tu-1.C new file mode 100644 index 00000000000..0cbf6b5215d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_tu(vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint8mf4_t test___riscv_vnclip_tu(vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint8mf2_t test___riscv_vnclip_tu(vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint8m1_t test___riscv_vnclip_tu(vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint8m2_t test___riscv_vnclip_tu(vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint8m4_t test___riscv_vnclip_tu(vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint16mf4_t test___riscv_vnclip_tu(vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint16mf2_t test___riscv_vnclip_tu(vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint16m1_t test___riscv_vnclip_tu(vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint16m2_t test___riscv_vnclip_tu(vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint16m4_t test___riscv_vnclip_tu(vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint32mf2_t test___riscv_vnclip_tu(vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint32m1_t test___riscv_vnclip_tu(vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint32m2_t test___riscv_vnclip_tu(vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + +vint32m4_t test___riscv_vnclip_tu(vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tu-2.C new file mode 100644 index 00000000000..2817d42d4b9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_tu(vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint8mf4_t test___riscv_vnclip_tu(vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint8mf2_t test___riscv_vnclip_tu(vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint8m1_t test___riscv_vnclip_tu(vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint8m2_t test___riscv_vnclip_tu(vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint8m4_t test___riscv_vnclip_tu(vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint16mf4_t test___riscv_vnclip_tu(vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint16mf2_t test___riscv_vnclip_tu(vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint16m1_t test___riscv_vnclip_tu(vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint16m2_t test___riscv_vnclip_tu(vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint16m4_t test___riscv_vnclip_tu(vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint32mf2_t test___riscv_vnclip_tu(vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint32m1_t test___riscv_vnclip_tu(vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint32m2_t test___riscv_vnclip_tu(vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + +vint32m4_t test___riscv_vnclip_tu(vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tu-3.C new file mode 100644 index 00000000000..8ee4d5c7814 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_tu(vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint8mf4_t test___riscv_vnclip_tu(vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint8mf2_t test___riscv_vnclip_tu(vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint8m1_t test___riscv_vnclip_tu(vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint8m2_t test___riscv_vnclip_tu(vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint8m4_t test___riscv_vnclip_tu(vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint16mf4_t test___riscv_vnclip_tu(vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint16mf2_t test___riscv_vnclip_tu(vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint16m1_t test___riscv_vnclip_tu(vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint16m2_t test___riscv_vnclip_tu(vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint16m4_t test___riscv_vnclip_tu(vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint32mf2_t test___riscv_vnclip_tu(vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint32m1_t test___riscv_vnclip_tu(vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint32m2_t test___riscv_vnclip_tu(vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + +vint32m4_t test___riscv_vnclip_tu(vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tu(merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tum-1.C new file mode 100644 index 00000000000..a40bb5d95f9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint8mf4_t test___riscv_vnclip_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint8mf2_t test___riscv_vnclip_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint8m1_t test___riscv_vnclip_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint8m2_t test___riscv_vnclip_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint8m4_t test___riscv_vnclip_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint16mf4_t test___riscv_vnclip_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint16mf2_t test___riscv_vnclip_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint16m1_t test___riscv_vnclip_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint16m2_t test___riscv_vnclip_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint16m4_t test___riscv_vnclip_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint32mf2_t test___riscv_vnclip_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint32m1_t test___riscv_vnclip_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint32m2_t test___riscv_vnclip_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + +vint32m4_t test___riscv_vnclip_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tum-2.C new file mode 100644 index 00000000000..d390f209b73 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint8mf4_t test___riscv_vnclip_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint8mf2_t test___riscv_vnclip_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint8m1_t test___riscv_vnclip_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint8m2_t test___riscv_vnclip_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint8m4_t test___riscv_vnclip_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint16mf4_t test___riscv_vnclip_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint16mf2_t test___riscv_vnclip_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint16m1_t test___riscv_vnclip_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint16m2_t test___riscv_vnclip_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint16m4_t test___riscv_vnclip_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint32mf2_t test___riscv_vnclip_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint32m1_t test___riscv_vnclip_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint32m2_t test___riscv_vnclip_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + +vint32m4_t test___riscv_vnclip_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tum-3.C new file mode 100644 index 00000000000..1a699d42394 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint8mf4_t test___riscv_vnclip_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint8mf2_t test___riscv_vnclip_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint8m1_t test___riscv_vnclip_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint8m2_t test___riscv_vnclip_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint8m4_t test___riscv_vnclip_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint16mf4_t test___riscv_vnclip_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint16mf2_t test___riscv_vnclip_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint16m1_t test___riscv_vnclip_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint16m2_t test___riscv_vnclip_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint16m4_t test___riscv_vnclip_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint32mf2_t test___riscv_vnclip_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint32m1_t test___riscv_vnclip_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint32m2_t test___riscv_vnclip_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + +vint32m4_t test___riscv_vnclip_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tum(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tumu-1.C new file mode 100644 index 00000000000..fcda2b00a03 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint8mf4_t test___riscv_vnclip_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint8mf2_t test___riscv_vnclip_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint8m1_t test___riscv_vnclip_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint8m2_t test___riscv_vnclip_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint8m4_t test___riscv_vnclip_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint16mf4_t test___riscv_vnclip_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint16mf2_t test___riscv_vnclip_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint16m1_t test___riscv_vnclip_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint16m2_t test___riscv_vnclip_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint16m4_t test___riscv_vnclip_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint32mf2_t test___riscv_vnclip_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint32m1_t test___riscv_vnclip_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint32m2_t test___riscv_vnclip_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + +vint32m4_t test___riscv_vnclip_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tumu-2.C new file mode 100644 index 00000000000..587e7e67964 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint8mf4_t test___riscv_vnclip_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint8mf2_t test___riscv_vnclip_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint8m1_t test___riscv_vnclip_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint8m2_t test___riscv_vnclip_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint8m4_t test___riscv_vnclip_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint16mf4_t test___riscv_vnclip_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint16mf2_t test___riscv_vnclip_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint16m1_t test___riscv_vnclip_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint16m2_t test___riscv_vnclip_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint16m4_t test___riscv_vnclip_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint32mf2_t test___riscv_vnclip_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint32m1_t test___riscv_vnclip_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint32m2_t test___riscv_vnclip_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + +vint32m4_t test___riscv_vnclip_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tumu-3.C new file mode 100644 index 00000000000..3f56064d946 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnclip_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint8mf4_t test___riscv_vnclip_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint8mf2_t test___riscv_vnclip_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint8m1_t test___riscv_vnclip_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint8m2_t test___riscv_vnclip_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint8m4_t test___riscv_vnclip_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint16mf4_t test___riscv_vnclip_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint16mf2_t test___riscv_vnclip_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint16m1_t test___riscv_vnclip_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint16m2_t test___riscv_vnclip_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint16m4_t test___riscv_vnclip_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint32mf2_t test___riscv_vnclip_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint32m1_t test___riscv_vnclip_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint32m2_t test___riscv_vnclip_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + +vint32m4_t test___riscv_vnclip_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclip_tumu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclip\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv-1.C new file mode 100644 index 00000000000..30298fb30f3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu(vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnclipu(vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnclipu(vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnclipu(vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnclipu(vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnclipu(vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnclipu(vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnclipu(vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnclipu(vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnclipu(vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnclipu(vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnclipu(vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnclipu(vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnclipu(vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnclipu(vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint8mf8_t test___riscv_vnclipu(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnclipu(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnclipu(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnclipu(vbool8_t mask,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnclipu(vbool4_t mask,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnclipu(vbool2_t mask,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnclipu(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnclipu(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnclipu(vbool16_t mask,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnclipu(vbool8_t mask,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnclipu(vbool4_t mask,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnclipu(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnclipu(vbool32_t mask,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnclipu(vbool16_t mask,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnclipu(vbool8_t mask,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv-2.C new file mode 100644 index 00000000000..03d00d2f72c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu(vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnclipu(vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnclipu(vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint8m1_t test___riscv_vnclipu(vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint8m2_t test___riscv_vnclipu(vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint8m4_t test___riscv_vnclipu(vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnclipu(vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnclipu(vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint16m1_t test___riscv_vnclipu(vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint16m2_t test___riscv_vnclipu(vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint16m4_t test___riscv_vnclipu(vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnclipu(vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint32m1_t test___riscv_vnclipu(vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint32m2_t test___riscv_vnclipu(vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint32m4_t test___riscv_vnclipu(vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint8mf8_t test___riscv_vnclipu(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnclipu(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnclipu(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnclipu(vbool8_t mask,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnclipu(vbool4_t mask,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnclipu(vbool2_t mask,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnclipu(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnclipu(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnclipu(vbool16_t mask,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnclipu(vbool8_t mask,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnclipu(vbool4_t mask,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnclipu(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnclipu(vbool32_t mask,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnclipu(vbool16_t mask,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnclipu(vbool8_t mask,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv-3.C new file mode 100644 index 00000000000..4bb2c26b461 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu(vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnclipu(vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnclipu(vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint8m1_t test___riscv_vnclipu(vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint8m2_t test___riscv_vnclipu(vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint8m4_t test___riscv_vnclipu(vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnclipu(vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnclipu(vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint16m1_t test___riscv_vnclipu(vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint16m2_t test___riscv_vnclipu(vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint16m4_t test___riscv_vnclipu(vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnclipu(vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint32m1_t test___riscv_vnclipu(vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint32m2_t test___riscv_vnclipu(vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint32m4_t test___riscv_vnclipu(vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint8mf8_t test___riscv_vnclipu(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnclipu(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnclipu(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnclipu(vbool8_t mask,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnclipu(vbool4_t mask,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnclipu(vbool2_t mask,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnclipu(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnclipu(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnclipu(vbool16_t mask,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnclipu(vbool8_t mask,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnclipu(vbool4_t mask,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnclipu(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnclipu(vbool32_t mask,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnclipu(vbool16_t mask,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnclipu(vbool8_t mask,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_mu-1.C new file mode 100644 index 00000000000..b21aca86b94 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnclipu_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnclipu_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnclipu_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnclipu_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnclipu_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnclipu_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnclipu_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnclipu_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnclipu_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnclipu_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnclipu_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnclipu_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnclipu_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnclipu_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_mu-2.C new file mode 100644 index 00000000000..05a5a49002e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnclipu_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnclipu_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnclipu_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnclipu_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnclipu_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnclipu_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnclipu_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnclipu_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnclipu_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnclipu_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnclipu_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnclipu_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnclipu_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnclipu_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_mu-3.C new file mode 100644 index 00000000000..276bad5e7a2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnclipu_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnclipu_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnclipu_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnclipu_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnclipu_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnclipu_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnclipu_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnclipu_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnclipu_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnclipu_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnclipu_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnclipu_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnclipu_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnclipu_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tu-1.C new file mode 100644 index 00000000000..38776eb6475 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_tu(vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnclipu_tu(vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnclipu_tu(vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnclipu_tu(vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnclipu_tu(vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnclipu_tu(vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnclipu_tu(vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnclipu_tu(vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnclipu_tu(vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnclipu_tu(vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnclipu_tu(vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnclipu_tu(vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnclipu_tu(vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnclipu_tu(vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnclipu_tu(vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tu-2.C new file mode 100644 index 00000000000..5d8290060cf --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_tu(vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnclipu_tu(vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnclipu_tu(vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnclipu_tu(vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnclipu_tu(vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnclipu_tu(vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnclipu_tu(vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnclipu_tu(vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnclipu_tu(vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnclipu_tu(vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnclipu_tu(vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnclipu_tu(vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnclipu_tu(vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnclipu_tu(vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnclipu_tu(vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tu-3.C new file mode 100644 index 00000000000..605b1ce535d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_tu(vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnclipu_tu(vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnclipu_tu(vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnclipu_tu(vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnclipu_tu(vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnclipu_tu(vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnclipu_tu(vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnclipu_tu(vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnclipu_tu(vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnclipu_tu(vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnclipu_tu(vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnclipu_tu(vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnclipu_tu(vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnclipu_tu(vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnclipu_tu(vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tum-1.C new file mode 100644 index 00000000000..9c287f621e7 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnclipu_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnclipu_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnclipu_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnclipu_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnclipu_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnclipu_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnclipu_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnclipu_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnclipu_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnclipu_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnclipu_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnclipu_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnclipu_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnclipu_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tum-2.C new file mode 100644 index 00000000000..679a7833801 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnclipu_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnclipu_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnclipu_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnclipu_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnclipu_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnclipu_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnclipu_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnclipu_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnclipu_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnclipu_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnclipu_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnclipu_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnclipu_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnclipu_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tum-3.C new file mode 100644 index 00000000000..31bb2762ed0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnclipu_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnclipu_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnclipu_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnclipu_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnclipu_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnclipu_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnclipu_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnclipu_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnclipu_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnclipu_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnclipu_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnclipu_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnclipu_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnclipu_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tumu-1.C new file mode 100644 index 00000000000..6ee4d3669ba --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnclipu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnclipu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnclipu_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnclipu_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnclipu_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnclipu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnclipu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnclipu_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnclipu_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnclipu_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnclipu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnclipu_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnclipu_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnclipu_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tumu-2.C new file mode 100644 index 00000000000..4280d18d6e5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnclipu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnclipu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnclipu_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnclipu_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnclipu_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnclipu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnclipu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnclipu_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnclipu_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnclipu_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnclipu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnclipu_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnclipu_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnclipu_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tumu-3.C new file mode 100644 index 00000000000..ebb20f5f340 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnclipu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnclipu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnclipu_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnclipu_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnclipu_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnclipu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnclipu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnclipu_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnclipu_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnclipu_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnclipu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnclipu_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnclipu_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnclipu_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclipu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx-1.C new file mode 100644 index 00000000000..5ba9250e379 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu(vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnclipu(vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnclipu(vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnclipu(vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnclipu(vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnclipu(vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnclipu(vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnclipu(vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnclipu(vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnclipu(vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnclipu(vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnclipu(vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnclipu(vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnclipu(vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnclipu(vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,vl); +} + + +vuint8mf8_t test___riscv_vnclipu(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnclipu(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnclipu(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnclipu(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnclipu(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnclipu(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnclipu(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnclipu(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnclipu(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnclipu(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnclipu(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnclipu(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnclipu(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnclipu(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnclipu(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx-2.C new file mode 100644 index 00000000000..fb3971b2c0d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu(vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnclipu(vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnclipu(vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint8m1_t test___riscv_vnclipu(vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint8m2_t test___riscv_vnclipu(vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint8m4_t test___riscv_vnclipu(vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnclipu(vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnclipu(vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint16m1_t test___riscv_vnclipu(vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint16m2_t test___riscv_vnclipu(vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint16m4_t test___riscv_vnclipu(vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnclipu(vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint32m1_t test___riscv_vnclipu(vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint32m2_t test___riscv_vnclipu(vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint32m4_t test___riscv_vnclipu(vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,31); +} + + +vuint8mf8_t test___riscv_vnclipu(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnclipu(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnclipu(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnclipu(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnclipu(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnclipu(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnclipu(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnclipu(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnclipu(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnclipu(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnclipu(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnclipu(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnclipu(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnclipu(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnclipu(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx-3.C new file mode 100644 index 00000000000..bb27942d6e9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu(vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnclipu(vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnclipu(vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint8m1_t test___riscv_vnclipu(vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint8m2_t test___riscv_vnclipu(vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint8m4_t test___riscv_vnclipu(vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnclipu(vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnclipu(vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint16m1_t test___riscv_vnclipu(vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint16m2_t test___riscv_vnclipu(vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint16m4_t test___riscv_vnclipu(vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnclipu(vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint32m1_t test___riscv_vnclipu(vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint32m2_t test___riscv_vnclipu(vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint32m4_t test___riscv_vnclipu(vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(op1,shift,32); +} + + +vuint8mf8_t test___riscv_vnclipu(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnclipu(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnclipu(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnclipu(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnclipu(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnclipu(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnclipu(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnclipu(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnclipu(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnclipu(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnclipu(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnclipu(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnclipu(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnclipu(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnclipu(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu(mask,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_mu-1.C new file mode 100644 index 00000000000..03382f84e32 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnclipu_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnclipu_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnclipu_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnclipu_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnclipu_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnclipu_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnclipu_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnclipu_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnclipu_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnclipu_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnclipu_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnclipu_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnclipu_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnclipu_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_mu-2.C new file mode 100644 index 00000000000..35161b6a112 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnclipu_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnclipu_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnclipu_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnclipu_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnclipu_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnclipu_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnclipu_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnclipu_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnclipu_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnclipu_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnclipu_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnclipu_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnclipu_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnclipu_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_mu-3.C new file mode 100644 index 00000000000..48c42cd0843 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnclipu_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnclipu_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnclipu_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnclipu_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnclipu_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnclipu_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnclipu_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnclipu_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnclipu_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnclipu_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnclipu_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnclipu_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnclipu_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnclipu_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_mu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tu-1.C new file mode 100644 index 00000000000..af6fcbe5704 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_tu(vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnclipu_tu(vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnclipu_tu(vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnclipu_tu(vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnclipu_tu(vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnclipu_tu(vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnclipu_tu(vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnclipu_tu(vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnclipu_tu(vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnclipu_tu(vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnclipu_tu(vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnclipu_tu(vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnclipu_tu(vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnclipu_tu(vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnclipu_tu(vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tu-2.C new file mode 100644 index 00000000000..df52f5d6a01 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_tu(vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnclipu_tu(vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnclipu_tu(vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnclipu_tu(vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnclipu_tu(vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnclipu_tu(vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnclipu_tu(vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnclipu_tu(vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnclipu_tu(vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnclipu_tu(vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnclipu_tu(vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnclipu_tu(vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnclipu_tu(vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnclipu_tu(vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnclipu_tu(vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tu-3.C new file mode 100644 index 00000000000..0256e1e54f9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_tu(vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnclipu_tu(vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnclipu_tu(vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnclipu_tu(vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnclipu_tu(vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnclipu_tu(vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnclipu_tu(vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnclipu_tu(vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnclipu_tu(vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnclipu_tu(vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnclipu_tu(vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnclipu_tu(vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnclipu_tu(vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnclipu_tu(vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnclipu_tu(vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tu(merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tum-1.C new file mode 100644 index 00000000000..968249c02b0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnclipu_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnclipu_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnclipu_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnclipu_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnclipu_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnclipu_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnclipu_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnclipu_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnclipu_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnclipu_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnclipu_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnclipu_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnclipu_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnclipu_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tum-2.C new file mode 100644 index 00000000000..b92ea88db38 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnclipu_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnclipu_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnclipu_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnclipu_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnclipu_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnclipu_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnclipu_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnclipu_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnclipu_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnclipu_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnclipu_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnclipu_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnclipu_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnclipu_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tum-3.C new file mode 100644 index 00000000000..a589067c10a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnclipu_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnclipu_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnclipu_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnclipu_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnclipu_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnclipu_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnclipu_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnclipu_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnclipu_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnclipu_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnclipu_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnclipu_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnclipu_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnclipu_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tum(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tumu-1.C new file mode 100644 index 00000000000..ac722829959 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnclipu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnclipu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnclipu_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnclipu_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnclipu_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnclipu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnclipu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnclipu_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnclipu_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnclipu_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnclipu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnclipu_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnclipu_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnclipu_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tumu-2.C new file mode 100644 index 00000000000..beae8ad5b3b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnclipu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnclipu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnclipu_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnclipu_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnclipu_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnclipu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnclipu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnclipu_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnclipu_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnclipu_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnclipu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnclipu_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnclipu_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnclipu_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tumu-3.C new file mode 100644 index 00000000000..7dd7ff05d1a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnclipu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnclipu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnclipu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnclipu_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnclipu_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnclipu_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnclipu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnclipu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnclipu_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnclipu_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnclipu_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnclipu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnclipu_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnclipu_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnclipu_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnclipu_tumu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnclipu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */