diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv-1.C
new file mode 100644
index 00000000000..0664da7ffe8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra(vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra(vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra(vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra(vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra(vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra(vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra(vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra(vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra(vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra(vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra(vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra(vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra(vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra(vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra(vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra(vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra(vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra(vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra(vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra(vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra(vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra(vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8mf8_t test___riscv_vssra(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra(vbool8_t mask,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra(vbool4_t mask,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra(vbool2_t mask,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra(vbool1_t mask,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra(vbool16_t mask,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra(vbool8_t mask,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra(vbool4_t mask,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra(vbool2_t mask,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra(vbool32_t mask,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra(vbool16_t mask,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra(vbool8_t mask,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra(vbool4_t mask,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra(vbool64_t mask,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra(vbool32_t mask,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra(vbool16_t mask,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra(vbool8_t mask,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv-2.C
new file mode 100644
index 00000000000..4d8fa5f336e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv-2.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra(vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra(vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra(vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra(vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra(vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra(vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra(vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra(vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra(vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra(vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra(vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra(vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra(vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra(vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra(vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra(vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra(vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra(vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra(vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra(vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra(vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra(vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8mf8_t test___riscv_vssra(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra(vbool8_t mask,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra(vbool4_t mask,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra(vbool2_t mask,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra(vbool1_t mask,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra(vbool16_t mask,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra(vbool8_t mask,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra(vbool4_t mask,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra(vbool2_t mask,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra(vbool32_t mask,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra(vbool16_t mask,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra(vbool8_t mask,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra(vbool4_t mask,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra(vbool64_t mask,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra(vbool32_t mask,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra(vbool16_t mask,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra(vbool8_t mask,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv-3.C
new file mode 100644
index 00000000000..dbb90f7a004
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv-3.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra(vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra(vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra(vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra(vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra(vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra(vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra(vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra(vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra(vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra(vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra(vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra(vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra(vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra(vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra(vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra(vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra(vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra(vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra(vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra(vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra(vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra(vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8mf8_t test___riscv_vssra(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra(vbool8_t mask,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra(vbool4_t mask,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra(vbool2_t mask,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra(vbool1_t mask,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra(vbool16_t mask,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra(vbool8_t mask,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra(vbool4_t mask,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra(vbool2_t mask,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra(vbool32_t mask,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra(vbool16_t mask,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra(vbool8_t mask,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra(vbool4_t mask,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra(vbool64_t mask,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra(vbool32_t mask,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra(vbool16_t mask,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra(vbool8_t mask,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_mu-1.C
new file mode 100644
index 00000000000..71e2f3b78bf
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_mu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_mu-2.C
new file mode 100644
index 00000000000..7957da55e6b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_mu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_mu-3.C
new file mode 100644
index 00000000000..e858ec18258
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_mu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tu-1.C
new file mode 100644
index 00000000000..add5c08217f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tu(vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra_tu(vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra_tu(vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra_tu(vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra_tu(vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra_tu(vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra_tu(vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra_tu(vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra_tu(vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra_tu(vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra_tu(vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra_tu(vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra_tu(vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra_tu(vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra_tu(vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra_tu(vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra_tu(vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra_tu(vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra_tu(vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra_tu(vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra_tu(vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra_tu(vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tu-2.C
new file mode 100644
index 00000000000..53c22580fba
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tu(vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra_tu(vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra_tu(vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra_tu(vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra_tu(vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra_tu(vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra_tu(vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra_tu(vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra_tu(vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra_tu(vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra_tu(vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra_tu(vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra_tu(vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra_tu(vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra_tu(vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra_tu(vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra_tu(vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra_tu(vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra_tu(vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra_tu(vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra_tu(vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra_tu(vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tu-3.C
new file mode 100644
index 00000000000..46bbada4802
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tu(vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra_tu(vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra_tu(vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra_tu(vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra_tu(vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra_tu(vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra_tu(vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra_tu(vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra_tu(vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra_tu(vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra_tu(vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra_tu(vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra_tu(vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra_tu(vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra_tu(vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra_tu(vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra_tu(vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra_tu(vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra_tu(vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra_tu(vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra_tu(vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra_tu(vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tum-1.C
new file mode 100644
index 00000000000..0201b202252
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tum-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tum-2.C
new file mode 100644
index 00000000000..61d23a013db
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tum-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tum-3.C
new file mode 100644
index 00000000000..9bf698c0665
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tum-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tumu-1.C
new file mode 100644
index 00000000000..dfd91756b34
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tumu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tumu-2.C
new file mode 100644
index 00000000000..4d2758ff249
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tumu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tumu-3.C
new file mode 100644
index 00000000000..f9ad6f174c9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tumu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vuint16m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vuint32m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vuint64m1_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vuint64m2_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vuint64m4_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vuint64m8_t shift,size_t vl)
+{
+    return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vssra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
