diff mbox series

RISC-V: Add vnsra C++ API tests

Message ID 20230209215943.27763-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Add vnsra C++ API tests |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai Feb. 9, 2023, 9:59 p.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vnsra_vv-1.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vv-2.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vv-3.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vv_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vv_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vv_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vv_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vv_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vv_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vv_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vv_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vv_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vv_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vv_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vv_tumu-3.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vx-1.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vx-2.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vx-3.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vx_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vx_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vx_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vx_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vx_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vx_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vx_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vx_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vx_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vx_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vx_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vnsra_vx_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vnsra_vv-1.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vnsra_vv-2.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vnsra_vv-3.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vnsra_vv_mu-1.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vnsra_vv_mu-2.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vnsra_vv_mu-3.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vnsra_vv_tu-1.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vnsra_vv_tu-2.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vnsra_vv_tu-3.C | 111 +++++++++
 .../riscv/rvv/base/vnsra_vv_tum-1.C           | 111 +++++++++
 .../riscv/rvv/base/vnsra_vv_tum-2.C           | 111 +++++++++
 .../riscv/rvv/base/vnsra_vv_tum-3.C           | 111 +++++++++
 .../riscv/rvv/base/vnsra_vv_tumu-1.C          | 111 +++++++++
 .../riscv/rvv/base/vnsra_vv_tumu-2.C          | 111 +++++++++
 .../riscv/rvv/base/vnsra_vv_tumu-3.C          | 111 +++++++++
 .../g++.target/riscv/rvv/base/vnsra_vx-1.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vnsra_vx-2.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vnsra_vx-3.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vnsra_vx_mu-1.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vnsra_vx_mu-2.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vnsra_vx_mu-3.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vnsra_vx_tu-1.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vnsra_vx_tu-2.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vnsra_vx_tu-3.C | 111 +++++++++
 .../riscv/rvv/base/vnsra_vx_tum-1.C           | 111 +++++++++
 .../riscv/rvv/base/vnsra_vx_tum-2.C           | 111 +++++++++
 .../riscv/rvv/base/vnsra_vx_tum-3.C           | 111 +++++++++
 .../riscv/rvv/base/vnsra_vx_tumu-1.C          | 111 +++++++++
 .../riscv/rvv/base/vnsra_vx_tumu-2.C          | 111 +++++++++
 .../riscv/rvv/base/vnsra_vx_tumu-3.C          | 111 +++++++++
 30 files changed, 3960 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tumu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tumu-3.C
diff mbox series

Patch

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-1.C
new file mode 100644
index 00000000000..34aaaaefc76
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-1.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra(vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra(vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra(vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra(vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra(vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra(vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra(vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra(vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra(vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra(vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra(vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra(vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra(vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra(vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra(vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint8mf8_t test___riscv_vnsra(vbool64_t mask,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra(vbool32_t mask,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra(vbool16_t mask,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra(vbool8_t mask,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra(vbool4_t mask,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra(vbool2_t mask,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra(vbool64_t mask,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra(vbool32_t mask,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra(vbool16_t mask,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra(vbool8_t mask,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra(vbool4_t mask,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra(vbool64_t mask,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra(vbool32_t mask,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra(vbool16_t mask,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra(vbool8_t mask,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-2.C
new file mode 100644
index 00000000000..d80774a6f4d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-2.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra(vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra(vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra(vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra(vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra(vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra(vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra(vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra(vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra(vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra(vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra(vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra(vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra(vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra(vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra(vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint8mf8_t test___riscv_vnsra(vbool64_t mask,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra(vbool32_t mask,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra(vbool16_t mask,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra(vbool8_t mask,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra(vbool4_t mask,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra(vbool2_t mask,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra(vbool64_t mask,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra(vbool32_t mask,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra(vbool16_t mask,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra(vbool8_t mask,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra(vbool4_t mask,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra(vbool64_t mask,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra(vbool32_t mask,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra(vbool16_t mask,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra(vbool8_t mask,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-3.C
new file mode 100644
index 00000000000..a31d664643b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-3.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra(vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra(vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra(vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra(vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra(vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra(vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra(vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra(vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra(vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra(vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra(vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra(vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra(vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra(vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra(vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint8mf8_t test___riscv_vnsra(vbool64_t mask,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra(vbool32_t mask,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra(vbool16_t mask,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra(vbool8_t mask,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra(vbool4_t mask,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra(vbool2_t mask,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra(vbool64_t mask,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra(vbool32_t mask,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra(vbool16_t mask,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra(vbool8_t mask,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra(vbool4_t mask,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra(vbool64_t mask,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra(vbool32_t mask,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra(vbool16_t mask,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra(vbool8_t mask,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-1.C
new file mode 100644
index 00000000000..59808512342
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-2.C
new file mode 100644
index 00000000000..330b109b05c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-3.C
new file mode 100644
index 00000000000..b6aeda68918
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-1.C
new file mode 100644
index 00000000000..09027f66ad5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_tu(vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra_tu(vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra_tu(vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra_tu(vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra_tu(vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra_tu(vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra_tu(vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra_tu(vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra_tu(vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra_tu(vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra_tu(vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra_tu(vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra_tu(vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra_tu(vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra_tu(vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-2.C
new file mode 100644
index 00000000000..a1f983f8d7e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_tu(vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra_tu(vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra_tu(vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra_tu(vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra_tu(vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra_tu(vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra_tu(vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra_tu(vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra_tu(vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra_tu(vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra_tu(vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra_tu(vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra_tu(vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra_tu(vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra_tu(vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-3.C
new file mode 100644
index 00000000000..49f574df484
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_tu(vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra_tu(vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra_tu(vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra_tu(vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra_tu(vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra_tu(vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra_tu(vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra_tu(vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra_tu(vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra_tu(vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra_tu(vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra_tu(vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra_tu(vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra_tu(vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra_tu(vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-1.C
new file mode 100644
index 00000000000..309dcfc8048
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-2.C
new file mode 100644
index 00000000000..3759c494b73
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-3.C
new file mode 100644
index 00000000000..bbec7702e64
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tumu-1.C
new file mode 100644
index 00000000000..022bb5ee86d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tumu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tumu-2.C
new file mode 100644
index 00000000000..965b0c5d682
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tumu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tumu-3.C
new file mode 100644
index 00000000000..7973533cada
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tumu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx-1.C
new file mode 100644
index 00000000000..98ecf288fd4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx-1.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra(vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra(vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra(vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra(vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra(vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra(vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra(vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra(vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra(vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra(vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra(vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra(vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra(vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra(vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra(vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,vl);
+}
+
+
+vint8mf8_t test___riscv_vnsra(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx-2.C
new file mode 100644
index 00000000000..98f58b6b6a7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx-2.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra(vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra(vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra(vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra(vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra(vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra(vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra(vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra(vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra(vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra(vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra(vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra(vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra(vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra(vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra(vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,31);
+}
+
+
+vint8mf8_t test___riscv_vnsra(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx-3.C
new file mode 100644
index 00000000000..74cd95b9001
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx-3.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra(vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra(vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra(vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra(vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra(vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra(vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra(vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra(vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra(vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra(vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra(vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra(vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra(vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra(vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra(vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(op1,shift,32);
+}
+
+
+vint8mf8_t test___riscv_vnsra(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra(mask,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_mu-1.C
new file mode 100644
index 00000000000..979d1be80c7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_mu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_mu-2.C
new file mode 100644
index 00000000000..f8dc48bef2b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_mu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_mu-3.C
new file mode 100644
index 00000000000..f8323805d4d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_mu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_mu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tu-1.C
new file mode 100644
index 00000000000..28cbc6cc303
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_tu(vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra_tu(vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra_tu(vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra_tu(vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra_tu(vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra_tu(vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra_tu(vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra_tu(vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra_tu(vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra_tu(vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra_tu(vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra_tu(vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra_tu(vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra_tu(vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra_tu(vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tu-2.C
new file mode 100644
index 00000000000..5708905ee95
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_tu(vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra_tu(vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra_tu(vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra_tu(vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra_tu(vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra_tu(vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra_tu(vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra_tu(vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra_tu(vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra_tu(vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra_tu(vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra_tu(vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra_tu(vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra_tu(vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra_tu(vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tu-3.C
new file mode 100644
index 00000000000..32a3676dcd9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_tu(vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra_tu(vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra_tu(vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra_tu(vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra_tu(vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra_tu(vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra_tu(vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra_tu(vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra_tu(vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra_tu(vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra_tu(vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra_tu(vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra_tu(vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra_tu(vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra_tu(vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tu(merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tum-1.C
new file mode 100644
index 00000000000..f45b0fe21c8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tum-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tum-2.C
new file mode 100644
index 00000000000..a6a5c5af689
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tum-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tum-3.C
new file mode 100644
index 00000000000..a0b36c2f08d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tum-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tum(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tumu-1.C
new file mode 100644
index 00000000000..fe97e2e4eca
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tumu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tumu-2.C
new file mode 100644
index 00000000000..c2afdf4f1cf
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tumu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tumu-3.C
new file mode 100644
index 00000000000..70a51d63b79
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tumu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_tumu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */