diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-1.c
new file mode 100644
index 00000000000..ac570138785
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-1.c
@@ -0,0 +1,201 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_x_w_i8mf8(vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf8(src,vl);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_x_w_i8mf4(vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf4(src,vl);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_x_w_i8mf2(vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf2(src,vl);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_x_w_i8m1(vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m1(src,vl);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_x_w_i8m2(vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m2(src,vl);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_x_w_i8m4(vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m4(src,vl);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_x_w_u8mf8(vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf8(src,vl);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_x_w_u8mf4(vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf4(src,vl);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_x_w_u8mf2(vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf2(src,vl);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_x_w_u8m1(vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m1(src,vl);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_x_w_u8m2(vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m2(src,vl);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_x_w_u8m4(vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m4(src,vl);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_x_w_i16mf4(vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf4(src,vl);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_x_w_i16mf2(vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf2(src,vl);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_x_w_i16m1(vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m1(src,vl);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_x_w_i16m2(vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m2(src,vl);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_x_w_i16m4(vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m4(src,vl);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_x_w_u16mf4(vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf4(src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_x_w_u16mf2(vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf2(src,vl);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_x_w_u16m1(vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m1(src,vl);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_x_w_u16m2(vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m2(src,vl);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_x_w_u16m4(vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m4(src,vl);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_x_w_i32mf2(vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32mf2(src,vl);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_x_w_i32m1(vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m1(src,vl);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_x_w_i32m2(vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m2(src,vl);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_x_w_i32m4(vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m4(src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_x_w_u32mf2(vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32mf2(src,vl);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_x_w_u32m1(vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m1(src,vl);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_x_w_u32m2(vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m2(src,vl);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_x_w_u32m4(vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m4(src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-2.c
new file mode 100644
index 00000000000..3f9af13613c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-2.c
@@ -0,0 +1,201 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_x_w_i8mf8(vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf8(src,31);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_x_w_i8mf4(vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf4(src,31);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_x_w_i8mf2(vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf2(src,31);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_x_w_i8m1(vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m1(src,31);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_x_w_i8m2(vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m2(src,31);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_x_w_i8m4(vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m4(src,31);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_x_w_u8mf8(vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf8(src,31);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_x_w_u8mf4(vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf4(src,31);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_x_w_u8mf2(vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf2(src,31);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_x_w_u8m1(vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m1(src,31);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_x_w_u8m2(vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m2(src,31);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_x_w_u8m4(vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m4(src,31);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_x_w_i16mf4(vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf4(src,31);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_x_w_i16mf2(vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf2(src,31);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_x_w_i16m1(vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m1(src,31);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_x_w_i16m2(vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m2(src,31);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_x_w_i16m4(vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m4(src,31);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_x_w_u16mf4(vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf4(src,31);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_x_w_u16mf2(vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf2(src,31);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_x_w_u16m1(vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m1(src,31);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_x_w_u16m2(vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m2(src,31);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_x_w_u16m4(vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m4(src,31);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_x_w_i32mf2(vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32mf2(src,31);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_x_w_i32m1(vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m1(src,31);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_x_w_i32m2(vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m2(src,31);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_x_w_i32m4(vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m4(src,31);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_x_w_u32mf2(vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32mf2(src,31);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_x_w_u32m1(vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m1(src,31);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_x_w_u32m2(vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m2(src,31);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_x_w_u32m4(vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m4(src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-3.c
new file mode 100644
index 00000000000..01dc28bc10f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-3.c
@@ -0,0 +1,201 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_x_w_i8mf8(vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf8(src,32);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_x_w_i8mf4(vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf4(src,32);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_x_w_i8mf2(vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf2(src,32);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_x_w_i8m1(vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m1(src,32);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_x_w_i8m2(vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m2(src,32);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_x_w_i8m4(vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m4(src,32);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_x_w_u8mf8(vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf8(src,32);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_x_w_u8mf4(vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf4(src,32);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_x_w_u8mf2(vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf2(src,32);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_x_w_u8m1(vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m1(src,32);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_x_w_u8m2(vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m2(src,32);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_x_w_u8m4(vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m4(src,32);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_x_w_i16mf4(vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf4(src,32);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_x_w_i16mf2(vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf2(src,32);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_x_w_i16m1(vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m1(src,32);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_x_w_i16m2(vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m2(src,32);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_x_w_i16m4(vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m4(src,32);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_x_w_u16mf4(vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf4(src,32);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_x_w_u16mf2(vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf2(src,32);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_x_w_u16m1(vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m1(src,32);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_x_w_u16m2(vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m2(src,32);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_x_w_u16m4(vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m4(src,32);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_x_w_i32mf2(vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32mf2(src,32);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_x_w_i32m1(vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m1(src,32);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_x_w_i32m2(vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m2(src,32);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_x_w_i32m4(vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m4(src,32);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_x_w_u32mf2(vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32mf2(src,32);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_x_w_u32m1(vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m1(src,32);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_x_w_u32m2(vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m2(src,32);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_x_w_u32m4(vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m4(src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_m-1.c
new file mode 100644
index 00000000000..0a26798778c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_m-1.c
@@ -0,0 +1,201 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_x_w_i8mf8_m(vbool64_t mask,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf8_m(mask,src,vl);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_x_w_i8mf4_m(vbool32_t mask,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf4_m(mask,src,vl);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_x_w_i8mf2_m(vbool16_t mask,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf2_m(mask,src,vl);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_x_w_i8m1_m(vbool8_t mask,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m1_m(mask,src,vl);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_x_w_i8m2_m(vbool4_t mask,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m2_m(mask,src,vl);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_x_w_i8m4_m(vbool2_t mask,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m4_m(mask,src,vl);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_x_w_u8mf8_m(vbool64_t mask,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf8_m(mask,src,vl);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_x_w_u8mf4_m(vbool32_t mask,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf4_m(mask,src,vl);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_x_w_u8mf2_m(vbool16_t mask,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf2_m(mask,src,vl);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_x_w_u8m1_m(vbool8_t mask,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m1_m(mask,src,vl);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_x_w_u8m2_m(vbool4_t mask,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m2_m(mask,src,vl);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_x_w_u8m4_m(vbool2_t mask,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m4_m(mask,src,vl);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_x_w_i16mf4_m(vbool64_t mask,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf4_m(mask,src,vl);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_x_w_i16mf2_m(vbool32_t mask,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf2_m(mask,src,vl);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_x_w_i16m1_m(vbool16_t mask,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m1_m(mask,src,vl);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_x_w_i16m2_m(vbool8_t mask,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m2_m(mask,src,vl);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_x_w_i16m4_m(vbool4_t mask,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m4_m(mask,src,vl);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_x_w_u16mf4_m(vbool64_t mask,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf4_m(mask,src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_x_w_u16mf2_m(vbool32_t mask,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf2_m(mask,src,vl);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_x_w_u16m1_m(vbool16_t mask,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m1_m(mask,src,vl);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_x_w_u16m2_m(vbool8_t mask,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m2_m(mask,src,vl);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_x_w_u16m4_m(vbool4_t mask,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m4_m(mask,src,vl);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_x_w_i32mf2_m(vbool64_t mask,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32mf2_m(mask,src,vl);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_x_w_i32m1_m(vbool32_t mask,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m1_m(mask,src,vl);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_x_w_i32m2_m(vbool16_t mask,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m2_m(mask,src,vl);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_x_w_i32m4_m(vbool8_t mask,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m4_m(mask,src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_x_w_u32mf2_m(vbool64_t mask,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32mf2_m(mask,src,vl);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_x_w_u32m1_m(vbool32_t mask,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m1_m(mask,src,vl);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_x_w_u32m2_m(vbool16_t mask,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m2_m(mask,src,vl);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_x_w_u32m4_m(vbool8_t mask,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m4_m(mask,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_m-2.c
new file mode 100644
index 00000000000..f256d5e821f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_m-2.c
@@ -0,0 +1,201 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_x_w_i8mf8_m(vbool64_t mask,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf8_m(mask,src,31);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_x_w_i8mf4_m(vbool32_t mask,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf4_m(mask,src,31);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_x_w_i8mf2_m(vbool16_t mask,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf2_m(mask,src,31);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_x_w_i8m1_m(vbool8_t mask,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m1_m(mask,src,31);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_x_w_i8m2_m(vbool4_t mask,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m2_m(mask,src,31);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_x_w_i8m4_m(vbool2_t mask,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m4_m(mask,src,31);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_x_w_u8mf8_m(vbool64_t mask,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf8_m(mask,src,31);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_x_w_u8mf4_m(vbool32_t mask,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf4_m(mask,src,31);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_x_w_u8mf2_m(vbool16_t mask,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf2_m(mask,src,31);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_x_w_u8m1_m(vbool8_t mask,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m1_m(mask,src,31);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_x_w_u8m2_m(vbool4_t mask,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m2_m(mask,src,31);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_x_w_u8m4_m(vbool2_t mask,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m4_m(mask,src,31);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_x_w_i16mf4_m(vbool64_t mask,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf4_m(mask,src,31);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_x_w_i16mf2_m(vbool32_t mask,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf2_m(mask,src,31);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_x_w_i16m1_m(vbool16_t mask,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m1_m(mask,src,31);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_x_w_i16m2_m(vbool8_t mask,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m2_m(mask,src,31);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_x_w_i16m4_m(vbool4_t mask,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m4_m(mask,src,31);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_x_w_u16mf4_m(vbool64_t mask,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf4_m(mask,src,31);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_x_w_u16mf2_m(vbool32_t mask,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf2_m(mask,src,31);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_x_w_u16m1_m(vbool16_t mask,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m1_m(mask,src,31);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_x_w_u16m2_m(vbool8_t mask,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m2_m(mask,src,31);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_x_w_u16m4_m(vbool4_t mask,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m4_m(mask,src,31);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_x_w_i32mf2_m(vbool64_t mask,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32mf2_m(mask,src,31);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_x_w_i32m1_m(vbool32_t mask,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m1_m(mask,src,31);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_x_w_i32m2_m(vbool16_t mask,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m2_m(mask,src,31);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_x_w_i32m4_m(vbool8_t mask,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m4_m(mask,src,31);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_x_w_u32mf2_m(vbool64_t mask,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32mf2_m(mask,src,31);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_x_w_u32m1_m(vbool32_t mask,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m1_m(mask,src,31);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_x_w_u32m2_m(vbool16_t mask,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m2_m(mask,src,31);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_x_w_u32m4_m(vbool8_t mask,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m4_m(mask,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_m-3.c
new file mode 100644
index 00000000000..35e1900163c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_m-3.c
@@ -0,0 +1,201 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_x_w_i8mf8_m(vbool64_t mask,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf8_m(mask,src,32);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_x_w_i8mf4_m(vbool32_t mask,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf4_m(mask,src,32);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_x_w_i8mf2_m(vbool16_t mask,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf2_m(mask,src,32);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_x_w_i8m1_m(vbool8_t mask,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m1_m(mask,src,32);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_x_w_i8m2_m(vbool4_t mask,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m2_m(mask,src,32);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_x_w_i8m4_m(vbool2_t mask,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m4_m(mask,src,32);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_x_w_u8mf8_m(vbool64_t mask,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf8_m(mask,src,32);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_x_w_u8mf4_m(vbool32_t mask,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf4_m(mask,src,32);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_x_w_u8mf2_m(vbool16_t mask,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf2_m(mask,src,32);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_x_w_u8m1_m(vbool8_t mask,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m1_m(mask,src,32);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_x_w_u8m2_m(vbool4_t mask,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m2_m(mask,src,32);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_x_w_u8m4_m(vbool2_t mask,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m4_m(mask,src,32);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_x_w_i16mf4_m(vbool64_t mask,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf4_m(mask,src,32);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_x_w_i16mf2_m(vbool32_t mask,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf2_m(mask,src,32);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_x_w_i16m1_m(vbool16_t mask,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m1_m(mask,src,32);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_x_w_i16m2_m(vbool8_t mask,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m2_m(mask,src,32);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_x_w_i16m4_m(vbool4_t mask,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m4_m(mask,src,32);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_x_w_u16mf4_m(vbool64_t mask,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf4_m(mask,src,32);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_x_w_u16mf2_m(vbool32_t mask,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf2_m(mask,src,32);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_x_w_u16m1_m(vbool16_t mask,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m1_m(mask,src,32);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_x_w_u16m2_m(vbool8_t mask,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m2_m(mask,src,32);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_x_w_u16m4_m(vbool4_t mask,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m4_m(mask,src,32);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_x_w_i32mf2_m(vbool64_t mask,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32mf2_m(mask,src,32);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_x_w_i32m1_m(vbool32_t mask,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m1_m(mask,src,32);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_x_w_i32m2_m(vbool16_t mask,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m2_m(mask,src,32);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_x_w_i32m4_m(vbool8_t mask,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m4_m(mask,src,32);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_x_w_u32mf2_m(vbool64_t mask,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32mf2_m(mask,src,32);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_x_w_u32m1_m(vbool32_t mask,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m1_m(mask,src,32);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_x_w_u32m2_m(vbool16_t mask,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m2_m(mask,src,32);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_x_w_u32m4_m(vbool8_t mask,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m4_m(mask,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_mu-1.c
new file mode 100644
index 00000000000..94a8ca9feb6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_mu-1.c
@@ -0,0 +1,201 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_x_w_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf8_mu(mask,merge,src,vl);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_x_w_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf4_mu(mask,merge,src,vl);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_x_w_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf2_mu(mask,merge,src,vl);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_x_w_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m1_mu(mask,merge,src,vl);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_x_w_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m2_mu(mask,merge,src,vl);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_x_w_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m4_mu(mask,merge,src,vl);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_x_w_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf8_mu(mask,merge,src,vl);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_x_w_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf4_mu(mask,merge,src,vl);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_x_w_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf2_mu(mask,merge,src,vl);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_x_w_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m1_mu(mask,merge,src,vl);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_x_w_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m2_mu(mask,merge,src,vl);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_x_w_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m4_mu(mask,merge,src,vl);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_x_w_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf4_mu(mask,merge,src,vl);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_x_w_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf2_mu(mask,merge,src,vl);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_x_w_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m1_mu(mask,merge,src,vl);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_x_w_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m2_mu(mask,merge,src,vl);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_x_w_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m4_mu(mask,merge,src,vl);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_x_w_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf4_mu(mask,merge,src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_x_w_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf2_mu(mask,merge,src,vl);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_x_w_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m1_mu(mask,merge,src,vl);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_x_w_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m2_mu(mask,merge,src,vl);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_x_w_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m4_mu(mask,merge,src,vl);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_x_w_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32mf2_mu(mask,merge,src,vl);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_x_w_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m1_mu(mask,merge,src,vl);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_x_w_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m2_mu(mask,merge,src,vl);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_x_w_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m4_mu(mask,merge,src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_x_w_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32mf2_mu(mask,merge,src,vl);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_x_w_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m1_mu(mask,merge,src,vl);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_x_w_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m2_mu(mask,merge,src,vl);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_x_w_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m4_mu(mask,merge,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_mu-2.c
new file mode 100644
index 00000000000..1bb59c4524d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_mu-2.c
@@ -0,0 +1,201 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_x_w_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf8_mu(mask,merge,src,31);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_x_w_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf4_mu(mask,merge,src,31);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_x_w_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf2_mu(mask,merge,src,31);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_x_w_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m1_mu(mask,merge,src,31);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_x_w_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m2_mu(mask,merge,src,31);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_x_w_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m4_mu(mask,merge,src,31);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_x_w_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf8_mu(mask,merge,src,31);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_x_w_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf4_mu(mask,merge,src,31);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_x_w_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf2_mu(mask,merge,src,31);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_x_w_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m1_mu(mask,merge,src,31);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_x_w_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m2_mu(mask,merge,src,31);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_x_w_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m4_mu(mask,merge,src,31);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_x_w_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf4_mu(mask,merge,src,31);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_x_w_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf2_mu(mask,merge,src,31);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_x_w_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m1_mu(mask,merge,src,31);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_x_w_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m2_mu(mask,merge,src,31);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_x_w_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m4_mu(mask,merge,src,31);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_x_w_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf4_mu(mask,merge,src,31);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_x_w_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf2_mu(mask,merge,src,31);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_x_w_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m1_mu(mask,merge,src,31);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_x_w_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m2_mu(mask,merge,src,31);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_x_w_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m4_mu(mask,merge,src,31);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_x_w_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32mf2_mu(mask,merge,src,31);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_x_w_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m1_mu(mask,merge,src,31);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_x_w_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m2_mu(mask,merge,src,31);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_x_w_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m4_mu(mask,merge,src,31);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_x_w_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32mf2_mu(mask,merge,src,31);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_x_w_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m1_mu(mask,merge,src,31);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_x_w_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m2_mu(mask,merge,src,31);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_x_w_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m4_mu(mask,merge,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_mu-3.c
new file mode 100644
index 00000000000..ecdf0350a06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_mu-3.c
@@ -0,0 +1,201 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_x_w_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf8_mu(mask,merge,src,32);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_x_w_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf4_mu(mask,merge,src,32);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_x_w_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf2_mu(mask,merge,src,32);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_x_w_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m1_mu(mask,merge,src,32);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_x_w_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m2_mu(mask,merge,src,32);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_x_w_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m4_mu(mask,merge,src,32);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_x_w_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf8_mu(mask,merge,src,32);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_x_w_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf4_mu(mask,merge,src,32);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_x_w_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf2_mu(mask,merge,src,32);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_x_w_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m1_mu(mask,merge,src,32);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_x_w_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m2_mu(mask,merge,src,32);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_x_w_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m4_mu(mask,merge,src,32);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_x_w_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf4_mu(mask,merge,src,32);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_x_w_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf2_mu(mask,merge,src,32);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_x_w_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m1_mu(mask,merge,src,32);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_x_w_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m2_mu(mask,merge,src,32);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_x_w_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m4_mu(mask,merge,src,32);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_x_w_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf4_mu(mask,merge,src,32);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_x_w_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf2_mu(mask,merge,src,32);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_x_w_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m1_mu(mask,merge,src,32);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_x_w_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m2_mu(mask,merge,src,32);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_x_w_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m4_mu(mask,merge,src,32);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_x_w_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32mf2_mu(mask,merge,src,32);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_x_w_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m1_mu(mask,merge,src,32);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_x_w_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m2_mu(mask,merge,src,32);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_x_w_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m4_mu(mask,merge,src,32);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_x_w_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32mf2_mu(mask,merge,src,32);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_x_w_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m1_mu(mask,merge,src,32);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_x_w_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m2_mu(mask,merge,src,32);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_x_w_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m4_mu(mask,merge,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tu-1.c
new file mode 100644
index 00000000000..a776c0f6ae0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tu-1.c
@@ -0,0 +1,201 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_x_w_i8mf8_tu(vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf8_tu(merge,src,vl);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_x_w_i8mf4_tu(vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf4_tu(merge,src,vl);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_x_w_i8mf2_tu(vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf2_tu(merge,src,vl);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_x_w_i8m1_tu(vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m1_tu(merge,src,vl);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_x_w_i8m2_tu(vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m2_tu(merge,src,vl);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_x_w_i8m4_tu(vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m4_tu(merge,src,vl);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_x_w_u8mf8_tu(vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf8_tu(merge,src,vl);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_x_w_u8mf4_tu(vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf4_tu(merge,src,vl);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_x_w_u8mf2_tu(vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf2_tu(merge,src,vl);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_x_w_u8m1_tu(vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m1_tu(merge,src,vl);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_x_w_u8m2_tu(vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m2_tu(merge,src,vl);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_x_w_u8m4_tu(vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m4_tu(merge,src,vl);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_x_w_i16mf4_tu(vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf4_tu(merge,src,vl);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_x_w_i16mf2_tu(vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf2_tu(merge,src,vl);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_x_w_i16m1_tu(vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m1_tu(merge,src,vl);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_x_w_i16m2_tu(vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m2_tu(merge,src,vl);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_x_w_i16m4_tu(vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m4_tu(merge,src,vl);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_x_w_u16mf4_tu(vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf4_tu(merge,src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_x_w_u16mf2_tu(vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf2_tu(merge,src,vl);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_x_w_u16m1_tu(vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m1_tu(merge,src,vl);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_x_w_u16m2_tu(vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m2_tu(merge,src,vl);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_x_w_u16m4_tu(vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m4_tu(merge,src,vl);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_x_w_i32mf2_tu(vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32mf2_tu(merge,src,vl);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_x_w_i32m1_tu(vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m1_tu(merge,src,vl);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_x_w_i32m2_tu(vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m2_tu(merge,src,vl);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_x_w_i32m4_tu(vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m4_tu(merge,src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_x_w_u32mf2_tu(vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32mf2_tu(merge,src,vl);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_x_w_u32m1_tu(vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m1_tu(merge,src,vl);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_x_w_u32m2_tu(vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m2_tu(merge,src,vl);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_x_w_u32m4_tu(vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m4_tu(merge,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tu-2.c
new file mode 100644
index 00000000000..f9fda94e759
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tu-2.c
@@ -0,0 +1,201 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_x_w_i8mf8_tu(vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf8_tu(merge,src,31);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_x_w_i8mf4_tu(vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf4_tu(merge,src,31);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_x_w_i8mf2_tu(vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf2_tu(merge,src,31);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_x_w_i8m1_tu(vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m1_tu(merge,src,31);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_x_w_i8m2_tu(vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m2_tu(merge,src,31);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_x_w_i8m4_tu(vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m4_tu(merge,src,31);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_x_w_u8mf8_tu(vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf8_tu(merge,src,31);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_x_w_u8mf4_tu(vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf4_tu(merge,src,31);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_x_w_u8mf2_tu(vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf2_tu(merge,src,31);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_x_w_u8m1_tu(vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m1_tu(merge,src,31);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_x_w_u8m2_tu(vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m2_tu(merge,src,31);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_x_w_u8m4_tu(vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m4_tu(merge,src,31);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_x_w_i16mf4_tu(vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf4_tu(merge,src,31);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_x_w_i16mf2_tu(vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf2_tu(merge,src,31);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_x_w_i16m1_tu(vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m1_tu(merge,src,31);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_x_w_i16m2_tu(vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m2_tu(merge,src,31);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_x_w_i16m4_tu(vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m4_tu(merge,src,31);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_x_w_u16mf4_tu(vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf4_tu(merge,src,31);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_x_w_u16mf2_tu(vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf2_tu(merge,src,31);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_x_w_u16m1_tu(vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m1_tu(merge,src,31);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_x_w_u16m2_tu(vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m2_tu(merge,src,31);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_x_w_u16m4_tu(vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m4_tu(merge,src,31);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_x_w_i32mf2_tu(vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32mf2_tu(merge,src,31);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_x_w_i32m1_tu(vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m1_tu(merge,src,31);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_x_w_i32m2_tu(vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m2_tu(merge,src,31);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_x_w_i32m4_tu(vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m4_tu(merge,src,31);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_x_w_u32mf2_tu(vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32mf2_tu(merge,src,31);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_x_w_u32m1_tu(vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m1_tu(merge,src,31);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_x_w_u32m2_tu(vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m2_tu(merge,src,31);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_x_w_u32m4_tu(vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m4_tu(merge,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tu-3.c
new file mode 100644
index 00000000000..253ea8adfaa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tu-3.c
@@ -0,0 +1,201 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_x_w_i8mf8_tu(vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf8_tu(merge,src,32);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_x_w_i8mf4_tu(vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf4_tu(merge,src,32);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_x_w_i8mf2_tu(vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf2_tu(merge,src,32);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_x_w_i8m1_tu(vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m1_tu(merge,src,32);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_x_w_i8m2_tu(vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m2_tu(merge,src,32);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_x_w_i8m4_tu(vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m4_tu(merge,src,32);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_x_w_u8mf8_tu(vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf8_tu(merge,src,32);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_x_w_u8mf4_tu(vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf4_tu(merge,src,32);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_x_w_u8mf2_tu(vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf2_tu(merge,src,32);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_x_w_u8m1_tu(vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m1_tu(merge,src,32);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_x_w_u8m2_tu(vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m2_tu(merge,src,32);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_x_w_u8m4_tu(vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m4_tu(merge,src,32);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_x_w_i16mf4_tu(vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf4_tu(merge,src,32);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_x_w_i16mf2_tu(vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf2_tu(merge,src,32);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_x_w_i16m1_tu(vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m1_tu(merge,src,32);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_x_w_i16m2_tu(vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m2_tu(merge,src,32);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_x_w_i16m4_tu(vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m4_tu(merge,src,32);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_x_w_u16mf4_tu(vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf4_tu(merge,src,32);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_x_w_u16mf2_tu(vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf2_tu(merge,src,32);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_x_w_u16m1_tu(vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m1_tu(merge,src,32);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_x_w_u16m2_tu(vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m2_tu(merge,src,32);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_x_w_u16m4_tu(vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m4_tu(merge,src,32);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_x_w_i32mf2_tu(vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32mf2_tu(merge,src,32);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_x_w_i32m1_tu(vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m1_tu(merge,src,32);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_x_w_i32m2_tu(vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m2_tu(merge,src,32);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_x_w_i32m4_tu(vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m4_tu(merge,src,32);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_x_w_u32mf2_tu(vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32mf2_tu(merge,src,32);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_x_w_u32m1_tu(vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m1_tu(merge,src,32);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_x_w_u32m2_tu(vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m2_tu(merge,src,32);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_x_w_u32m4_tu(vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m4_tu(merge,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tum-1.c
new file mode 100644
index 00000000000..caa42ba632b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tum-1.c
@@ -0,0 +1,201 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_x_w_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf8_tum(mask,merge,src,vl);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_x_w_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf4_tum(mask,merge,src,vl);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_x_w_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf2_tum(mask,merge,src,vl);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_x_w_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m1_tum(mask,merge,src,vl);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_x_w_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m2_tum(mask,merge,src,vl);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_x_w_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m4_tum(mask,merge,src,vl);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_x_w_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf8_tum(mask,merge,src,vl);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_x_w_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf4_tum(mask,merge,src,vl);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_x_w_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf2_tum(mask,merge,src,vl);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_x_w_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m1_tum(mask,merge,src,vl);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_x_w_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m2_tum(mask,merge,src,vl);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_x_w_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m4_tum(mask,merge,src,vl);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_x_w_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf4_tum(mask,merge,src,vl);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_x_w_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf2_tum(mask,merge,src,vl);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_x_w_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m1_tum(mask,merge,src,vl);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_x_w_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m2_tum(mask,merge,src,vl);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_x_w_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m4_tum(mask,merge,src,vl);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_x_w_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf4_tum(mask,merge,src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_x_w_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf2_tum(mask,merge,src,vl);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_x_w_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m1_tum(mask,merge,src,vl);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_x_w_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m2_tum(mask,merge,src,vl);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_x_w_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m4_tum(mask,merge,src,vl);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_x_w_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32mf2_tum(mask,merge,src,vl);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_x_w_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m1_tum(mask,merge,src,vl);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_x_w_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m2_tum(mask,merge,src,vl);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_x_w_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m4_tum(mask,merge,src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_x_w_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32mf2_tum(mask,merge,src,vl);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_x_w_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m1_tum(mask,merge,src,vl);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_x_w_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m2_tum(mask,merge,src,vl);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_x_w_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m4_tum(mask,merge,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tum-2.c
new file mode 100644
index 00000000000..430b844f6af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tum-2.c
@@ -0,0 +1,201 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_x_w_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf8_tum(mask,merge,src,31);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_x_w_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf4_tum(mask,merge,src,31);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_x_w_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf2_tum(mask,merge,src,31);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_x_w_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m1_tum(mask,merge,src,31);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_x_w_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m2_tum(mask,merge,src,31);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_x_w_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m4_tum(mask,merge,src,31);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_x_w_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf8_tum(mask,merge,src,31);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_x_w_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf4_tum(mask,merge,src,31);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_x_w_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf2_tum(mask,merge,src,31);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_x_w_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m1_tum(mask,merge,src,31);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_x_w_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m2_tum(mask,merge,src,31);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_x_w_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m4_tum(mask,merge,src,31);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_x_w_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf4_tum(mask,merge,src,31);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_x_w_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf2_tum(mask,merge,src,31);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_x_w_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m1_tum(mask,merge,src,31);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_x_w_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m2_tum(mask,merge,src,31);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_x_w_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m4_tum(mask,merge,src,31);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_x_w_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf4_tum(mask,merge,src,31);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_x_w_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf2_tum(mask,merge,src,31);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_x_w_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m1_tum(mask,merge,src,31);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_x_w_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m2_tum(mask,merge,src,31);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_x_w_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m4_tum(mask,merge,src,31);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_x_w_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32mf2_tum(mask,merge,src,31);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_x_w_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m1_tum(mask,merge,src,31);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_x_w_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m2_tum(mask,merge,src,31);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_x_w_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m4_tum(mask,merge,src,31);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_x_w_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32mf2_tum(mask,merge,src,31);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_x_w_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m1_tum(mask,merge,src,31);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_x_w_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m2_tum(mask,merge,src,31);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_x_w_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m4_tum(mask,merge,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tum-3.c
new file mode 100644
index 00000000000..de314065571
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tum-3.c
@@ -0,0 +1,201 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_x_w_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf8_tum(mask,merge,src,32);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_x_w_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf4_tum(mask,merge,src,32);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_x_w_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf2_tum(mask,merge,src,32);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_x_w_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m1_tum(mask,merge,src,32);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_x_w_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m2_tum(mask,merge,src,32);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_x_w_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m4_tum(mask,merge,src,32);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_x_w_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf8_tum(mask,merge,src,32);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_x_w_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf4_tum(mask,merge,src,32);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_x_w_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf2_tum(mask,merge,src,32);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_x_w_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m1_tum(mask,merge,src,32);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_x_w_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m2_tum(mask,merge,src,32);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_x_w_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m4_tum(mask,merge,src,32);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_x_w_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf4_tum(mask,merge,src,32);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_x_w_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf2_tum(mask,merge,src,32);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_x_w_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m1_tum(mask,merge,src,32);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_x_w_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m2_tum(mask,merge,src,32);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_x_w_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m4_tum(mask,merge,src,32);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_x_w_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf4_tum(mask,merge,src,32);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_x_w_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf2_tum(mask,merge,src,32);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_x_w_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m1_tum(mask,merge,src,32);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_x_w_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m2_tum(mask,merge,src,32);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_x_w_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m4_tum(mask,merge,src,32);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_x_w_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32mf2_tum(mask,merge,src,32);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_x_w_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m1_tum(mask,merge,src,32);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_x_w_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m2_tum(mask,merge,src,32);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_x_w_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m4_tum(mask,merge,src,32);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_x_w_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32mf2_tum(mask,merge,src,32);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_x_w_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m1_tum(mask,merge,src,32);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_x_w_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m2_tum(mask,merge,src,32);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_x_w_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m4_tum(mask,merge,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tumu-1.c
new file mode 100644
index 00000000000..d1ea2c1eb46
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tumu-1.c
@@ -0,0 +1,201 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_x_w_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf8_tumu(mask,merge,src,vl);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_x_w_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf4_tumu(mask,merge,src,vl);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_x_w_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf2_tumu(mask,merge,src,vl);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_x_w_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m1_tumu(mask,merge,src,vl);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_x_w_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m2_tumu(mask,merge,src,vl);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_x_w_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m4_tumu(mask,merge,src,vl);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_x_w_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf8_tumu(mask,merge,src,vl);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_x_w_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf4_tumu(mask,merge,src,vl);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_x_w_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf2_tumu(mask,merge,src,vl);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_x_w_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m1_tumu(mask,merge,src,vl);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_x_w_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m2_tumu(mask,merge,src,vl);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_x_w_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m4_tumu(mask,merge,src,vl);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_x_w_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf4_tumu(mask,merge,src,vl);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_x_w_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf2_tumu(mask,merge,src,vl);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_x_w_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m1_tumu(mask,merge,src,vl);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_x_w_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m2_tumu(mask,merge,src,vl);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_x_w_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m4_tumu(mask,merge,src,vl);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_x_w_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf4_tumu(mask,merge,src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_x_w_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf2_tumu(mask,merge,src,vl);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_x_w_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m1_tumu(mask,merge,src,vl);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_x_w_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m2_tumu(mask,merge,src,vl);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_x_w_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m4_tumu(mask,merge,src,vl);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_x_w_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32mf2_tumu(mask,merge,src,vl);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_x_w_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m1_tumu(mask,merge,src,vl);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_x_w_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m2_tumu(mask,merge,src,vl);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_x_w_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m4_tumu(mask,merge,src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_x_w_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32mf2_tumu(mask,merge,src,vl);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_x_w_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m1_tumu(mask,merge,src,vl);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_x_w_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m2_tumu(mask,merge,src,vl);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_x_w_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m4_tumu(mask,merge,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tumu-2.c
new file mode 100644
index 00000000000..60dd457be5a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tumu-2.c
@@ -0,0 +1,201 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_x_w_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf8_tumu(mask,merge,src,31);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_x_w_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf4_tumu(mask,merge,src,31);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_x_w_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf2_tumu(mask,merge,src,31);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_x_w_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m1_tumu(mask,merge,src,31);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_x_w_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m2_tumu(mask,merge,src,31);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_x_w_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m4_tumu(mask,merge,src,31);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_x_w_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf8_tumu(mask,merge,src,31);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_x_w_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf4_tumu(mask,merge,src,31);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_x_w_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf2_tumu(mask,merge,src,31);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_x_w_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m1_tumu(mask,merge,src,31);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_x_w_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m2_tumu(mask,merge,src,31);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_x_w_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m4_tumu(mask,merge,src,31);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_x_w_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf4_tumu(mask,merge,src,31);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_x_w_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf2_tumu(mask,merge,src,31);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_x_w_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m1_tumu(mask,merge,src,31);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_x_w_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m2_tumu(mask,merge,src,31);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_x_w_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m4_tumu(mask,merge,src,31);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_x_w_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf4_tumu(mask,merge,src,31);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_x_w_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf2_tumu(mask,merge,src,31);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_x_w_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m1_tumu(mask,merge,src,31);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_x_w_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m2_tumu(mask,merge,src,31);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_x_w_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m4_tumu(mask,merge,src,31);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_x_w_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32mf2_tumu(mask,merge,src,31);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_x_w_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m1_tumu(mask,merge,src,31);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_x_w_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m2_tumu(mask,merge,src,31);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_x_w_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m4_tumu(mask,merge,src,31);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_x_w_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32mf2_tumu(mask,merge,src,31);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_x_w_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m1_tumu(mask,merge,src,31);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_x_w_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m2_tumu(mask,merge,src,31);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_x_w_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m4_tumu(mask,merge,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tumu-3.c
new file mode 100644
index 00000000000..745c2cc167d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tumu-3.c
@@ -0,0 +1,201 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_x_w_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf8_tumu(mask,merge,src,32);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_x_w_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf4_tumu(mask,merge,src,32);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_x_w_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8mf2_tumu(mask,merge,src,32);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_x_w_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m1_tumu(mask,merge,src,32);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_x_w_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m2_tumu(mask,merge,src,32);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_x_w_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i8m4_tumu(mask,merge,src,32);
+}
+
+
+vuint8mf8_t test___riscv_vncvt_x_x_w_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf8_tumu(mask,merge,src,32);
+}
+
+
+vuint8mf4_t test___riscv_vncvt_x_x_w_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf4_tumu(mask,merge,src,32);
+}
+
+
+vuint8mf2_t test___riscv_vncvt_x_x_w_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8mf2_tumu(mask,merge,src,32);
+}
+
+
+vuint8m1_t test___riscv_vncvt_x_x_w_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m1_tumu(mask,merge,src,32);
+}
+
+
+vuint8m2_t test___riscv_vncvt_x_x_w_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m2_tumu(mask,merge,src,32);
+}
+
+
+vuint8m4_t test___riscv_vncvt_x_x_w_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u8m4_tumu(mask,merge,src,32);
+}
+
+
+vint16mf4_t test___riscv_vncvt_x_x_w_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf4_tumu(mask,merge,src,32);
+}
+
+
+vint16mf2_t test___riscv_vncvt_x_x_w_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16mf2_tumu(mask,merge,src,32);
+}
+
+
+vint16m1_t test___riscv_vncvt_x_x_w_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m1_tumu(mask,merge,src,32);
+}
+
+
+vint16m2_t test___riscv_vncvt_x_x_w_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m2_tumu(mask,merge,src,32);
+}
+
+
+vint16m4_t test___riscv_vncvt_x_x_w_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i16m4_tumu(mask,merge,src,32);
+}
+
+
+vuint16mf4_t test___riscv_vncvt_x_x_w_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf4_tumu(mask,merge,src,32);
+}
+
+
+vuint16mf2_t test___riscv_vncvt_x_x_w_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16mf2_tumu(mask,merge,src,32);
+}
+
+
+vuint16m1_t test___riscv_vncvt_x_x_w_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m1_tumu(mask,merge,src,32);
+}
+
+
+vuint16m2_t test___riscv_vncvt_x_x_w_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m2_tumu(mask,merge,src,32);
+}
+
+
+vuint16m4_t test___riscv_vncvt_x_x_w_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u16m4_tumu(mask,merge,src,32);
+}
+
+
+vint32mf2_t test___riscv_vncvt_x_x_w_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32mf2_tumu(mask,merge,src,32);
+}
+
+
+vint32m1_t test___riscv_vncvt_x_x_w_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m1_tumu(mask,merge,src,32);
+}
+
+
+vint32m2_t test___riscv_vncvt_x_x_w_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m2_tumu(mask,merge,src,32);
+}
+
+
+vint32m4_t test___riscv_vncvt_x_x_w_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_i32m4_tumu(mask,merge,src,32);
+}
+
+
+vuint32mf2_t test___riscv_vncvt_x_x_w_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32mf2_tumu(mask,merge,src,32);
+}
+
+
+vuint32m1_t test___riscv_vncvt_x_x_w_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m1_tumu(mask,merge,src,32);
+}
+
+
+vuint32m2_t test___riscv_vncvt_x_x_w_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m2_tumu(mask,merge,src,32);
+}
+
+
+vuint32m4_t test___riscv_vncvt_x_x_w_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t src,size_t vl)
+{
+    return __riscv_vncvt_x_x_w_u32m4_tumu(mask,merge,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
