diff mbox series

RISC-V: Add vnsra C API tests

Message ID 20230209215241.23872-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Add vnsra C API tests |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai Feb. 9, 2023, 9:52 p.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/vnsra_wv-1.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wv-2.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wv-3.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wv_m-1.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wv_m-2.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wv_m-3.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wv_mu-1.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wv_mu-2.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wv_mu-3.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wv_tu-1.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wv_tu-2.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wv_tu-3.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wv_tum-1.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wv_tum-2.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wv_tum-3.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wv_tumu-1.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wv_tumu-2.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wv_tumu-3.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wx-1.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wx-2.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wx-3.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wx_m-1.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wx_m-2.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wx_m-3.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wx_mu-1.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wx_mu-2.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wx_mu-3.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wx_tu-1.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wx_tu-2.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wx_tu-3.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wx_tum-1.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wx_tum-2.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wx_tum-3.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wx_tumu-1.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wx_tumu-2.c: New test.
        * gcc.target/riscv/rvv/base/vnsra_wx_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vnsra_wv-1.c    | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wv-2.c    | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wv-3.c    | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wv_m-1.c  | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wv_m-2.c  | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wv_m-3.c  | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wv_mu-1.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wv_mu-2.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wv_mu-3.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wv_tu-1.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wv_tu-2.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wv_tu-3.c | 111 ++++++++++++++++++
 .../riscv/rvv/base/vnsra_wv_tum-1.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vnsra_wv_tum-2.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vnsra_wv_tum-3.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vnsra_wv_tumu-1.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vnsra_wv_tumu-2.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vnsra_wv_tumu-3.c          | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wx-1.c    | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wx-2.c    | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wx-3.c    | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wx_m-1.c  | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wx_m-2.c  | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wx_m-3.c  | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wx_mu-1.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wx_mu-2.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wx_mu-3.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wx_tu-1.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wx_tu-2.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnsra_wx_tu-3.c | 111 ++++++++++++++++++
 .../riscv/rvv/base/vnsra_wx_tum-1.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vnsra_wx_tum-2.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vnsra_wx_tum-3.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vnsra_wx_tumu-1.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vnsra_wx_tumu-2.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vnsra_wx_tumu-3.c          | 111 ++++++++++++++++++
 36 files changed, 3996 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tumu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tumu-3.c
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv-1.c
new file mode 100644
index 00000000000..699d2a41238
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wv_i8mf8(vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf8(op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wv_i8mf4(vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf4(op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wv_i8mf2(vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf2(op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra_wv_i8m1(vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m1(op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra_wv_i8m2(vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m2(op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra_wv_i8m4(vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m4(op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wv_i16mf4(vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf4(op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wv_i16mf2(vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf2(op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra_wv_i16m1(vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m1(op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra_wv_i16m2(vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m2(op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra_wv_i16m4(vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m4(op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wv_i32mf2(vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32mf2(op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra_wv_i32m1(vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m1(op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra_wv_i32m2(vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m2(op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra_wv_i32m4(vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m4(op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv-2.c
new file mode 100644
index 00000000000..8930860ffbd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wv_i8mf8(vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf8(op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wv_i8mf4(vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf4(op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wv_i8mf2(vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf2(op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra_wv_i8m1(vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m1(op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra_wv_i8m2(vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m2(op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra_wv_i8m4(vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m4(op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wv_i16mf4(vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf4(op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wv_i16mf2(vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf2(op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra_wv_i16m1(vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m1(op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra_wv_i16m2(vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m2(op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra_wv_i16m4(vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m4(op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wv_i32mf2(vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32mf2(op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra_wv_i32m1(vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m1(op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra_wv_i32m2(vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m2(op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra_wv_i32m4(vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m4(op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv-3.c
new file mode 100644
index 00000000000..1163624298f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wv_i8mf8(vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf8(op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wv_i8mf4(vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf4(op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wv_i8mf2(vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf2(op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra_wv_i8m1(vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m1(op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra_wv_i8m2(vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m2(op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra_wv_i8m4(vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m4(op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wv_i16mf4(vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf4(op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wv_i16mf2(vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf2(op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra_wv_i16m1(vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m1(op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra_wv_i16m2(vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m2(op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra_wv_i16m4(vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m4(op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wv_i32mf2(vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32mf2(op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra_wv_i32m1(vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m1(op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra_wv_i32m2(vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m2(op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra_wv_i32m4(vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m4(op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_m-1.c
new file mode 100644
index 00000000000..3200a4301da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_m-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wv_i8mf8_m(vbool64_t mask,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf8_m(mask,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wv_i8mf4_m(vbool32_t mask,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf4_m(mask,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wv_i8mf2_m(vbool16_t mask,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf2_m(mask,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra_wv_i8m1_m(vbool8_t mask,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m1_m(mask,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra_wv_i8m2_m(vbool4_t mask,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m2_m(mask,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra_wv_i8m4_m(vbool2_t mask,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m4_m(mask,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wv_i16mf4_m(vbool64_t mask,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf4_m(mask,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wv_i16mf2_m(vbool32_t mask,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf2_m(mask,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra_wv_i16m1_m(vbool16_t mask,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m1_m(mask,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra_wv_i16m2_m(vbool8_t mask,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m2_m(mask,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra_wv_i16m4_m(vbool4_t mask,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m4_m(mask,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wv_i32mf2_m(vbool64_t mask,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32mf2_m(mask,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra_wv_i32m1_m(vbool32_t mask,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m1_m(mask,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra_wv_i32m2_m(vbool16_t mask,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m2_m(mask,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra_wv_i32m4_m(vbool8_t mask,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m4_m(mask,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_m-2.c
new file mode 100644
index 00000000000..7458f3bfedb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_m-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wv_i8mf8_m(vbool64_t mask,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf8_m(mask,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wv_i8mf4_m(vbool32_t mask,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf4_m(mask,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wv_i8mf2_m(vbool16_t mask,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf2_m(mask,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra_wv_i8m1_m(vbool8_t mask,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m1_m(mask,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra_wv_i8m2_m(vbool4_t mask,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m2_m(mask,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra_wv_i8m4_m(vbool2_t mask,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m4_m(mask,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wv_i16mf4_m(vbool64_t mask,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf4_m(mask,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wv_i16mf2_m(vbool32_t mask,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf2_m(mask,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra_wv_i16m1_m(vbool16_t mask,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m1_m(mask,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra_wv_i16m2_m(vbool8_t mask,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m2_m(mask,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra_wv_i16m4_m(vbool4_t mask,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m4_m(mask,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wv_i32mf2_m(vbool64_t mask,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32mf2_m(mask,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra_wv_i32m1_m(vbool32_t mask,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m1_m(mask,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra_wv_i32m2_m(vbool16_t mask,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m2_m(mask,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra_wv_i32m4_m(vbool8_t mask,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m4_m(mask,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_m-3.c
new file mode 100644
index 00000000000..68e8343454f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_m-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wv_i8mf8_m(vbool64_t mask,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf8_m(mask,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wv_i8mf4_m(vbool32_t mask,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf4_m(mask,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wv_i8mf2_m(vbool16_t mask,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf2_m(mask,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra_wv_i8m1_m(vbool8_t mask,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m1_m(mask,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra_wv_i8m2_m(vbool4_t mask,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m2_m(mask,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra_wv_i8m4_m(vbool2_t mask,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m4_m(mask,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wv_i16mf4_m(vbool64_t mask,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf4_m(mask,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wv_i16mf2_m(vbool32_t mask,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf2_m(mask,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra_wv_i16m1_m(vbool16_t mask,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m1_m(mask,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra_wv_i16m2_m(vbool8_t mask,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m2_m(mask,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra_wv_i16m4_m(vbool4_t mask,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m4_m(mask,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wv_i32mf2_m(vbool64_t mask,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32mf2_m(mask,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra_wv_i32m1_m(vbool32_t mask,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m1_m(mask,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra_wv_i32m2_m(vbool16_t mask,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m2_m(mask,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra_wv_i32m4_m(vbool8_t mask,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m4_m(mask,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_mu-1.c
new file mode 100644
index 00000000000..df60811e0f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_mu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wv_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf8_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wv_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wv_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra_wv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra_wv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra_wv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra_wv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra_wv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra_wv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra_wv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra_wv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra_wv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_mu-2.c
new file mode 100644
index 00000000000..ff6e2e3fdac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_mu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wv_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf8_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wv_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wv_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra_wv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra_wv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra_wv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra_wv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra_wv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra_wv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra_wv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra_wv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra_wv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m4_mu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_mu-3.c
new file mode 100644
index 00000000000..8d749b57f2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_mu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wv_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf8_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wv_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wv_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra_wv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra_wv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra_wv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra_wv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra_wv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra_wv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra_wv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra_wv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra_wv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m4_mu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tu-1.c
new file mode 100644
index 00000000000..ca3e963647d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wv_i8mf8_tu(vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf8_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wv_i8mf4_tu(vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf4_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wv_i8mf2_tu(vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf2_tu(merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra_wv_i8m1_tu(vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m1_tu(merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra_wv_i8m2_tu(vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m2_tu(merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra_wv_i8m4_tu(vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m4_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wv_i16mf4_tu(vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf4_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wv_i16mf2_tu(vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf2_tu(merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra_wv_i16m1_tu(vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m1_tu(merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra_wv_i16m2_tu(vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m2_tu(merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra_wv_i16m4_tu(vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m4_tu(merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wv_i32mf2_tu(vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32mf2_tu(merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra_wv_i32m1_tu(vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m1_tu(merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra_wv_i32m2_tu(vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m2_tu(merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra_wv_i32m4_tu(vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m4_tu(merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tu-2.c
new file mode 100644
index 00000000000..319e0c580fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wv_i8mf8_tu(vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf8_tu(merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wv_i8mf4_tu(vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf4_tu(merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wv_i8mf2_tu(vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf2_tu(merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra_wv_i8m1_tu(vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m1_tu(merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra_wv_i8m2_tu(vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m2_tu(merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra_wv_i8m4_tu(vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m4_tu(merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wv_i16mf4_tu(vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf4_tu(merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wv_i16mf2_tu(vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf2_tu(merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra_wv_i16m1_tu(vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m1_tu(merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra_wv_i16m2_tu(vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m2_tu(merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra_wv_i16m4_tu(vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m4_tu(merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wv_i32mf2_tu(vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32mf2_tu(merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra_wv_i32m1_tu(vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m1_tu(merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra_wv_i32m2_tu(vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m2_tu(merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra_wv_i32m4_tu(vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m4_tu(merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tu-3.c
new file mode 100644
index 00000000000..b17eec2b8d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wv_i8mf8_tu(vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf8_tu(merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wv_i8mf4_tu(vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf4_tu(merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wv_i8mf2_tu(vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf2_tu(merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra_wv_i8m1_tu(vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m1_tu(merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra_wv_i8m2_tu(vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m2_tu(merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra_wv_i8m4_tu(vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m4_tu(merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wv_i16mf4_tu(vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf4_tu(merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wv_i16mf2_tu(vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf2_tu(merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra_wv_i16m1_tu(vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m1_tu(merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra_wv_i16m2_tu(vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m2_tu(merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra_wv_i16m4_tu(vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m4_tu(merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wv_i32mf2_tu(vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32mf2_tu(merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra_wv_i32m1_tu(vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m1_tu(merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra_wv_i32m2_tu(vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m2_tu(merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra_wv_i32m4_tu(vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m4_tu(merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tum-1.c
new file mode 100644
index 00000000000..d41f41f9361
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tum-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wv_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf8_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wv_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wv_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra_wv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra_wv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra_wv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra_wv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra_wv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra_wv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra_wv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra_wv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra_wv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tum-2.c
new file mode 100644
index 00000000000..ad396d664b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tum-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wv_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf8_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wv_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wv_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra_wv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra_wv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra_wv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra_wv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra_wv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra_wv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra_wv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra_wv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra_wv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m4_tum(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tum-3.c
new file mode 100644
index 00000000000..c7078da01b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tum-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wv_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf8_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wv_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wv_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra_wv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra_wv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra_wv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra_wv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra_wv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra_wv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra_wv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra_wv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra_wv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m4_tum(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tumu-1.c
new file mode 100644
index 00000000000..e82fa2f576b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tumu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wv_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf8_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wv_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wv_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra_wv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra_wv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra_wv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra_wv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra_wv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra_wv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra_wv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra_wv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra_wv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tumu-2.c
new file mode 100644
index 00000000000..89a8361be94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tumu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wv_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf8_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wv_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wv_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra_wv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra_wv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra_wv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra_wv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra_wv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra_wv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra_wv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra_wv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra_wv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tumu-3.c
new file mode 100644
index 00000000000..2805fa3edab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tumu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wv_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,vuint8mf8_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf8_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wv_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,vuint8mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wv_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,vuint8mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra_wv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,vuint8m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra_wv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,vuint8m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra_wv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,vuint8m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i8m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,vuint16mf4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,vuint16mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra_wv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,vuint16m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra_wv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,vuint16m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra_wv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,vuint16m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i16m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,vuint32mf2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra_wv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,vuint32m1_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra_wv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,vuint32m2_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra_wv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,vuint32m4_t shift,size_t vl)
+{
+    return __riscv_vnsra_wv_i32m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsra\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx-1.c
new file mode 100644
index 00000000000..9d73d3ca177
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wx_i8mf8(vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf8(op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wx_i8mf4(vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf4(op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wx_i8mf2(vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf2(op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra_wx_i8m1(vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m1(op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra_wx_i8m2(vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m2(op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra_wx_i8m4(vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m4(op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wx_i16mf4(vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf4(op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wx_i16mf2(vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf2(op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra_wx_i16m1(vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m1(op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra_wx_i16m2(vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m2(op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra_wx_i16m4(vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m4(op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wx_i32mf2(vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32mf2(op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra_wx_i32m1(vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m1(op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra_wx_i32m2(vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m2(op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra_wx_i32m4(vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m4(op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx-2.c
new file mode 100644
index 00000000000..a6427748146
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wx_i8mf8(vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf8(op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wx_i8mf4(vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf4(op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wx_i8mf2(vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf2(op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra_wx_i8m1(vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m1(op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra_wx_i8m2(vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m2(op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra_wx_i8m4(vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m4(op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wx_i16mf4(vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf4(op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wx_i16mf2(vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf2(op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra_wx_i16m1(vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m1(op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra_wx_i16m2(vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m2(op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra_wx_i16m4(vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m4(op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wx_i32mf2(vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32mf2(op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra_wx_i32m1(vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m1(op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra_wx_i32m2(vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m2(op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra_wx_i32m4(vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m4(op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx-3.c
new file mode 100644
index 00000000000..6a136972095
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wx_i8mf8(vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf8(op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wx_i8mf4(vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf4(op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wx_i8mf2(vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf2(op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra_wx_i8m1(vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m1(op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra_wx_i8m2(vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m2(op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra_wx_i8m4(vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m4(op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wx_i16mf4(vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf4(op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wx_i16mf2(vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf2(op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra_wx_i16m1(vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m1(op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra_wx_i16m2(vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m2(op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra_wx_i16m4(vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m4(op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wx_i32mf2(vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32mf2(op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra_wx_i32m1(vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m1(op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra_wx_i32m2(vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m2(op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra_wx_i32m4(vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m4(op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_m-1.c
new file mode 100644
index 00000000000..a960228bdf7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_m-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wx_i8mf8_m(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf8_m(mask,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wx_i8mf4_m(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf4_m(mask,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wx_i8mf2_m(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf2_m(mask,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra_wx_i8m1_m(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m1_m(mask,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra_wx_i8m2_m(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m2_m(mask,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra_wx_i8m4_m(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m4_m(mask,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wx_i16mf4_m(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf4_m(mask,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wx_i16mf2_m(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf2_m(mask,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra_wx_i16m1_m(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m1_m(mask,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra_wx_i16m2_m(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m2_m(mask,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra_wx_i16m4_m(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m4_m(mask,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wx_i32mf2_m(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32mf2_m(mask,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra_wx_i32m1_m(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m1_m(mask,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra_wx_i32m2_m(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m2_m(mask,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra_wx_i32m4_m(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m4_m(mask,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_m-2.c
new file mode 100644
index 00000000000..64ee422857b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_m-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wx_i8mf8_m(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf8_m(mask,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wx_i8mf4_m(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf4_m(mask,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wx_i8mf2_m(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf2_m(mask,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra_wx_i8m1_m(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m1_m(mask,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra_wx_i8m2_m(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m2_m(mask,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra_wx_i8m4_m(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m4_m(mask,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wx_i16mf4_m(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf4_m(mask,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wx_i16mf2_m(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf2_m(mask,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra_wx_i16m1_m(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m1_m(mask,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra_wx_i16m2_m(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m2_m(mask,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra_wx_i16m4_m(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m4_m(mask,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wx_i32mf2_m(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32mf2_m(mask,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra_wx_i32m1_m(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m1_m(mask,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra_wx_i32m2_m(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m2_m(mask,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra_wx_i32m4_m(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m4_m(mask,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_m-3.c
new file mode 100644
index 00000000000..1fb8b431540
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_m-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wx_i8mf8_m(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf8_m(mask,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wx_i8mf4_m(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf4_m(mask,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wx_i8mf2_m(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf2_m(mask,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra_wx_i8m1_m(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m1_m(mask,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra_wx_i8m2_m(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m2_m(mask,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra_wx_i8m4_m(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m4_m(mask,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wx_i16mf4_m(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf4_m(mask,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wx_i16mf2_m(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf2_m(mask,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra_wx_i16m1_m(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m1_m(mask,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra_wx_i16m2_m(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m2_m(mask,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra_wx_i16m4_m(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m4_m(mask,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wx_i32mf2_m(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32mf2_m(mask,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra_wx_i32m1_m(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m1_m(mask,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra_wx_i32m2_m(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m2_m(mask,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra_wx_i32m4_m(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m4_m(mask,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_mu-1.c
new file mode 100644
index 00000000000..4d0a3cb4c1d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_mu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf8_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra_wx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra_wx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra_wx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra_wx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra_wx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra_wx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra_wx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra_wx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra_wx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_mu-2.c
new file mode 100644
index 00000000000..b4ffd402af6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_mu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf8_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra_wx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra_wx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra_wx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra_wx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra_wx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra_wx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra_wx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra_wx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra_wx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m4_mu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_mu-3.c
new file mode 100644
index 00000000000..3e7f8d78ef8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_mu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf8_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra_wx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra_wx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra_wx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra_wx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra_wx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra_wx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra_wx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra_wx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra_wx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m4_mu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tu-1.c
new file mode 100644
index 00000000000..02380fad466
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wx_i8mf8_tu(vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf8_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wx_i8mf4_tu(vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf4_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wx_i8mf2_tu(vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf2_tu(merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra_wx_i8m1_tu(vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m1_tu(merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra_wx_i8m2_tu(vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m2_tu(merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra_wx_i8m4_tu(vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m4_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wx_i16mf4_tu(vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf4_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wx_i16mf2_tu(vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf2_tu(merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra_wx_i16m1_tu(vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m1_tu(merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra_wx_i16m2_tu(vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m2_tu(merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra_wx_i16m4_tu(vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m4_tu(merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wx_i32mf2_tu(vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32mf2_tu(merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra_wx_i32m1_tu(vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m1_tu(merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra_wx_i32m2_tu(vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m2_tu(merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra_wx_i32m4_tu(vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m4_tu(merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tu-2.c
new file mode 100644
index 00000000000..873ba05fc33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wx_i8mf8_tu(vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf8_tu(merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wx_i8mf4_tu(vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf4_tu(merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wx_i8mf2_tu(vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf2_tu(merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra_wx_i8m1_tu(vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m1_tu(merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra_wx_i8m2_tu(vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m2_tu(merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra_wx_i8m4_tu(vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m4_tu(merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wx_i16mf4_tu(vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf4_tu(merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wx_i16mf2_tu(vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf2_tu(merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra_wx_i16m1_tu(vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m1_tu(merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra_wx_i16m2_tu(vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m2_tu(merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra_wx_i16m4_tu(vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m4_tu(merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wx_i32mf2_tu(vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32mf2_tu(merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra_wx_i32m1_tu(vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m1_tu(merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra_wx_i32m2_tu(vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m2_tu(merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra_wx_i32m4_tu(vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m4_tu(merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tu-3.c
new file mode 100644
index 00000000000..8c3abbdd606
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wx_i8mf8_tu(vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf8_tu(merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wx_i8mf4_tu(vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf4_tu(merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wx_i8mf2_tu(vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf2_tu(merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra_wx_i8m1_tu(vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m1_tu(merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra_wx_i8m2_tu(vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m2_tu(merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra_wx_i8m4_tu(vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m4_tu(merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wx_i16mf4_tu(vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf4_tu(merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wx_i16mf2_tu(vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf2_tu(merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra_wx_i16m1_tu(vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m1_tu(merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra_wx_i16m2_tu(vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m2_tu(merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra_wx_i16m4_tu(vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m4_tu(merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wx_i32mf2_tu(vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32mf2_tu(merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra_wx_i32m1_tu(vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m1_tu(merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra_wx_i32m2_tu(vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m2_tu(merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra_wx_i32m4_tu(vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m4_tu(merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tum-1.c
new file mode 100644
index 00000000000..49996e05102
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tum-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf8_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra_wx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra_wx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra_wx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra_wx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra_wx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra_wx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra_wx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra_wx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra_wx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tum-2.c
new file mode 100644
index 00000000000..dff3b3ea728
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tum-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf8_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra_wx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra_wx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra_wx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra_wx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra_wx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra_wx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra_wx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra_wx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra_wx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m4_tum(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tum-3.c
new file mode 100644
index 00000000000..ebbc13decdc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tum-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf8_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra_wx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra_wx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra_wx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra_wx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra_wx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra_wx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra_wx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra_wx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra_wx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m4_tum(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tumu-1.c
new file mode 100644
index 00000000000..1471ddf2d77
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tumu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf8_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vnsra_wx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vnsra_wx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vnsra_wx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vnsra_wx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vnsra_wx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vnsra_wx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vnsra_wx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vnsra_wx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vnsra_wx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tumu-2.c
new file mode 100644
index 00000000000..d594e43c151
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tumu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf8_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vnsra_wx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vnsra_wx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vnsra_wx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vnsra_wx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vnsra_wx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vnsra_wx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vnsra_wx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vnsra_wx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vnsra_wx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tumu-3.c
new file mode 100644
index 00000000000..85b3935f886
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tumu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnsra_wx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf8_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vnsra_wx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vnsra_wx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vnsra_wx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vnsra_wx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vnsra_wx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i8m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vnsra_wx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vnsra_wx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vnsra_wx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vnsra_wx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vnsra_wx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i16m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vnsra_wx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vnsra_wx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vnsra_wx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vnsra_wx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vnsra_wx_i32m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsra\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */