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To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vnsrl C API tests Date: Fri, 10 Feb 2023 05:50:19 +0800 Message-Id: <20230209215019.22674-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757391858677052749?= X-GMAIL-MSGID: =?utf-8?q?1757391858677052749?= From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vnsrl_wv-1.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wv-2.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wv-3.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wv_m-1.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wv_m-2.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wv_m-3.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wv_mu-1.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wv_mu-2.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wv_mu-3.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wv_tu-1.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wv_tu-2.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wv_tu-3.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wv_tum-1.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wv_tum-2.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wv_tum-3.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wv_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wv_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wv_tumu-3.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wx-1.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wx-2.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wx-3.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wx_m-1.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wx_m-2.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wx_m-3.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wx_mu-1.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wx_mu-2.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wx_mu-3.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wx_tu-1.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wx_tu-2.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wx_tu-3.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wx_tum-1.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wx_tum-2.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wx_tum-3.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wx_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wx_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vnsrl_wx_tumu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vnsrl_wv-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wv-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wv-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_m-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_m-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_m-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_mu-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_mu-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_mu-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tu-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tu-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wv_tu-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vnsrl_wv_tum-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vnsrl_wv_tum-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vnsrl_wv_tum-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vnsrl_wv_tumu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vnsrl_wv_tumu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vnsrl_wv_tumu-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wx-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wx-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wx-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_m-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_m-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_m-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_mu-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_mu-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_mu-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tu-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tu-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vnsrl_wx_tu-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vnsrl_wx_tum-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vnsrl_wx_tum-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vnsrl_wx_tum-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vnsrl_wx_tumu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vnsrl_wx_tumu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vnsrl_wx_tumu-3.c | 111 ++++++++++++++++++ 36 files changed, 3996 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tumu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv-1.c new file mode 100644 index 00000000000..abe2e915f12 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wv_u8mf8(vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf8(op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl_wv_u8mf4(vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf4(op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl_wv_u8mf2(vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf2(op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl_wv_u8m1(vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m1(op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl_wv_u8m2(vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m2(op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl_wv_u8m4(vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m4(op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl_wv_u16mf4(vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf4(op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl_wv_u16mf2(vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf2(op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl_wv_u16m1(vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m1(op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl_wv_u16m2(vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m2(op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl_wv_u16m4(vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m4(op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl_wv_u32mf2(vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32mf2(op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl_wv_u32m1(vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m1(op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl_wv_u32m2(vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m2(op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl_wv_u32m4(vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m4(op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv-2.c new file mode 100644 index 00000000000..c367187dcca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wv_u8mf8(vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf8(op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl_wv_u8mf4(vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf4(op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl_wv_u8mf2(vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf2(op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl_wv_u8m1(vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m1(op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl_wv_u8m2(vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m2(op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl_wv_u8m4(vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m4(op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl_wv_u16mf4(vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf4(op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl_wv_u16mf2(vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf2(op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl_wv_u16m1(vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m1(op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl_wv_u16m2(vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m2(op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl_wv_u16m4(vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m4(op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl_wv_u32mf2(vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32mf2(op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl_wv_u32m1(vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m1(op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl_wv_u32m2(vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m2(op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl_wv_u32m4(vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m4(op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv-3.c new file mode 100644 index 00000000000..fbf98ef83c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wv_u8mf8(vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf8(op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl_wv_u8mf4(vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf4(op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl_wv_u8mf2(vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf2(op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl_wv_u8m1(vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m1(op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl_wv_u8m2(vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m2(op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl_wv_u8m4(vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m4(op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl_wv_u16mf4(vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf4(op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl_wv_u16mf2(vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf2(op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl_wv_u16m1(vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m1(op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl_wv_u16m2(vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m2(op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl_wv_u16m4(vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m4(op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl_wv_u32mf2(vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32mf2(op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl_wv_u32m1(vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m1(op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl_wv_u32m2(vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m2(op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl_wv_u32m4(vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m4(op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_m-1.c new file mode 100644 index 00000000000..8eaeec9a060 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wv_u8mf8_m(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf8_m(mask,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl_wv_u8mf4_m(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf4_m(mask,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl_wv_u8mf2_m(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf2_m(mask,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl_wv_u8m1_m(vbool8_t mask,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m1_m(mask,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl_wv_u8m2_m(vbool4_t mask,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m2_m(mask,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl_wv_u8m4_m(vbool2_t mask,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m4_m(mask,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl_wv_u16mf4_m(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf4_m(mask,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl_wv_u16mf2_m(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf2_m(mask,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl_wv_u16m1_m(vbool16_t mask,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m1_m(mask,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl_wv_u16m2_m(vbool8_t mask,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m2_m(mask,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl_wv_u16m4_m(vbool4_t mask,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m4_m(mask,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl_wv_u32mf2_m(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32mf2_m(mask,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl_wv_u32m1_m(vbool32_t mask,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m1_m(mask,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl_wv_u32m2_m(vbool16_t mask,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m2_m(mask,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl_wv_u32m4_m(vbool8_t mask,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m4_m(mask,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_m-2.c new file mode 100644 index 00000000000..fce5b84483a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wv_u8mf8_m(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf8_m(mask,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl_wv_u8mf4_m(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf4_m(mask,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl_wv_u8mf2_m(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf2_m(mask,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl_wv_u8m1_m(vbool8_t mask,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m1_m(mask,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl_wv_u8m2_m(vbool4_t mask,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m2_m(mask,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl_wv_u8m4_m(vbool2_t mask,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m4_m(mask,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl_wv_u16mf4_m(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf4_m(mask,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl_wv_u16mf2_m(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf2_m(mask,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl_wv_u16m1_m(vbool16_t mask,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m1_m(mask,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl_wv_u16m2_m(vbool8_t mask,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m2_m(mask,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl_wv_u16m4_m(vbool4_t mask,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m4_m(mask,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl_wv_u32mf2_m(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32mf2_m(mask,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl_wv_u32m1_m(vbool32_t mask,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m1_m(mask,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl_wv_u32m2_m(vbool16_t mask,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m2_m(mask,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl_wv_u32m4_m(vbool8_t mask,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m4_m(mask,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_m-3.c new file mode 100644 index 00000000000..f4297527bf0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wv_u8mf8_m(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf8_m(mask,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl_wv_u8mf4_m(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf4_m(mask,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl_wv_u8mf2_m(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf2_m(mask,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl_wv_u8m1_m(vbool8_t mask,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m1_m(mask,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl_wv_u8m2_m(vbool4_t mask,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m2_m(mask,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl_wv_u8m4_m(vbool2_t mask,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m4_m(mask,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl_wv_u16mf4_m(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf4_m(mask,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl_wv_u16mf2_m(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf2_m(mask,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl_wv_u16m1_m(vbool16_t mask,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m1_m(mask,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl_wv_u16m2_m(vbool8_t mask,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m2_m(mask,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl_wv_u16m4_m(vbool4_t mask,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m4_m(mask,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl_wv_u32mf2_m(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32mf2_m(mask,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl_wv_u32m1_m(vbool32_t mask,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m1_m(mask,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl_wv_u32m2_m(vbool16_t mask,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m2_m(mask,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl_wv_u32m4_m(vbool8_t mask,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m4_m(mask,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_mu-1.c new file mode 100644 index 00000000000..73c5777f2b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf8_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl_wv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf4_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl_wv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf2_mu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl_wv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m1_mu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl_wv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m2_mu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl_wv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m4_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl_wv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf4_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl_wv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf2_mu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl_wv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m1_mu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl_wv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m2_mu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl_wv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m4_mu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl_wv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32mf2_mu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl_wv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m1_mu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl_wv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m2_mu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl_wv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m4_mu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_mu-2.c new file mode 100644 index 00000000000..14b96d02163 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf8_mu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl_wv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf4_mu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl_wv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf2_mu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl_wv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m1_mu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl_wv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m2_mu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl_wv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m4_mu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl_wv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf4_mu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl_wv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf2_mu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl_wv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m1_mu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl_wv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m2_mu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl_wv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m4_mu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl_wv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32mf2_mu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl_wv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m1_mu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl_wv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m2_mu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl_wv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m4_mu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_mu-3.c new file mode 100644 index 00000000000..f8121f09a37 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf8_mu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl_wv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf4_mu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl_wv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf2_mu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl_wv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m1_mu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl_wv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m2_mu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl_wv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m4_mu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl_wv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf4_mu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl_wv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf2_mu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl_wv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m1_mu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl_wv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m2_mu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl_wv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m4_mu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl_wv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32mf2_mu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl_wv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m1_mu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl_wv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m2_mu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl_wv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m4_mu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tu-1.c new file mode 100644 index 00000000000..0ae9535523c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wv_u8mf8_tu(vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf8_tu(merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl_wv_u8mf4_tu(vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf4_tu(merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl_wv_u8mf2_tu(vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf2_tu(merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl_wv_u8m1_tu(vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m1_tu(merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl_wv_u8m2_tu(vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m2_tu(merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl_wv_u8m4_tu(vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m4_tu(merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl_wv_u16mf4_tu(vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf4_tu(merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl_wv_u16mf2_tu(vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf2_tu(merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl_wv_u16m1_tu(vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m1_tu(merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl_wv_u16m2_tu(vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m2_tu(merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl_wv_u16m4_tu(vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m4_tu(merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl_wv_u32mf2_tu(vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32mf2_tu(merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl_wv_u32m1_tu(vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m1_tu(merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl_wv_u32m2_tu(vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m2_tu(merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl_wv_u32m4_tu(vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m4_tu(merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tu-2.c new file mode 100644 index 00000000000..2222c79ef51 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wv_u8mf8_tu(vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf8_tu(merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl_wv_u8mf4_tu(vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf4_tu(merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl_wv_u8mf2_tu(vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf2_tu(merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl_wv_u8m1_tu(vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m1_tu(merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl_wv_u8m2_tu(vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m2_tu(merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl_wv_u8m4_tu(vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m4_tu(merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl_wv_u16mf4_tu(vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf4_tu(merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl_wv_u16mf2_tu(vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf2_tu(merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl_wv_u16m1_tu(vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m1_tu(merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl_wv_u16m2_tu(vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m2_tu(merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl_wv_u16m4_tu(vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m4_tu(merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl_wv_u32mf2_tu(vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32mf2_tu(merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl_wv_u32m1_tu(vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m1_tu(merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl_wv_u32m2_tu(vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m2_tu(merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl_wv_u32m4_tu(vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m4_tu(merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tu-3.c new file mode 100644 index 00000000000..e67b7bbf51c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wv_u8mf8_tu(vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf8_tu(merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl_wv_u8mf4_tu(vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf4_tu(merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl_wv_u8mf2_tu(vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf2_tu(merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl_wv_u8m1_tu(vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m1_tu(merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl_wv_u8m2_tu(vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m2_tu(merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl_wv_u8m4_tu(vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m4_tu(merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl_wv_u16mf4_tu(vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf4_tu(merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl_wv_u16mf2_tu(vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf2_tu(merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl_wv_u16m1_tu(vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m1_tu(merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl_wv_u16m2_tu(vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m2_tu(merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl_wv_u16m4_tu(vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m4_tu(merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl_wv_u32mf2_tu(vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32mf2_tu(merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl_wv_u32m1_tu(vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m1_tu(merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl_wv_u32m2_tu(vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m2_tu(merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl_wv_u32m4_tu(vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m4_tu(merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tum-1.c new file mode 100644 index 00000000000..faf173209ed --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf8_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl_wv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf4_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl_wv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf2_tum(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl_wv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m1_tum(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl_wv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m2_tum(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl_wv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m4_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl_wv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf4_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl_wv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf2_tum(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl_wv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m1_tum(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl_wv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m2_tum(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl_wv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m4_tum(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl_wv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32mf2_tum(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl_wv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m1_tum(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl_wv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m2_tum(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl_wv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m4_tum(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tum-2.c new file mode 100644 index 00000000000..e2465057aa9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf8_tum(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl_wv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf4_tum(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl_wv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf2_tum(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl_wv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m1_tum(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl_wv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m2_tum(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl_wv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m4_tum(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl_wv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf4_tum(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl_wv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf2_tum(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl_wv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m1_tum(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl_wv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m2_tum(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl_wv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m4_tum(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl_wv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32mf2_tum(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl_wv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m1_tum(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl_wv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m2_tum(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl_wv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m4_tum(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tum-3.c new file mode 100644 index 00000000000..1f9794d3351 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf8_tum(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl_wv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf4_tum(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl_wv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf2_tum(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl_wv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m1_tum(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl_wv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m2_tum(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl_wv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m4_tum(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl_wv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf4_tum(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl_wv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf2_tum(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl_wv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m1_tum(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl_wv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m2_tum(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl_wv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m4_tum(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl_wv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32mf2_tum(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl_wv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m1_tum(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl_wv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m2_tum(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl_wv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m4_tum(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tumu-1.c new file mode 100644 index 00000000000..b7602f948cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf8_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl_wv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf4_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl_wv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf2_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl_wv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m1_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl_wv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m2_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl_wv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m4_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl_wv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf4_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl_wv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf2_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl_wv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m1_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl_wv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m2_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl_wv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m4_tumu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl_wv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32mf2_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl_wv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m1_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl_wv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m2_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl_wv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m4_tumu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tumu-2.c new file mode 100644 index 00000000000..0931afbfba0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf8_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl_wv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf4_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl_wv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf2_tumu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl_wv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m1_tumu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl_wv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m2_tumu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl_wv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m4_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl_wv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf4_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl_wv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf2_tumu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl_wv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m1_tumu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl_wv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m2_tumu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl_wv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m4_tumu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl_wv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32mf2_tumu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl_wv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m1_tumu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl_wv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m2_tumu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl_wv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m4_tumu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tumu-3.c new file mode 100644 index 00000000000..46fdcc2fc63 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf8_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl_wv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf4_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl_wv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8mf2_tumu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl_wv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m1_tumu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl_wv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m2_tumu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl_wv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u8m4_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl_wv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf4_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl_wv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16mf2_tumu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl_wv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m1_tumu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl_wv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m2_tumu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl_wv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u16m4_tumu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl_wv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32mf2_tumu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl_wv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m1_tumu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl_wv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m2_tumu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl_wv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_wv_u32m4_tumu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx-1.c new file mode 100644 index 00000000000..f968df3db62 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wx_u8mf8(vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf8(op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl_wx_u8mf4(vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf4(op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl_wx_u8mf2(vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf2(op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl_wx_u8m1(vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m1(op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl_wx_u8m2(vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m2(op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl_wx_u8m4(vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m4(op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl_wx_u16mf4(vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf4(op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl_wx_u16mf2(vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf2(op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl_wx_u16m1(vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m1(op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl_wx_u16m2(vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m2(op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl_wx_u16m4(vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m4(op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl_wx_u32mf2(vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32mf2(op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl_wx_u32m1(vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m1(op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl_wx_u32m2(vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m2(op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl_wx_u32m4(vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m4(op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx-2.c new file mode 100644 index 00000000000..721298a9ea6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wx_u8mf8(vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf8(op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl_wx_u8mf4(vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf4(op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl_wx_u8mf2(vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf2(op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl_wx_u8m1(vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m1(op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl_wx_u8m2(vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m2(op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl_wx_u8m4(vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m4(op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl_wx_u16mf4(vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf4(op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl_wx_u16mf2(vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf2(op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl_wx_u16m1(vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m1(op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl_wx_u16m2(vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m2(op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl_wx_u16m4(vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m4(op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl_wx_u32mf2(vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32mf2(op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl_wx_u32m1(vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m1(op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl_wx_u32m2(vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m2(op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl_wx_u32m4(vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m4(op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx-3.c new file mode 100644 index 00000000000..31288de68c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wx_u8mf8(vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf8(op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl_wx_u8mf4(vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf4(op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl_wx_u8mf2(vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf2(op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl_wx_u8m1(vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m1(op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl_wx_u8m2(vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m2(op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl_wx_u8m4(vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m4(op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl_wx_u16mf4(vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf4(op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl_wx_u16mf2(vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf2(op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl_wx_u16m1(vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m1(op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl_wx_u16m2(vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m2(op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl_wx_u16m4(vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m4(op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl_wx_u32mf2(vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32mf2(op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl_wx_u32m1(vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m1(op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl_wx_u32m2(vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m2(op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl_wx_u32m4(vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m4(op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_m-1.c new file mode 100644 index 00000000000..c31830983e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wx_u8mf8_m(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf8_m(mask,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl_wx_u8mf4_m(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf4_m(mask,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl_wx_u8mf2_m(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf2_m(mask,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl_wx_u8m1_m(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m1_m(mask,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl_wx_u8m2_m(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m2_m(mask,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl_wx_u8m4_m(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m4_m(mask,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl_wx_u16mf4_m(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf4_m(mask,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl_wx_u16mf2_m(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf2_m(mask,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl_wx_u16m1_m(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m1_m(mask,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl_wx_u16m2_m(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m2_m(mask,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl_wx_u16m4_m(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m4_m(mask,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl_wx_u32mf2_m(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32mf2_m(mask,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl_wx_u32m1_m(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m1_m(mask,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl_wx_u32m2_m(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m2_m(mask,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl_wx_u32m4_m(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m4_m(mask,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_m-2.c new file mode 100644 index 00000000000..e9a406e3a02 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wx_u8mf8_m(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf8_m(mask,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl_wx_u8mf4_m(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf4_m(mask,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl_wx_u8mf2_m(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf2_m(mask,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl_wx_u8m1_m(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m1_m(mask,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl_wx_u8m2_m(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m2_m(mask,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl_wx_u8m4_m(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m4_m(mask,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl_wx_u16mf4_m(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf4_m(mask,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl_wx_u16mf2_m(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf2_m(mask,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl_wx_u16m1_m(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m1_m(mask,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl_wx_u16m2_m(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m2_m(mask,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl_wx_u16m4_m(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m4_m(mask,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl_wx_u32mf2_m(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32mf2_m(mask,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl_wx_u32m1_m(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m1_m(mask,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl_wx_u32m2_m(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m2_m(mask,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl_wx_u32m4_m(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m4_m(mask,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_m-3.c new file mode 100644 index 00000000000..f70df999e41 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wx_u8mf8_m(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf8_m(mask,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl_wx_u8mf4_m(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf4_m(mask,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl_wx_u8mf2_m(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf2_m(mask,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl_wx_u8m1_m(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m1_m(mask,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl_wx_u8m2_m(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m2_m(mask,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl_wx_u8m4_m(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m4_m(mask,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl_wx_u16mf4_m(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf4_m(mask,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl_wx_u16mf2_m(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf2_m(mask,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl_wx_u16m1_m(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m1_m(mask,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl_wx_u16m2_m(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m2_m(mask,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl_wx_u16m4_m(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m4_m(mask,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl_wx_u32mf2_m(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32mf2_m(mask,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl_wx_u32m1_m(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m1_m(mask,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl_wx_u32m2_m(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m2_m(mask,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl_wx_u32m4_m(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m4_m(mask,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_mu-1.c new file mode 100644 index 00000000000..ee84402383c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf8_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl_wx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf4_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl_wx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf2_mu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl_wx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m1_mu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl_wx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m2_mu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl_wx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m4_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl_wx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf4_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl_wx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf2_mu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl_wx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m1_mu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl_wx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m2_mu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl_wx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m4_mu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl_wx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32mf2_mu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl_wx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m1_mu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl_wx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m2_mu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl_wx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m4_mu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_mu-2.c new file mode 100644 index 00000000000..ee0fba8789e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf8_mu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl_wx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf4_mu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl_wx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf2_mu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl_wx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m1_mu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl_wx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m2_mu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl_wx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m4_mu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl_wx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf4_mu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl_wx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf2_mu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl_wx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m1_mu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl_wx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m2_mu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl_wx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m4_mu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl_wx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32mf2_mu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl_wx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m1_mu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl_wx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m2_mu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl_wx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m4_mu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_mu-3.c new file mode 100644 index 00000000000..9ad69e2ae78 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf8_mu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl_wx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf4_mu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl_wx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf2_mu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl_wx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m1_mu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl_wx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m2_mu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl_wx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m4_mu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl_wx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf4_mu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl_wx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf2_mu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl_wx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m1_mu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl_wx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m2_mu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl_wx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m4_mu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl_wx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32mf2_mu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl_wx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m1_mu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl_wx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m2_mu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl_wx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m4_mu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tu-1.c new file mode 100644 index 00000000000..513f3211989 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wx_u8mf8_tu(vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf8_tu(merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl_wx_u8mf4_tu(vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf4_tu(merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl_wx_u8mf2_tu(vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf2_tu(merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl_wx_u8m1_tu(vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m1_tu(merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl_wx_u8m2_tu(vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m2_tu(merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl_wx_u8m4_tu(vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m4_tu(merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl_wx_u16mf4_tu(vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf4_tu(merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl_wx_u16mf2_tu(vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf2_tu(merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl_wx_u16m1_tu(vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m1_tu(merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl_wx_u16m2_tu(vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m2_tu(merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl_wx_u16m4_tu(vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m4_tu(merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl_wx_u32mf2_tu(vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32mf2_tu(merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl_wx_u32m1_tu(vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m1_tu(merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl_wx_u32m2_tu(vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m2_tu(merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl_wx_u32m4_tu(vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m4_tu(merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tu-2.c new file mode 100644 index 00000000000..991a5065805 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wx_u8mf8_tu(vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf8_tu(merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl_wx_u8mf4_tu(vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf4_tu(merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl_wx_u8mf2_tu(vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf2_tu(merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl_wx_u8m1_tu(vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m1_tu(merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl_wx_u8m2_tu(vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m2_tu(merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl_wx_u8m4_tu(vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m4_tu(merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl_wx_u16mf4_tu(vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf4_tu(merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl_wx_u16mf2_tu(vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf2_tu(merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl_wx_u16m1_tu(vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m1_tu(merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl_wx_u16m2_tu(vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m2_tu(merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl_wx_u16m4_tu(vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m4_tu(merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl_wx_u32mf2_tu(vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32mf2_tu(merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl_wx_u32m1_tu(vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m1_tu(merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl_wx_u32m2_tu(vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m2_tu(merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl_wx_u32m4_tu(vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m4_tu(merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tu-3.c new file mode 100644 index 00000000000..537ac5cf1a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wx_u8mf8_tu(vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf8_tu(merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl_wx_u8mf4_tu(vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf4_tu(merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl_wx_u8mf2_tu(vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf2_tu(merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl_wx_u8m1_tu(vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m1_tu(merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl_wx_u8m2_tu(vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m2_tu(merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl_wx_u8m4_tu(vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m4_tu(merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl_wx_u16mf4_tu(vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf4_tu(merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl_wx_u16mf2_tu(vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf2_tu(merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl_wx_u16m1_tu(vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m1_tu(merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl_wx_u16m2_tu(vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m2_tu(merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl_wx_u16m4_tu(vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m4_tu(merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl_wx_u32mf2_tu(vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32mf2_tu(merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl_wx_u32m1_tu(vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m1_tu(merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl_wx_u32m2_tu(vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m2_tu(merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl_wx_u32m4_tu(vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m4_tu(merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tum-1.c new file mode 100644 index 00000000000..d9dca56df97 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf8_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl_wx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf4_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl_wx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf2_tum(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl_wx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m1_tum(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl_wx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m2_tum(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl_wx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m4_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl_wx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf4_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl_wx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf2_tum(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl_wx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m1_tum(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl_wx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m2_tum(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl_wx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m4_tum(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl_wx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32mf2_tum(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl_wx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m1_tum(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl_wx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m2_tum(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl_wx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m4_tum(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tum-2.c new file mode 100644 index 00000000000..abcb0c392df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf8_tum(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl_wx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf4_tum(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl_wx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf2_tum(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl_wx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m1_tum(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl_wx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m2_tum(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl_wx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m4_tum(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl_wx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf4_tum(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl_wx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf2_tum(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl_wx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m1_tum(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl_wx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m2_tum(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl_wx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m4_tum(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl_wx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32mf2_tum(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl_wx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m1_tum(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl_wx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m2_tum(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl_wx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m4_tum(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tum-3.c new file mode 100644 index 00000000000..36c647c29f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf8_tum(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl_wx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf4_tum(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl_wx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf2_tum(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl_wx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m1_tum(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl_wx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m2_tum(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl_wx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m4_tum(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl_wx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf4_tum(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl_wx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf2_tum(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl_wx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m1_tum(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl_wx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m2_tum(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl_wx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m4_tum(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl_wx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32mf2_tum(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl_wx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m1_tum(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl_wx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m2_tum(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl_wx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m4_tum(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tumu-1.c new file mode 100644 index 00000000000..ab80691f2b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf8_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl_wx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf4_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl_wx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf2_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl_wx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m1_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl_wx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m2_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl_wx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m4_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl_wx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf4_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl_wx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf2_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl_wx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m1_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl_wx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m2_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl_wx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m4_tumu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl_wx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32mf2_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl_wx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m1_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl_wx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m2_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl_wx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m4_tumu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tumu-2.c new file mode 100644 index 00000000000..ab403aacd46 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf8_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl_wx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf4_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl_wx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf2_tumu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl_wx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m1_tumu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl_wx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m2_tumu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl_wx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m4_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl_wx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf4_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl_wx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf2_tumu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl_wx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m1_tumu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl_wx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m2_tumu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl_wx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m4_tumu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl_wx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32mf2_tumu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl_wx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m1_tumu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl_wx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m2_tumu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl_wx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m4_tumu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tumu-3.c new file mode 100644 index 00000000000..f18d6dd3d9b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_wx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf8_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl_wx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf4_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl_wx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8mf2_tumu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl_wx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m1_tumu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl_wx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m2_tumu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl_wx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u8m4_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl_wx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf4_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl_wx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16mf2_tumu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl_wx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m1_tumu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl_wx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m2_tumu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl_wx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u16m4_tumu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl_wx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32mf2_tumu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl_wx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m1_tumu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl_wx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m2_tumu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl_wx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_wx_u32m4_tumu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */