diff mbox series

RISC-V: Add vmadc C API tests

Message ID	20230208205448.269030-1-juzhe.zhong@rivai.ai
State	Accepted
Headers	Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D36D33858D20 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong <juzhe.zhong@rivai.ai> Subject: [PATCH] RISC-V: Add vmadc C API tests Date: Thu, 9 Feb 2023 04:54:48 +0800 Message-Id: <20230208205448.269030-1-juzhe.zhong@rivai.ai> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 Precedence: list Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org> X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?=
Series	RISC-V: Add vmadc C API tests \| RISC-V: Add vmadc C API tests

Checks

Context	Check	Description
snail/gcc-patch-check	success	Github commit url

Commit Message

juzhe.zhong@rivai.ai Feb. 8, 2023, 8:54 p.m. UTC

  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/vmadc-1.c: New test.
        * gcc.target/riscv/rvv/base/vmadc-2.c: New test.
        * gcc.target/riscv/rvv/base/vmadc-3.c: New test.
        * gcc.target/riscv/rvv/base/vmadc-4.c: New test.
        * gcc.target/riscv/rvv/base/vmadc-5.c: New test.
        * gcc.target/riscv/rvv/base/vmadc-6.c: New test.
        * gcc.target/riscv/rvv/base/vmadc-7.c: New test.
        * gcc.target/riscv/rvv/base/vmadc-8.c: New test.
        * gcc.target/riscv/rvv/base/vmadc_vv-1.c: New test.
        * gcc.target/riscv/rvv/base/vmadc_vv-2.c: New test.
        * gcc.target/riscv/rvv/base/vmadc_vv-3.c: New test.
        * gcc.target/riscv/rvv/base/vmadc_vvm-1.c: New test.
        * gcc.target/riscv/rvv/base/vmadc_vvm-2.c: New test.
        * gcc.target/riscv/rvv/base/vmadc_vvm-3.c: New test.
        * gcc.target/riscv/rvv/base/vmadc_vx_rv32-1.c: New test.
        * gcc.target/riscv/rvv/base/vmadc_vx_rv32-2.c: New test.
        * gcc.target/riscv/rvv/base/vmadc_vx_rv32-3.c: New test.
        * gcc.target/riscv/rvv/base/vmadc_vx_rv64-1.c: New test.
        * gcc.target/riscv/rvv/base/vmadc_vx_rv64-2.c: New test.
        * gcc.target/riscv/rvv/base/vmadc_vx_rv64-3.c: New test.
        * gcc.target/riscv/rvv/base/vmadc_vxm_rv32-1.c: New test.
        * gcc.target/riscv/rvv/base/vmadc_vxm_rv32-2.c: New test.
        * gcc.target/riscv/rvv/base/vmadc_vxm_rv32-3.c: New test.
        * gcc.target/riscv/rvv/base/vmadc_vxm_rv64-1.c: New test.
        * gcc.target/riscv/rvv/base/vmadc_vxm_rv64-2.c: New test.
        * gcc.target/riscv/rvv/base/vmadc_vxm_rv64-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vmadc-1.c       |  25 ++
 .../gcc.target/riscv/rvv/base/vmadc-2.c       |  43 +++
 .../gcc.target/riscv/rvv/base/vmadc-3.c       |  78 +++++
 .../gcc.target/riscv/rvv/base/vmadc-4.c       |  79 +++++
 .../gcc.target/riscv/rvv/base/vmadc-5.c       |  24 ++
 .../gcc.target/riscv/rvv/base/vmadc-6.c       |  43 +++
 .../gcc.target/riscv/rvv/base/vmadc-7.c       |  85 +++++
 .../gcc.target/riscv/rvv/base/vmadc-8.c       |  86 ++++++
 .../gcc.target/riscv/rvv/base/vmadc_vv-1.c    | 292 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmadc_vv-2.c    | 292 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmadc_vv-3.c    | 292 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmadc_vvm-1.c   | 292 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmadc_vvm-2.c   | 292 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmadc_vvm-3.c   | 292 ++++++++++++++++++
 .../riscv/rvv/base/vmadc_vx_rv32-1.c          | 289 +++++++++++++++++
 .../riscv/rvv/base/vmadc_vx_rv32-2.c          | 289 +++++++++++++++++
 .../riscv/rvv/base/vmadc_vx_rv32-3.c          | 289 +++++++++++++++++
 .../riscv/rvv/base/vmadc_vx_rv64-1.c          | 292 ++++++++++++++++++
 .../riscv/rvv/base/vmadc_vx_rv64-2.c          | 292 ++++++++++++++++++
 .../riscv/rvv/base/vmadc_vx_rv64-3.c          | 292 ++++++++++++++++++
 .../riscv/rvv/base/vmadc_vxm_rv32-1.c         | 289 +++++++++++++++++
 .../riscv/rvv/base/vmadc_vxm_rv32-2.c         | 289 +++++++++++++++++
 .../riscv/rvv/base/vmadc_vxm_rv32-3.c         | 289 +++++++++++++++++
 .../riscv/rvv/base/vmadc_vxm_rv64-1.c         | 292 ++++++++++++++++++
 .../riscv/rvv/base/vmadc_vxm_rv64-2.c         | 292 ++++++++++++++++++
 .../riscv/rvv/base/vmadc_vxm_rv64-3.c         | 292 ++++++++++++++++++
 26 files changed, 5701 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-3.c

diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-1.c
new file mode 100644
index 00000000000..1f281f0c6e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-1.c
@@ -0,0 +1,25 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+#include "riscv_vector.h"
+
+void f1 (void * in, void *out)
+{
+  vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4);
+  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+  vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+  vbool32_t v3 = __riscv_vmadc_vvm_i32m1_b32 (v2, v2, mask, 4);
+  __riscv_vsm_v_b32 (out, v3, 4);
+}
+
+void f2 (void * in, void *out)
+{
+  vbool32_t mask = *(vbool32_t*)in;
+  asm volatile ("":::"memory");
+  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+  vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+  vbool32_t v3 = __riscv_vmadc_vvm_i32m1_b32 (v2, v2, mask, 4);
+  __riscv_vsm_v_b32 (out, v3, 4);
+}
+
+/* { dg-final { scan-assembler-times {vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-not {vmv} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-2.c
new file mode 100644
index 00000000000..35dbd8e99b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-2.c
@@ -0,0 +1,43 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+#include "riscv_vector.h"
+
+void f1 (void * in, void *out, int32_t x)
+{
+  vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4);
+  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+  vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+  vbool32_t v3 = __riscv_vmadc_vxm_i32m1_b32 (v2, -16, mask, 4);
+  __riscv_vsm_v_b32 (out, v3, 4);
+}
+
+void f2 (void * in, void *out, int32_t x)
+{
+  vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4);
+  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+  vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+  vbool32_t v3 = __riscv_vmadc_vxm_i32m1_b32 (v2, 15, mask, 4);
+  __riscv_vsm_v_b32 (out, v3, 4);
+}
+
+void f3 (void * in, void *out, int32_t x)
+{
+  vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4);
+  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+  vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+  vbool32_t v3 = __riscv_vmadc_vxm_i32m1_b32 (v2, -17, mask, 4);
+  __riscv_vsm_v_b32 (out, v3, 4);
+}
+
+void f4 (void * in, void *out, int32_t x)
+{
+  vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4);
+  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+  vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+  vbool32_t v3 = __riscv_vmadc_vxm_i32m1_b32 (v2, 16, mask, 4);
+  __riscv_vsm_v_b32 (out, v3, 4);
+}
+
+/* { dg-final { scan-assembler-times {vmadc\.vim\s+v[0-9]+,\s*v[0-9]+,\s*-16,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vmadc\.vim\s+v[0-9]+,\s*v[0-9]+,\s*15,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-3.c
new file mode 100644
index 00000000000..3a5a292df34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-3.c
@@ -0,0 +1,78 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+void f0 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vxm_i64m1_b64 (v2, -16, mask, 4);
+  vbool64_t v4 = __riscv_vmadc_vxm_i64m1_b64 (v, -16, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f1 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vxm_i64m1_b64 (v2, 15, mask, 4);
+  vbool64_t v4 = __riscv_vmadc_vxm_i64m1_b64 (v, 15, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f2 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vxm_i64m1_b64 (v2, -17, mask, 4);
+  vbool64_t v4 = __riscv_vmadc_vxm_i64m1_b64 (v, -17, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f3 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vxm_i64m1_b64 (v2, 16, mask, 4);
+  vbool64_t v4 = __riscv_vmadc_vxm_i64m1_b64 (v, 16, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f4 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vxm_i64m1_b64 (v2, 0xAAAAAAAA, mask, 4);
+  vbool64_t v4 = __riscv_vmadc_vxm_i64m1_b64 (v, 0xAAAAAAAA, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f5 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vxm_i64m1_b64 (v2, 0xAAAAAAAAAAAAAAAA, mask, 4);
+  vbool64_t v4 = __riscv_vmadc_vxm_i64m1_b64 (v, 0xAAAAAAAAAAAAAAAA, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f6 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vxm_i64m1_b64 (v2, x, mask, 4);
+  vbool64_t v4 = __riscv_vmadc_vxm_i64m1_b64 (v, x, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+/* { dg-final { scan-assembler-times {vmadc\.vim\s+v[0-9]+,\s*v[0-9]+,\s*-16,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmadc\.vim\s+v[0-9]+,\s*v[0-9]+,\s*15,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 10 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-4.c
new file mode 100644
index 00000000000..7bbe6913f8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-4.c
@@ -0,0 +1,79 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+
+#include "riscv_vector.h"
+
+void f0 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vxm_i64m1_b64 (v2, -16, mask, 4);
+  vbool64_t v4 = __riscv_vmadc_vxm_i64m1_b64 (v, -16, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f1 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vxm_i64m1_b64 (v2, 15, mask, 4);
+  vbool64_t v4 = __riscv_vmadc_vxm_i64m1_b64 (v, 15, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f2 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vxm_i64m1_b64 (v2, -17, mask, 4);
+  vbool64_t v4 = __riscv_vmadc_vxm_i64m1_b64 (v, -17, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f3 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vxm_i64m1_b64 (v2, 16, mask, 4);
+  vbool64_t v4 = __riscv_vmadc_vxm_i64m1_b64 (v, 16, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f4 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vxm_i64m1_b64 (v2, 0xAAAAAAA, mask, 4);
+  vbool64_t v4 = __riscv_vmadc_vxm_i64m1_b64 (v, 0xAAAAAAA, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f5 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vxm_i64m1_b64 (v2, 0xAAAAAAAAAAAAAAAA, mask, 4);
+  vbool64_t v4 = __riscv_vmadc_vxm_i64m1_b64 (v, 0xAAAAAAAAAAAAAAAA, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f6 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vxm_i64m1_b64 (v2, x, mask, 4);
+  vbool64_t v4 = __riscv_vmadc_vxm_i64m1_b64 (v, x, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+/* { dg-final { scan-assembler-times {vmadc\.vim\s+v[0-9]+,\s*v[0-9]+,\s*-16,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmadc\.vim\s+v[0-9]+,\s*v[0-9]+,\s*15,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 6 } } */
+/* { dg-final { scan-assembler-times {vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-5.c
new file mode 100644
index 00000000000..5a27c352fa0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-5.c
@@ -0,0 +1,24 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+#include "riscv_vector.h"
+
+void f1 (void * in, void *out)
+{
+  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+  vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+  vbool32_t v3 = __riscv_vmadc_vv_i32m1_b32 (v2, v2, 4);
+  __riscv_vsm_v_b32 (out, v3, 4);
+}
+
+void f2 (void * in, void *out)
+{
+  vbool32_t mask = *(vbool32_t*)in;
+  asm volatile ("":::"memory");
+  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+  vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+  vbool32_t v3 = __riscv_vmadc_vv_i32m1_b32 (v2, v2, 4);
+  __riscv_vsm_v_b32 (out, v3, 4);
+}
+
+/* { dg-final { scan-assembler-times {vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-not {vmv} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-6.c
new file mode 100644
index 00000000000..d66962dc9cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-6.c
@@ -0,0 +1,43 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+#include "riscv_vector.h"
+
+void f1 (void * in, void *out, int32_t x)
+{
+  
+  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+  vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+  vbool32_t v3 = __riscv_vmadc_vx_i32m1_b32 (v2, -16, 4);
+  __riscv_vsm_v_b32 (out, v3, 4);
+}
+
+void f2 (void * in, void *out, int32_t x)
+{
+  
+  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+  vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+  vbool32_t v3 = __riscv_vmadc_vx_i32m1_b32 (v2, 15, 4);
+  __riscv_vsm_v_b32 (out, v3, 4);
+}
+
+void f3 (void * in, void *out, int32_t x)
+{
+  
+  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+  vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+  vbool32_t v3 = __riscv_vmadc_vx_i32m1_b32 (v2, -17, 4);
+  __riscv_vsm_v_b32 (out, v3, 4);
+}
+
+void f4 (void * in, void *out, int32_t x)
+{
+  
+  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+  vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+  vbool32_t v3 = __riscv_vmadc_vx_i32m1_b32 (v2, 16, 4);
+  __riscv_vsm_v_b32 (out, v3, 4);
+}
+
+/* { dg-final { scan-assembler-times {vmadc\.vi\s+v[0-9]+,\s*v[0-9]+,\s*-16} 1 } } */
+/* { dg-final { scan-assembler-times {vmadc\.vi\s+v[0-9]+,\s*v[0-9]+,\s*15} 1 } } */
+/* { dg-final { scan-assembler-times {vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-7.c
new file mode 100644
index 00000000000..648ea08a794
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-7.c
@@ -0,0 +1,85 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+void f0 (void * in, void *out, int64_t x, int n)
+{
+  
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vx_i64m1_b64 (v2, -16, 4);
+  vbool64_t v4 = __riscv_vmadc_vx_i64m1_b64 (v, -16, 4);
+  __riscv_vsm_v_b64 (out + 200, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f1 (void * in, void *out, int64_t x, int n)
+{
+  
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vx_i64m1_b64 (v2, 15, 4);
+  vbool64_t v4 = __riscv_vmadc_vx_i64m1_b64 (v, 15, 4);
+  __riscv_vsm_v_b64 (out + 200, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f2 (void * in, void *out, int64_t x, int n)
+{
+  
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vx_i64m1_b64 (v2, -17, 4);
+  vbool64_t v4 = __riscv_vmadc_vx_i64m1_b64 (v, -17, 4);
+  __riscv_vsm_v_b64 (out + 200, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f3 (void * in, void *out, int64_t x, int n)
+{
+  
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vx_i64m1_b64 (v2, 16, 4);
+  vbool64_t v4 = __riscv_vmadc_vx_i64m1_b64 (v, 16, 4);
+  __riscv_vsm_v_b64 (out + 200, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f4 (void * in, void *out, int64_t x, int n)
+{
+  
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vx_i64m1_b64 (v2, 0xAAAAAAAA, 4);
+  vbool64_t v4 = __riscv_vmadc_vx_i64m1_b64 (v, 0xAAAAAAAA, 4);
+  __riscv_vsm_v_b64 (out + 200, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f5 (void * in, void *out, int64_t x, int n)
+{
+  
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vx_i64m1_b64 (v2, 0xAAAAAAAAAAAAAAAA, 4);
+  vbool64_t v4 = __riscv_vmadc_vx_i64m1_b64 (v, 0xAAAAAAAAAAAAAAAA, 4);
+  __riscv_vsm_v_b64 (out + 200, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f6 (void * in, void *out, int64_t x, int n)
+{
+  
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vx_i64m1_b64 (v2, x, 4);
+  vbool64_t v4 = __riscv_vmadc_vx_i64m1_b64 (v, x, 4);
+  __riscv_vsm_v_b64 (out + 200, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+/* { dg-final { scan-assembler-times {vmadc\.vi\s+v[0-9]+,\s*v[0-9]+,\s*-16} 2 } } */
+/* { dg-final { scan-assembler-times {vmadc\.vi\s+v[0-9]+,\s*v[0-9]+,\s*15} 2 } } */
+/* { dg-final { scan-assembler-times {vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 10 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-8.c
new file mode 100644
index 00000000000..bbe4bcb63eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-8.c
@@ -0,0 +1,86 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+
+#include "riscv_vector.h"
+
+void f0 (void * in, void *out, int64_t x, int n)
+{
+  
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vx_i64m1_b64 (v2, -16, 4);
+  vbool64_t v4 = __riscv_vmadc_vx_i64m1_b64 (v, -16, 4);
+  __riscv_vsm_v_b64 (out + 200, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f1 (void * in, void *out, int64_t x, int n)
+{
+  
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vx_i64m1_b64 (v2, 15, 4);
+  vbool64_t v4 = __riscv_vmadc_vx_i64m1_b64 (v, 15, 4);
+  __riscv_vsm_v_b64 (out + 200, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f2 (void * in, void *out, int64_t x, int n)
+{
+  
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vx_i64m1_b64 (v2, -17, 4);
+  vbool64_t v4 = __riscv_vmadc_vx_i64m1_b64 (v, -17, 4);
+  __riscv_vsm_v_b64 (out + 200, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f3 (void * in, void *out, int64_t x, int n)
+{
+  
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vx_i64m1_b64 (v2, 16, 4);
+  vbool64_t v4 = __riscv_vmadc_vx_i64m1_b64 (v, 16, 4);
+  __riscv_vsm_v_b64 (out + 200, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f4 (void * in, void *out, int64_t x, int n)
+{
+  
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vx_i64m1_b64 (v2, 0xAAAAAAA, 4);
+  vbool64_t v4 = __riscv_vmadc_vx_i64m1_b64 (v, 0xAAAAAAA, 4);
+  __riscv_vsm_v_b64 (out + 200, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f5 (void * in, void *out, int64_t x, int n)
+{
+  
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vx_i64m1_b64 (v2, 0xAAAAAAAAAAAAAAAA, 4);
+  vbool64_t v4 = __riscv_vmadc_vx_i64m1_b64 (v, 0xAAAAAAAAAAAAAAAA, 4);
+  __riscv_vsm_v_b64 (out + 200, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+void f6 (void * in, void *out, int64_t x, int n)
+{
+  
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vbool64_t v3 = __riscv_vmadc_vx_i64m1_b64 (v2, x, 4);
+  vbool64_t v4 = __riscv_vmadc_vx_i64m1_b64 (v, x, 4);
+  __riscv_vsm_v_b64 (out + 200, v3, 4);
+  __riscv_vsm_v_b64 (out + 2, v4, 4);
+}
+
+/* { dg-final { scan-assembler-times {vmadc\.vi\s+v[0-9]+,\s*v[0-9]+,\s*-16} 2 } } */
+/* { dg-final { scan-assembler-times {vmadc\.vi\s+v[0-9]+,\s*v[0-9]+,\s*15} 2 } } */
+/* { dg-final { scan-assembler-times {vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 6 } } */
+/* { dg-final { scan-assembler-times {vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-1.c
new file mode 100644
index 00000000000..4f4780b9028
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-1.c
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmadc_vv_i8mf8_b64(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8mf8_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_i8mf4_b32(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8mf4_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_i8mf2_b16(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8mf2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_i8m1_b8(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8m1_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vv_i8m2_b4(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8m2_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vv_i8m4_b2(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8m4_b2(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmadc_vv_i8m8_b1(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8m8_b1(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_i16mf4_b64(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i16mf4_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_i16mf2_b32(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i16mf2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_i16m1_b16(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i16m1_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_i16m2_b8(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i16m2_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vv_i16m4_b4(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i16m4_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vv_i16m8_b2(vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i16m8_b2(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_i32mf2_b64(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i32mf2_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_i32m1_b32(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i32m1_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_i32m2_b16(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i32m2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_i32m4_b8(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i32m4_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vv_i32m8_b4(vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i32m8_b4(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_i64m1_b64(vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i64m1_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_i64m2_b32(vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i64m2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_i64m4_b16(vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i64m4_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_i64m8_b8(vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i64m8_b8(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_u8mf8_b64(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8mf8_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_u8mf4_b32(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8mf4_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_u8mf2_b16(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8mf2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_u8m1_b8(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8m1_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vv_u8m2_b4(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8m2_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vv_u8m4_b2(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8m4_b2(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmadc_vv_u8m8_b1(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8m8_b1(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_u16mf4_b64(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u16mf4_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_u16mf2_b32(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u16mf2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_u16m1_b16(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u16m1_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_u16m2_b8(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u16m2_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vv_u16m4_b4(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u16m4_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vv_u16m8_b2(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u16m8_b2(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_u32mf2_b64(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u32mf2_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_u32m1_b32(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u32m1_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_u32m2_b16(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u32m2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_u32m4_b8(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u32m4_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vv_u32m8_b4(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u32m8_b4(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_u64m1_b64(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u64m1_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_u64m2_b32(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u64m2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_u64m4_b16(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u64m4_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_u64m8_b8(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u64m8_b8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-2.c
new file mode 100644
index 00000000000..690b0091241
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-2.c
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmadc_vv_i8mf8_b64(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8mf8_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_i8mf4_b32(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8mf4_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_i8mf2_b16(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8mf2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_i8m1_b8(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8m1_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vv_i8m2_b4(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8m2_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vv_i8m4_b2(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8m4_b2(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmadc_vv_i8m8_b1(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8m8_b1(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_i16mf4_b64(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i16mf4_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_i16mf2_b32(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i16mf2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_i16m1_b16(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i16m1_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_i16m2_b8(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i16m2_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vv_i16m4_b4(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i16m4_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vv_i16m8_b2(vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i16m8_b2(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_i32mf2_b64(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i32mf2_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_i32m1_b32(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i32m1_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_i32m2_b16(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i32m2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_i32m4_b8(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i32m4_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vv_i32m8_b4(vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i32m8_b4(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_i64m1_b64(vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i64m1_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_i64m2_b32(vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i64m2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_i64m4_b16(vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i64m4_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_i64m8_b8(vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i64m8_b8(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_u8mf8_b64(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8mf8_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_u8mf4_b32(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8mf4_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_u8mf2_b16(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8mf2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_u8m1_b8(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8m1_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vv_u8m2_b4(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8m2_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vv_u8m4_b2(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8m4_b2(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmadc_vv_u8m8_b1(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8m8_b1(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_u16mf4_b64(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u16mf4_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_u16mf2_b32(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u16mf2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_u16m1_b16(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u16m1_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_u16m2_b8(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u16m2_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vv_u16m4_b4(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u16m4_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vv_u16m8_b2(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u16m8_b2(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_u32mf2_b64(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u32mf2_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_u32m1_b32(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u32m1_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_u32m2_b16(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u32m2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_u32m4_b8(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u32m4_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vv_u32m8_b4(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u32m8_b4(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_u64m1_b64(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u64m1_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_u64m2_b32(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u64m2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_u64m4_b16(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u64m4_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_u64m8_b8(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u64m8_b8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-3.c
new file mode 100644
index 00000000000..894178188b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-3.c
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmadc_vv_i8mf8_b64(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8mf8_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_i8mf4_b32(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8mf4_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_i8mf2_b16(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8mf2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_i8m1_b8(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8m1_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vv_i8m2_b4(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8m2_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vv_i8m4_b2(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8m4_b2(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmadc_vv_i8m8_b1(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i8m8_b1(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_i16mf4_b64(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i16mf4_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_i16mf2_b32(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i16mf2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_i16m1_b16(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i16m1_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_i16m2_b8(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i16m2_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vv_i16m4_b4(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i16m4_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vv_i16m8_b2(vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i16m8_b2(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_i32mf2_b64(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i32mf2_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_i32m1_b32(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i32m1_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_i32m2_b16(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i32m2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_i32m4_b8(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i32m4_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vv_i32m8_b4(vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i32m8_b4(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_i64m1_b64(vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i64m1_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_i64m2_b32(vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i64m2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_i64m4_b16(vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i64m4_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_i64m8_b8(vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_i64m8_b8(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_u8mf8_b64(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8mf8_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_u8mf4_b32(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8mf4_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_u8mf2_b16(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8mf2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_u8m1_b8(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8m1_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vv_u8m2_b4(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8m2_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vv_u8m4_b2(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8m4_b2(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmadc_vv_u8m8_b1(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u8m8_b1(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_u16mf4_b64(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u16mf4_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_u16mf2_b32(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u16mf2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_u16m1_b16(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u16m1_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_u16m2_b8(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u16m2_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vv_u16m4_b4(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u16m4_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vv_u16m8_b2(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u16m8_b2(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_u32mf2_b64(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u32mf2_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_u32m1_b32(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u32m1_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_u32m2_b16(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u32m2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_u32m4_b8(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u32m4_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vv_u32m8_b4(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u32m8_b4(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vv_u64m1_b64(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u64m1_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vv_u64m2_b32(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u64m2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vv_u64m4_b16(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u64m4_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vv_u64m8_b8(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vv_u64m8_b8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-1.c
new file mode 100644
index 00000000000..b6854783c2a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-1.c
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmadc_vvm_i8mf8_b64(vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8mf8_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_i8mf4_b32(vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8mf4_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_i8mf2_b16(vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8mf2_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_i8m1_b8(vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8m1_b8(op1,op2,carryin,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vvm_i8m2_b4(vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8m2_b4(op1,op2,carryin,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vvm_i8m4_b2(vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8m4_b2(op1,op2,carryin,vl);
+}
+
+
+vbool1_t test___riscv_vmadc_vvm_i8m8_b1(vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8m8_b1(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_i16mf4_b64(vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i16mf4_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_i16mf2_b32(vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i16mf2_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_i16m1_b16(vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i16m1_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_i16m2_b8(vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i16m2_b8(op1,op2,carryin,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vvm_i16m4_b4(vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i16m4_b4(op1,op2,carryin,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vvm_i16m8_b2(vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i16m8_b2(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_i32mf2_b64(vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i32mf2_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_i32m1_b32(vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i32m1_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_i32m2_b16(vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i32m2_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_i32m4_b8(vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i32m4_b8(op1,op2,carryin,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vvm_i32m8_b4(vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i32m8_b4(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_i64m1_b64(vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i64m1_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_i64m2_b32(vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i64m2_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_i64m4_b16(vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i64m4_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_i64m8_b8(vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i64m8_b8(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_u8mf8_b64(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8mf8_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_u8mf4_b32(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8mf4_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_u8mf2_b16(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8mf2_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_u8m1_b8(vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8m1_b8(op1,op2,carryin,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vvm_u8m2_b4(vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8m2_b4(op1,op2,carryin,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vvm_u8m4_b2(vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8m4_b2(op1,op2,carryin,vl);
+}
+
+
+vbool1_t test___riscv_vmadc_vvm_u8m8_b1(vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8m8_b1(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_u16mf4_b64(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u16mf4_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_u16mf2_b32(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u16mf2_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_u16m1_b16(vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u16m1_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_u16m2_b8(vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u16m2_b8(op1,op2,carryin,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vvm_u16m4_b4(vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u16m4_b4(op1,op2,carryin,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vvm_u16m8_b2(vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u16m8_b2(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_u32mf2_b64(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u32mf2_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_u32m1_b32(vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u32m1_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_u32m2_b16(vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u32m2_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_u32m4_b8(vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u32m4_b8(op1,op2,carryin,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vvm_u32m8_b4(vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u32m8_b4(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_u64m1_b64(vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u64m1_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_u64m2_b32(vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u64m2_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_u64m4_b16(vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u64m4_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_u64m8_b8(vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u64m8_b8(op1,op2,carryin,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-2.c
new file mode 100644
index 00000000000..3237685e914
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-2.c
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmadc_vvm_i8mf8_b64(vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8mf8_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_i8mf4_b32(vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8mf4_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_i8mf2_b16(vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8mf2_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_i8m1_b8(vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8m1_b8(op1,op2,carryin,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vvm_i8m2_b4(vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8m2_b4(op1,op2,carryin,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vvm_i8m4_b2(vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8m4_b2(op1,op2,carryin,31);
+}
+
+
+vbool1_t test___riscv_vmadc_vvm_i8m8_b1(vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8m8_b1(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_i16mf4_b64(vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i16mf4_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_i16mf2_b32(vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i16mf2_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_i16m1_b16(vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i16m1_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_i16m2_b8(vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i16m2_b8(op1,op2,carryin,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vvm_i16m4_b4(vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i16m4_b4(op1,op2,carryin,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vvm_i16m8_b2(vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i16m8_b2(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_i32mf2_b64(vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i32mf2_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_i32m1_b32(vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i32m1_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_i32m2_b16(vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i32m2_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_i32m4_b8(vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i32m4_b8(op1,op2,carryin,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vvm_i32m8_b4(vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i32m8_b4(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_i64m1_b64(vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i64m1_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_i64m2_b32(vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i64m2_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_i64m4_b16(vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i64m4_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_i64m8_b8(vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i64m8_b8(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_u8mf8_b64(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8mf8_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_u8mf4_b32(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8mf4_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_u8mf2_b16(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8mf2_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_u8m1_b8(vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8m1_b8(op1,op2,carryin,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vvm_u8m2_b4(vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8m2_b4(op1,op2,carryin,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vvm_u8m4_b2(vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8m4_b2(op1,op2,carryin,31);
+}
+
+
+vbool1_t test___riscv_vmadc_vvm_u8m8_b1(vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8m8_b1(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_u16mf4_b64(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u16mf4_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_u16mf2_b32(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u16mf2_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_u16m1_b16(vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u16m1_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_u16m2_b8(vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u16m2_b8(op1,op2,carryin,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vvm_u16m4_b4(vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u16m4_b4(op1,op2,carryin,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vvm_u16m8_b2(vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u16m8_b2(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_u32mf2_b64(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u32mf2_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_u32m1_b32(vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u32m1_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_u32m2_b16(vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u32m2_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_u32m4_b8(vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u32m4_b8(op1,op2,carryin,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vvm_u32m8_b4(vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u32m8_b4(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_u64m1_b64(vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u64m1_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_u64m2_b32(vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u64m2_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_u64m4_b16(vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u64m4_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_u64m8_b8(vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u64m8_b8(op1,op2,carryin,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-3.c
new file mode 100644
index 00000000000..ab34bdeba8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-3.c
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmadc_vvm_i8mf8_b64(vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8mf8_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_i8mf4_b32(vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8mf4_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_i8mf2_b16(vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8mf2_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_i8m1_b8(vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8m1_b8(op1,op2,carryin,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vvm_i8m2_b4(vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8m2_b4(op1,op2,carryin,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vvm_i8m4_b2(vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8m4_b2(op1,op2,carryin,32);
+}
+
+
+vbool1_t test___riscv_vmadc_vvm_i8m8_b1(vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i8m8_b1(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_i16mf4_b64(vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i16mf4_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_i16mf2_b32(vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i16mf2_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_i16m1_b16(vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i16m1_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_i16m2_b8(vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i16m2_b8(op1,op2,carryin,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vvm_i16m4_b4(vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i16m4_b4(op1,op2,carryin,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vvm_i16m8_b2(vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i16m8_b2(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_i32mf2_b64(vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i32mf2_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_i32m1_b32(vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i32m1_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_i32m2_b16(vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i32m2_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_i32m4_b8(vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i32m4_b8(op1,op2,carryin,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vvm_i32m8_b4(vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i32m8_b4(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_i64m1_b64(vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i64m1_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_i64m2_b32(vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i64m2_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_i64m4_b16(vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i64m4_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_i64m8_b8(vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_i64m8_b8(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_u8mf8_b64(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8mf8_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_u8mf4_b32(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8mf4_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_u8mf2_b16(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8mf2_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_u8m1_b8(vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8m1_b8(op1,op2,carryin,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vvm_u8m2_b4(vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8m2_b4(op1,op2,carryin,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vvm_u8m4_b2(vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8m4_b2(op1,op2,carryin,32);
+}
+
+
+vbool1_t test___riscv_vmadc_vvm_u8m8_b1(vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u8m8_b1(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_u16mf4_b64(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u16mf4_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_u16mf2_b32(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u16mf2_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_u16m1_b16(vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u16m1_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_u16m2_b8(vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u16m2_b8(op1,op2,carryin,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vvm_u16m4_b4(vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u16m4_b4(op1,op2,carryin,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vvm_u16m8_b2(vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u16m8_b2(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_u32mf2_b64(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u32mf2_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_u32m1_b32(vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u32m1_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_u32m2_b16(vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u32m2_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_u32m4_b8(vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u32m4_b8(op1,op2,carryin,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vvm_u32m8_b4(vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u32m8_b4(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vvm_u64m1_b64(vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u64m1_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vvm_u64m2_b32(vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u64m2_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vvm_u64m4_b16(vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u64m4_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vvm_u64m8_b8(vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vvm_u64m8_b8(op1,op2,carryin,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-1.c
new file mode 100644
index 00000000000..cbabfdac407
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-1.c
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmadc_vx_i8mf8_b64(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8mf8_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i8mf4_b32(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8mf4_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i8mf2_b16(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8mf2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i8m1_b8(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m1_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_i8m2_b4(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m2_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_i8m4_b2(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m4_b2(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmadc_vx_i8m8_b1(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m8_b1(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_i16mf4_b64(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16mf4_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i16mf2_b32(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16mf2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i16m1_b16(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m1_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i16m2_b8(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m2_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_i16m4_b4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m4_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_i16m8_b2(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m8_b2(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_i32mf2_b64(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32mf2_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i32m1_b32(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m1_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i32m2_b16(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i32m4_b8(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m4_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_i32m8_b4(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m8_b4(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_i64m1_b64(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m1_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i64m2_b32(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i64m4_b16(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m4_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i64m8_b8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m8_b8(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u8mf8_b64(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8mf8_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u8mf4_b32(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8mf4_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u8mf2_b16(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8mf2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u8m1_b8(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m1_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_u8m2_b4(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m2_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_u8m4_b2(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m4_b2(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmadc_vx_u8m8_b1(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m8_b1(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u16mf4_b64(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16mf4_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u16mf2_b32(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16mf2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u16m1_b16(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m1_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u16m2_b8(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m2_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_u16m4_b4(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m4_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_u16m8_b2(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m8_b2(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u32mf2_b64(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32mf2_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u32m1_b32(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m1_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u32m2_b16(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u32m4_b8(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m4_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_u32m8_b4(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m8_b4(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u64m1_b64(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m1_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u64m2_b32(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u64m4_b16(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m4_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u64m8_b8(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m8_b8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-2.c
new file mode 100644
index 00000000000..099c3e1082a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-2.c
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmadc_vx_i8mf8_b64(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8mf8_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i8mf4_b32(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8mf4_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i8mf2_b16(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8mf2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i8m1_b8(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m1_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_i8m2_b4(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m2_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_i8m4_b2(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m4_b2(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmadc_vx_i8m8_b1(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m8_b1(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_i16mf4_b64(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16mf4_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i16mf2_b32(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16mf2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i16m1_b16(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m1_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i16m2_b8(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m2_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_i16m4_b4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m4_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_i16m8_b2(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m8_b2(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_i32mf2_b64(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32mf2_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i32m1_b32(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m1_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i32m2_b16(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i32m4_b8(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m4_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_i32m8_b4(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m8_b4(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_i64m1_b64(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m1_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i64m2_b32(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i64m4_b16(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m4_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i64m8_b8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m8_b8(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u8mf8_b64(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8mf8_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u8mf4_b32(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8mf4_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u8mf2_b16(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8mf2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u8m1_b8(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m1_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_u8m2_b4(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m2_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_u8m4_b2(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m4_b2(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmadc_vx_u8m8_b1(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m8_b1(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u16mf4_b64(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16mf4_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u16mf2_b32(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16mf2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u16m1_b16(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m1_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u16m2_b8(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m2_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_u16m4_b4(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m4_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_u16m8_b2(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m8_b2(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u32mf2_b64(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32mf2_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u32m1_b32(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m1_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u32m2_b16(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u32m4_b8(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m4_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_u32m8_b4(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m8_b4(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u64m1_b64(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m1_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u64m2_b32(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u64m4_b16(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m4_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u64m8_b8(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m8_b8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-3.c
new file mode 100644
index 00000000000..aee2c37c8c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-3.c
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmadc_vx_i8mf8_b64(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8mf8_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i8mf4_b32(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8mf4_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i8mf2_b16(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8mf2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i8m1_b8(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m1_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_i8m2_b4(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m2_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_i8m4_b2(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m4_b2(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmadc_vx_i8m8_b1(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m8_b1(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_i16mf4_b64(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16mf4_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i16mf2_b32(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16mf2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i16m1_b16(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m1_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i16m2_b8(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m2_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_i16m4_b4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m4_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_i16m8_b2(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m8_b2(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_i32mf2_b64(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32mf2_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i32m1_b32(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m1_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i32m2_b16(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i32m4_b8(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m4_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_i32m8_b4(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m8_b4(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_i64m1_b64(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m1_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i64m2_b32(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i64m4_b16(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m4_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i64m8_b8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m8_b8(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u8mf8_b64(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8mf8_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u8mf4_b32(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8mf4_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u8mf2_b16(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8mf2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u8m1_b8(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m1_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_u8m2_b4(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m2_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_u8m4_b2(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m4_b2(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmadc_vx_u8m8_b1(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m8_b1(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u16mf4_b64(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16mf4_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u16mf2_b32(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16mf2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u16m1_b16(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m1_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u16m2_b8(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m2_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_u16m4_b4(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m4_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_u16m8_b2(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m8_b2(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u32mf2_b64(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32mf2_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u32m1_b32(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m1_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u32m2_b16(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u32m4_b8(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m4_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_u32m8_b4(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m8_b4(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u64m1_b64(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m1_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u64m2_b32(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u64m4_b16(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m4_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u64m8_b8(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m8_b8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmadc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-1.c
new file mode 100644
index 00000000000..743ddd148a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-1.c
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmadc_vx_i8mf8_b64(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8mf8_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i8mf4_b32(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8mf4_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i8mf2_b16(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8mf2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i8m1_b8(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m1_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_i8m2_b4(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m2_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_i8m4_b2(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m4_b2(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmadc_vx_i8m8_b1(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m8_b1(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_i16mf4_b64(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16mf4_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i16mf2_b32(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16mf2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i16m1_b16(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m1_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i16m2_b8(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m2_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_i16m4_b4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m4_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_i16m8_b2(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m8_b2(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_i32mf2_b64(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32mf2_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i32m1_b32(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m1_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i32m2_b16(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i32m4_b8(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m4_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_i32m8_b4(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m8_b4(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_i64m1_b64(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m1_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i64m2_b32(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i64m4_b16(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m4_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i64m8_b8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m8_b8(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u8mf8_b64(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8mf8_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u8mf4_b32(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8mf4_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u8mf2_b16(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8mf2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u8m1_b8(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m1_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_u8m2_b4(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m2_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_u8m4_b2(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m4_b2(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmadc_vx_u8m8_b1(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m8_b1(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u16mf4_b64(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16mf4_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u16mf2_b32(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16mf2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u16m1_b16(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m1_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u16m2_b8(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m2_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_u16m4_b4(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m4_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_u16m8_b2(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m8_b2(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u32mf2_b64(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32mf2_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u32m1_b32(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m1_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u32m2_b16(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u32m4_b8(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m4_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_u32m8_b4(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m8_b4(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u64m1_b64(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m1_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u64m2_b32(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u64m4_b16(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m4_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u64m8_b8(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m8_b8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-2.c
new file mode 100644
index 00000000000..fd3f1b6b8b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-2.c
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmadc_vx_i8mf8_b64(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8mf8_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i8mf4_b32(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8mf4_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i8mf2_b16(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8mf2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i8m1_b8(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m1_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_i8m2_b4(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m2_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_i8m4_b2(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m4_b2(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmadc_vx_i8m8_b1(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m8_b1(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_i16mf4_b64(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16mf4_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i16mf2_b32(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16mf2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i16m1_b16(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m1_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i16m2_b8(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m2_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_i16m4_b4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m4_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_i16m8_b2(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m8_b2(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_i32mf2_b64(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32mf2_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i32m1_b32(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m1_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i32m2_b16(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i32m4_b8(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m4_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_i32m8_b4(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m8_b4(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_i64m1_b64(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m1_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i64m2_b32(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i64m4_b16(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m4_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i64m8_b8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m8_b8(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u8mf8_b64(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8mf8_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u8mf4_b32(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8mf4_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u8mf2_b16(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8mf2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u8m1_b8(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m1_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_u8m2_b4(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m2_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_u8m4_b2(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m4_b2(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmadc_vx_u8m8_b1(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m8_b1(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u16mf4_b64(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16mf4_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u16mf2_b32(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16mf2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u16m1_b16(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m1_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u16m2_b8(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m2_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_u16m4_b4(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m4_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_u16m8_b2(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m8_b2(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u32mf2_b64(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32mf2_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u32m1_b32(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m1_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u32m2_b16(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u32m4_b8(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m4_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_u32m8_b4(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m8_b4(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u64m1_b64(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m1_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u64m2_b32(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u64m4_b16(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m4_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u64m8_b8(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m8_b8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-3.c
new file mode 100644
index 00000000000..8d0e155bcb8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-3.c
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmadc_vx_i8mf8_b64(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8mf8_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i8mf4_b32(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8mf4_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i8mf2_b16(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8mf2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i8m1_b8(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m1_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_i8m2_b4(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m2_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_i8m4_b2(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m4_b2(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmadc_vx_i8m8_b1(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i8m8_b1(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_i16mf4_b64(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16mf4_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i16mf2_b32(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16mf2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i16m1_b16(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m1_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i16m2_b8(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m2_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_i16m4_b4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m4_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_i16m8_b2(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i16m8_b2(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_i32mf2_b64(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32mf2_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i32m1_b32(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m1_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i32m2_b16(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i32m4_b8(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m4_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_i32m8_b4(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i32m8_b4(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_i64m1_b64(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m1_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_i64m2_b32(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_i64m4_b16(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m4_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_i64m8_b8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_i64m8_b8(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u8mf8_b64(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8mf8_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u8mf4_b32(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8mf4_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u8mf2_b16(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8mf2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u8m1_b8(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m1_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_u8m2_b4(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m2_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_u8m4_b2(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m4_b2(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmadc_vx_u8m8_b1(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u8m8_b1(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u16mf4_b64(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16mf4_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u16mf2_b32(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16mf2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u16m1_b16(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m1_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u16m2_b8(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m2_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_u16m4_b4(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m4_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vx_u16m8_b2(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u16m8_b2(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u32mf2_b64(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32mf2_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u32m1_b32(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m1_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u32m2_b16(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u32m4_b8(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m4_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vx_u32m8_b4(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u32m8_b4(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vx_u64m1_b64(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m1_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vx_u64m2_b32(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vx_u64m4_b16(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m4_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vx_u64m8_b8(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmadc_vx_u64m8_b8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-1.c
new file mode 100644
index 00000000000..0cfdad79082
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-1.c
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmadc_vxm_i8mf8_b64(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8mf8_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i8mf4_b32(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8mf4_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i8mf2_b16(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8mf2_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i8m1_b8(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m1_b8(op1,op2,carryin,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_i8m2_b4(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m2_b4(op1,op2,carryin,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_i8m4_b2(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m4_b2(op1,op2,carryin,vl);
+}
+
+
+vbool1_t test___riscv_vmadc_vxm_i8m8_b1(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m8_b1(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_i16mf4_b64(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16mf4_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i16mf2_b32(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16mf2_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i16m1_b16(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m1_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i16m2_b8(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m2_b8(op1,op2,carryin,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_i16m4_b4(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m4_b4(op1,op2,carryin,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_i16m8_b2(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m8_b2(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_i32mf2_b64(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32mf2_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i32m1_b32(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m1_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i32m2_b16(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m2_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i32m4_b8(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m4_b8(op1,op2,carryin,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_i32m8_b4(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m8_b4(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_i64m1_b64(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m1_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i64m2_b32(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m2_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i64m4_b16(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m4_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i64m8_b8(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m8_b8(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u8mf8_b64(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8mf8_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u8mf4_b32(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8mf4_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u8mf2_b16(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8mf2_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u8m1_b8(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m1_b8(op1,op2,carryin,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_u8m2_b4(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m2_b4(op1,op2,carryin,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_u8m4_b2(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m4_b2(op1,op2,carryin,vl);
+}
+
+
+vbool1_t test___riscv_vmadc_vxm_u8m8_b1(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m8_b1(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u16mf4_b64(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16mf4_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u16mf2_b32(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16mf2_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u16m1_b16(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m1_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u16m2_b8(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m2_b8(op1,op2,carryin,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_u16m4_b4(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m4_b4(op1,op2,carryin,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_u16m8_b2(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m8_b2(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u32mf2_b64(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32mf2_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u32m1_b32(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m1_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u32m2_b16(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m2_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u32m4_b8(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m4_b8(op1,op2,carryin,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_u32m8_b4(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m8_b4(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u64m1_b64(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m1_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u64m2_b32(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m2_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u64m4_b16(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m4_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u64m8_b8(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m8_b8(op1,op2,carryin,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-2.c
new file mode 100644
index 00000000000..0e9c06f0999
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-2.c
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmadc_vxm_i8mf8_b64(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8mf8_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i8mf4_b32(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8mf4_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i8mf2_b16(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8mf2_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i8m1_b8(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m1_b8(op1,op2,carryin,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_i8m2_b4(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m2_b4(op1,op2,carryin,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_i8m4_b2(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m4_b2(op1,op2,carryin,31);
+}
+
+
+vbool1_t test___riscv_vmadc_vxm_i8m8_b1(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m8_b1(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_i16mf4_b64(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16mf4_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i16mf2_b32(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16mf2_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i16m1_b16(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m1_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i16m2_b8(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m2_b8(op1,op2,carryin,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_i16m4_b4(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m4_b4(op1,op2,carryin,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_i16m8_b2(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m8_b2(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_i32mf2_b64(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32mf2_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i32m1_b32(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m1_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i32m2_b16(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m2_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i32m4_b8(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m4_b8(op1,op2,carryin,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_i32m8_b4(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m8_b4(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_i64m1_b64(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m1_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i64m2_b32(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m2_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i64m4_b16(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m4_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i64m8_b8(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m8_b8(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u8mf8_b64(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8mf8_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u8mf4_b32(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8mf4_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u8mf2_b16(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8mf2_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u8m1_b8(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m1_b8(op1,op2,carryin,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_u8m2_b4(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m2_b4(op1,op2,carryin,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_u8m4_b2(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m4_b2(op1,op2,carryin,31);
+}
+
+
+vbool1_t test___riscv_vmadc_vxm_u8m8_b1(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m8_b1(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u16mf4_b64(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16mf4_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u16mf2_b32(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16mf2_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u16m1_b16(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m1_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u16m2_b8(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m2_b8(op1,op2,carryin,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_u16m4_b4(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m4_b4(op1,op2,carryin,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_u16m8_b2(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m8_b2(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u32mf2_b64(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32mf2_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u32m1_b32(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m1_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u32m2_b16(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m2_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u32m4_b8(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m4_b8(op1,op2,carryin,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_u32m8_b4(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m8_b4(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u64m1_b64(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m1_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u64m2_b32(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m2_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u64m4_b16(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m4_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u64m8_b8(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m8_b8(op1,op2,carryin,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-3.c
new file mode 100644
index 00000000000..5b8254da92b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-3.c
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmadc_vxm_i8mf8_b64(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8mf8_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i8mf4_b32(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8mf4_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i8mf2_b16(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8mf2_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i8m1_b8(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m1_b8(op1,op2,carryin,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_i8m2_b4(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m2_b4(op1,op2,carryin,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_i8m4_b2(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m4_b2(op1,op2,carryin,32);
+}
+
+
+vbool1_t test___riscv_vmadc_vxm_i8m8_b1(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m8_b1(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_i16mf4_b64(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16mf4_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i16mf2_b32(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16mf2_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i16m1_b16(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m1_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i16m2_b8(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m2_b8(op1,op2,carryin,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_i16m4_b4(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m4_b4(op1,op2,carryin,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_i16m8_b2(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m8_b2(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_i32mf2_b64(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32mf2_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i32m1_b32(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m1_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i32m2_b16(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m2_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i32m4_b8(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m4_b8(op1,op2,carryin,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_i32m8_b4(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m8_b4(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_i64m1_b64(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m1_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i64m2_b32(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m2_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i64m4_b16(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m4_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i64m8_b8(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m8_b8(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u8mf8_b64(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8mf8_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u8mf4_b32(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8mf4_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u8mf2_b16(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8mf2_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u8m1_b8(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m1_b8(op1,op2,carryin,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_u8m2_b4(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m2_b4(op1,op2,carryin,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_u8m4_b2(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m4_b2(op1,op2,carryin,32);
+}
+
+
+vbool1_t test___riscv_vmadc_vxm_u8m8_b1(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m8_b1(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u16mf4_b64(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16mf4_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u16mf2_b32(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16mf2_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u16m1_b16(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m1_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u16m2_b8(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m2_b8(op1,op2,carryin,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_u16m4_b4(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m4_b4(op1,op2,carryin,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_u16m8_b2(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m8_b2(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u32mf2_b64(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32mf2_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u32m1_b32(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m1_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u32m2_b16(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m2_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u32m4_b8(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m4_b8(op1,op2,carryin,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_u32m8_b4(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m8_b4(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u64m1_b64(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m1_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u64m2_b32(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m2_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u64m4_b16(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m4_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u64m8_b8(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m8_b8(op1,op2,carryin,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vmadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-1.c
new file mode 100644
index 00000000000..98e77a102a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-1.c
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmadc_vxm_i8mf8_b64(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8mf8_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i8mf4_b32(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8mf4_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i8mf2_b16(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8mf2_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i8m1_b8(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m1_b8(op1,op2,carryin,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_i8m2_b4(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m2_b4(op1,op2,carryin,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_i8m4_b2(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m4_b2(op1,op2,carryin,vl);
+}
+
+
+vbool1_t test___riscv_vmadc_vxm_i8m8_b1(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m8_b1(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_i16mf4_b64(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16mf4_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i16mf2_b32(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16mf2_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i16m1_b16(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m1_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i16m2_b8(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m2_b8(op1,op2,carryin,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_i16m4_b4(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m4_b4(op1,op2,carryin,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_i16m8_b2(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m8_b2(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_i32mf2_b64(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32mf2_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i32m1_b32(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m1_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i32m2_b16(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m2_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i32m4_b8(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m4_b8(op1,op2,carryin,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_i32m8_b4(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m8_b4(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_i64m1_b64(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m1_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i64m2_b32(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m2_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i64m4_b16(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m4_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i64m8_b8(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m8_b8(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u8mf8_b64(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8mf8_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u8mf4_b32(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8mf4_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u8mf2_b16(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8mf2_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u8m1_b8(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m1_b8(op1,op2,carryin,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_u8m2_b4(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m2_b4(op1,op2,carryin,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_u8m4_b2(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m4_b2(op1,op2,carryin,vl);
+}
+
+
+vbool1_t test___riscv_vmadc_vxm_u8m8_b1(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m8_b1(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u16mf4_b64(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16mf4_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u16mf2_b32(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16mf2_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u16m1_b16(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m1_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u16m2_b8(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m2_b8(op1,op2,carryin,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_u16m4_b4(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m4_b4(op1,op2,carryin,vl);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_u16m8_b2(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m8_b2(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u32mf2_b64(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32mf2_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u32m1_b32(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m1_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u32m2_b16(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m2_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u32m4_b8(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m4_b8(op1,op2,carryin,vl);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_u32m8_b4(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m8_b4(op1,op2,carryin,vl);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u64m1_b64(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m1_b64(op1,op2,carryin,vl);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u64m2_b32(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m2_b32(op1,op2,carryin,vl);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u64m4_b16(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m4_b16(op1,op2,carryin,vl);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u64m8_b8(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m8_b8(op1,op2,carryin,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-2.c
new file mode 100644
index 00000000000..9cb64a2a5c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-2.c
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmadc_vxm_i8mf8_b64(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8mf8_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i8mf4_b32(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8mf4_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i8mf2_b16(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8mf2_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i8m1_b8(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m1_b8(op1,op2,carryin,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_i8m2_b4(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m2_b4(op1,op2,carryin,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_i8m4_b2(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m4_b2(op1,op2,carryin,31);
+}
+
+
+vbool1_t test___riscv_vmadc_vxm_i8m8_b1(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m8_b1(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_i16mf4_b64(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16mf4_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i16mf2_b32(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16mf2_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i16m1_b16(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m1_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i16m2_b8(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m2_b8(op1,op2,carryin,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_i16m4_b4(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m4_b4(op1,op2,carryin,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_i16m8_b2(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m8_b2(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_i32mf2_b64(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32mf2_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i32m1_b32(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m1_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i32m2_b16(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m2_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i32m4_b8(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m4_b8(op1,op2,carryin,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_i32m8_b4(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m8_b4(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_i64m1_b64(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m1_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i64m2_b32(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m2_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i64m4_b16(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m4_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i64m8_b8(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m8_b8(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u8mf8_b64(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8mf8_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u8mf4_b32(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8mf4_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u8mf2_b16(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8mf2_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u8m1_b8(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m1_b8(op1,op2,carryin,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_u8m2_b4(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m2_b4(op1,op2,carryin,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_u8m4_b2(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m4_b2(op1,op2,carryin,31);
+}
+
+
+vbool1_t test___riscv_vmadc_vxm_u8m8_b1(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m8_b1(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u16mf4_b64(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16mf4_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u16mf2_b32(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16mf2_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u16m1_b16(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m1_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u16m2_b8(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m2_b8(op1,op2,carryin,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_u16m4_b4(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m4_b4(op1,op2,carryin,31);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_u16m8_b2(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m8_b2(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u32mf2_b64(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32mf2_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u32m1_b32(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m1_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u32m2_b16(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m2_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u32m4_b8(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m4_b8(op1,op2,carryin,31);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_u32m8_b4(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m8_b4(op1,op2,carryin,31);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u64m1_b64(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m1_b64(op1,op2,carryin,31);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u64m2_b32(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m2_b32(op1,op2,carryin,31);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u64m4_b16(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m4_b16(op1,op2,carryin,31);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u64m8_b8(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m8_b8(op1,op2,carryin,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-3.c
new file mode 100644
index 00000000000..e7183e629c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-3.c
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmadc_vxm_i8mf8_b64(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8mf8_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i8mf4_b32(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8mf4_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i8mf2_b16(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8mf2_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i8m1_b8(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m1_b8(op1,op2,carryin,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_i8m2_b4(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m2_b4(op1,op2,carryin,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_i8m4_b2(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m4_b2(op1,op2,carryin,32);
+}
+
+
+vbool1_t test___riscv_vmadc_vxm_i8m8_b1(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i8m8_b1(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_i16mf4_b64(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16mf4_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i16mf2_b32(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16mf2_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i16m1_b16(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m1_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i16m2_b8(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m2_b8(op1,op2,carryin,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_i16m4_b4(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m4_b4(op1,op2,carryin,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_i16m8_b2(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i16m8_b2(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_i32mf2_b64(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32mf2_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i32m1_b32(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m1_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i32m2_b16(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m2_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i32m4_b8(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m4_b8(op1,op2,carryin,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_i32m8_b4(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i32m8_b4(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_i64m1_b64(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m1_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_i64m2_b32(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m2_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_i64m4_b16(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m4_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_i64m8_b8(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_i64m8_b8(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u8mf8_b64(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8mf8_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u8mf4_b32(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8mf4_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u8mf2_b16(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8mf2_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u8m1_b8(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m1_b8(op1,op2,carryin,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_u8m2_b4(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m2_b4(op1,op2,carryin,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_u8m4_b2(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m4_b2(op1,op2,carryin,32);
+}
+
+
+vbool1_t test___riscv_vmadc_vxm_u8m8_b1(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u8m8_b1(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u16mf4_b64(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16mf4_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u16mf2_b32(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16mf2_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u16m1_b16(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m1_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u16m2_b8(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m2_b8(op1,op2,carryin,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_u16m4_b4(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m4_b4(op1,op2,carryin,32);
+}
+
+
+vbool2_t test___riscv_vmadc_vxm_u16m8_b2(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u16m8_b2(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u32mf2_b64(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32mf2_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u32m1_b32(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m1_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u32m2_b16(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m2_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u32m4_b8(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m4_b8(op1,op2,carryin,32);
+}
+
+
+vbool4_t test___riscv_vmadc_vxm_u32m8_b4(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u32m8_b4(op1,op2,carryin,32);
+}
+
+
+vbool64_t test___riscv_vmadc_vxm_u64m1_b64(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m1_b64(op1,op2,carryin,32);
+}
+
+
+vbool32_t test___riscv_vmadc_vxm_u64m2_b32(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m2_b32(op1,op2,carryin,32);
+}
+
+
+vbool16_t test___riscv_vmadc_vxm_u64m4_b16(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m4_b16(op1,op2,carryin,32);
+}
+
+
+vbool8_t test___riscv_vmadc_vxm_u64m8_b8(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+    return __riscv_vmadc_vxm_u64m8_b8(op1,op2,carryin,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */