From patchwork Wed Feb 8 02:34:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 54144 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp3209133wrn; Tue, 7 Feb 2023 18:35:42 -0800 (PST) X-Google-Smtp-Source: AK7set/vRDCQvspqacUmwcDOLAcf/tCUSNL6GvV8zG25GcUuYEO/uthmfK/lxGFA5zybbL3I9EGk X-Received: by 2002:a50:cc95:0:b0:48f:68b1:db4e with SMTP id q21-20020a50cc95000000b0048f68b1db4emr5644798edi.27.1675823742365; Tue, 07 Feb 2023 18:35:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675823742; cv=none; d=google.com; s=arc-20160816; b=ePEdJiixWarpcwLGK5Pp0WSgUs3YvDQ2v5xBgUsIvfgxZtsjmgAuljOHVIS6KER+LP bHFgCQvfxH00sNlq66hQ8zPDNaYpOEhlfbd8dwldOJEXzEapInnyDAawtmMK41q5HAB1 7m1/mn6rO2fFZ5OEAA4bDeqpVKquFQRMeJOjHZgIlhyLcPalsx704smr5ACLVWHnTIVy egVZQmgMYxC870+MmjqbK1d+GxLYv19zzIZEDVb3YtYXXg4ur3gm9Eg7hNwH+J2cicgR s4zAxLPhGVyRigXgG6Vq5KozXd0KrIA0tywDI/tGTV69I4V9h7DZk1/3avGwg0UrmkY6 i1oA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:feedback-id :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:dmarc-filter:delivered-to; bh=u8uOW2aCRUcrYzR0/9T329hxQ08Bk8UZmUl6q245J3o=; b=W+YI+uq1dikuO3cI2kY1L/CpbdMRnYMdX6i+2wiUj3fL7Uz54svFKgHRmdDoNXx6lu TDDvep6zCfyZtJSdaCb+IVdM4ZMflSfdBoeJYjPpGRh8WBGtx+gEYgWRtdf08aN3BEii kuc1LIhbAF59s4gO971jCEUEJnJbLXVJxxwFtr4y8UrYPT2vs8sgV+5mteKhNpajXDX4 FNVkRPSpjJq3tTcgXBo91rtBtXOyLG37djRmG8he0nXU//q5C3PyW1AP7PxDjjOVQt4y 1Ru3UYwzSqOpikc0xEoZFfmj30tMIdLMeLdkaNLLrFcallIdcHso0NdXppk6akvdgFRk npKw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id v17-20020aa7dbd1000000b004aaa74dce26si10206370edt.569.2023.02.07.18.35.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Feb 2023 18:35:42 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 885A038582A1 for ; Wed, 8 Feb 2023 02:35:40 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) by sourceware.org (Postfix) with ESMTPS id 354883858D39 for ; Wed, 8 Feb 2023 02:34:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 354883858D39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp85t1675823686t7fgzlqj Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 08 Feb 2023 10:34:45 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: G9U7jez9saNq2b0MmM4oA1xOSOBZVYyPtJXK1+gbrFUCZsly03dRtgh31mk3u MeTAxqYQPVw9krDuzZHsWqVsWrBmtskLYRmCTpp3exmgqNw0mL/w7vhZlbufHXiyQv8gvrL B+FtOEyUwgctoT0kUo9gwMJ7mO7WM7zsnqSLhoAG5aCs1xatyF5nbcFnVWVRmtZ4tTct3b+ jvZZoLbBveZ/i4bYAsXZ3EEyknnbhaboY4/Dkr0m+RklzV3Jz2WsnOZD79SmCPiOULULYby fMFtPVvVewGiNge80GXOOzVhdPrfvG3SnNk4C3QGmakSlJfZ42D19kEG2uFoK9w4/T2/eYg 8OppMelGxK0u2uLJox+q2MGpPTOxXabOsptobJawEKl7p9QAl8= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vsbc.vvm/vsbc.vxm C API tests Date: Wed, 8 Feb 2023 10:34:30 +0800 Message-Id: <20230208023430.226464-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757228556327841521?= X-GMAIL-MSGID: =?utf-8?q?1757228556327841521?= From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vsbc-1.c: New test. * gcc.target/riscv/rvv/base/vsbc-2.c: New test. * gcc.target/riscv/rvv/base/vsbc-3.c: New test. * gcc.target/riscv/rvv/base/vsbc-4.c: New test. * gcc.target/riscv/rvv/base/vsbc_vvm-1.c: New test. * gcc.target/riscv/rvv/base/vsbc_vvm-2.c: New test. * gcc.target/riscv/rvv/base/vsbc_vvm-3.c: New test. * gcc.target/riscv/rvv/base/vsbc_vvm_tu-1.c: New test. * gcc.target/riscv/rvv/base/vsbc_vvm_tu-2.c: New test. * gcc.target/riscv/rvv/base/vsbc_vvm_tu-3.c: New test. * gcc.target/riscv/rvv/base/vsbc_vxm_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vsbc_vxm_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vsbc_vxm_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vsbc_vxm_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vsbc_vxm_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vsbc_vxm_rv64-3.c: New test. * gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.c: New test. --- .../gcc.target/riscv/rvv/base/vsbc-1.c | 27 ++ .../gcc.target/riscv/rvv/base/vsbc-2.c | 56 ++++ .../gcc.target/riscv/rvv/base/vsbc-3.c | 77 +++++ .../gcc.target/riscv/rvv/base/vsbc-4.c | 78 +++++ .../gcc.target/riscv/rvv/base/vsbc_vvm-1.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vvm-2.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vvm-3.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vvm_tu-1.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vvm_tu-2.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vvm_tu-3.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_rv32-1.c | 289 +++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_rv32-2.c | 289 +++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_rv32-3.c | 289 +++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_rv64-1.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_rv64-2.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_rv64-3.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_tu_rv32-1.c | 289 +++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_tu_rv32-2.c | 289 +++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_tu_rv32-3.c | 289 +++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_tu_rv64-1.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_tu_rv64-2.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_tu_rv64-3.c | 292 ++++++++++++++++++ 22 files changed, 5476 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-1.c new file mode 100644 index 00000000000..0ec5ac1f716 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-1.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +#include "riscv_vector.h" + +void f1 (void * in, void *out) +{ + vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vsbc_vvm_i32m1 (v2, v2, mask, 4); + vint32m1_t v4 = __riscv_vsbc_vvm_i32m1_tu (v3, v2, v2, mask, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +void f2 (void * in, void *out) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vsbc_vvm_i32m1 (v2, v2, mask, 4); + vint32m1_t v4 = __riscv_vsbc_vvm_i32m1_tu (v3, v2, v2, mask, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* { dg-final { scan-assembler-times {vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-2.c new file mode 100644 index 00000000000..02fd17edbf5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-2.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +#include "riscv_vector.h" + +void f0 (void * in, void *out, int32_t x) +{ + vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vsbc_vxm_i32m1 (v2, 0, mask, 4); + vint32m1_t v4 = __riscv_vsbc_vxm_i32m1_tu (v3, v2, 0, mask, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +void f1 (void * in, void *out, int32_t x) +{ + vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vsbc_vxm_i32m1 (v2, -16, mask, 4); + vint32m1_t v4 = __riscv_vsbc_vxm_i32m1_tu (v3, v2, -16, mask, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +void f2 (void * in, void *out, int32_t x) +{ + vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vsbc_vxm_i32m1 (v2, 15, mask, 4); + vint32m1_t v4 = __riscv_vsbc_vxm_i32m1_tu (v3, v2, 15, mask, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +void f3 (void * in, void *out, int32_t x) +{ + vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vsbc_vxm_i32m1 (v2, -17, mask, 4); + vint32m1_t v4 = __riscv_vsbc_vxm_i32m1_tu (v3, v2, -17, mask, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +void f4 (void * in, void *out, int32_t x) +{ + vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vsbc_vxm_i32m1 (v2, 16, mask, 4); + vint32m1_t v4 = __riscv_vsbc_vxm_i32m1_tu (v3, v2, 16, mask, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* { dg-final { scan-assembler-times {vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*zero,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-3.c new file mode 100644 index 00000000000..85feeb93a59 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-3.c @@ -0,0 +1,77 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +void f0 (void * in, void *out, int64_t x, int n) +{ + vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4); + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsbc_vxm_i64m1 (v2, 0, mask, 4); + vint64m1_t v4 = __riscv_vsbc_vxm_i64m1 (v3, 0, mask, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +void f1 (void * in, void *out, int64_t x, int n) +{ + vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4); + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsbc_vxm_i64m1 (v2, 15, mask, 4); + vint64m1_t v4 = __riscv_vsbc_vxm_i64m1 (v3, 15, mask, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +void f2 (void * in, void *out, int64_t x, int n) +{ + vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4); + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsbc_vxm_i64m1 (v2, -17, mask, 4); + vint64m1_t v4 = __riscv_vsbc_vxm_i64m1 (v3, -17, mask, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +void f3 (void * in, void *out, int64_t x, int n) +{ + vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4); + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsbc_vxm_i64m1 (v2, 16, mask, 4); + vint64m1_t v4 = __riscv_vsbc_vxm_i64m1 (v3, 16, mask, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +void f4 (void * in, void *out, int64_t x, int n) +{ + vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4); + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsbc_vxm_i64m1 (v2, 0xAAAAAAAA, mask, 4); + vint64m1_t v4 = __riscv_vsbc_vxm_i64m1 (v3, 0xAAAAAAAA, mask, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +void f5 (void * in, void *out, int64_t x, int n) +{ + vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4); + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsbc_vxm_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, mask, 4); + vint64m1_t v4 = __riscv_vsbc_vxm_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, mask, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +void f6 (void * in, void *out, int64_t x, int n) +{ + vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4); + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsbc_vxm_i64m1 (v2, x, mask, 4); + vint64m1_t v4 = __riscv_vsbc_vxm_i64m1 (v3, x, mask, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*zero,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-4.c new file mode 100644 index 00000000000..2f6c64db0b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-4.c @@ -0,0 +1,78 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ + +#include "riscv_vector.h" + +void f0 (void * in, void *out, int64_t x, int n) +{ + vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4); + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsbc_vxm_i64m1 (v2, 0, mask, 4); + vint64m1_t v4 = __riscv_vsbc_vxm_i64m1 (v3, 0, mask, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +void f1 (void * in, void *out, int64_t x, int n) +{ + vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4); + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsbc_vxm_i64m1 (v2, 15, mask, 4); + vint64m1_t v4 = __riscv_vsbc_vxm_i64m1 (v3, 15, mask, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +void f2 (void * in, void *out, int64_t x, int n) +{ + vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4); + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsbc_vxm_i64m1 (v2, -17, mask, 4); + vint64m1_t v4 = __riscv_vsbc_vxm_i64m1 (v3, -17, mask, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +void f3 (void * in, void *out, int64_t x, int n) +{ + vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4); + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsbc_vxm_i64m1 (v2, 16, mask, 4); + vint64m1_t v4 = __riscv_vsbc_vxm_i64m1 (v3, 16, mask, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +void f4 (void * in, void *out, int64_t x, int n) +{ + vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4); + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsbc_vxm_i64m1 (v2, 0xAAAAAAA, mask, 4); + vint64m1_t v4 = __riscv_vsbc_vxm_i64m1 (v3, 0xAAAAAAA, mask, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +void f5 (void * in, void *out, int64_t x, int n) +{ + vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4); + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsbc_vxm_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, mask, 4); + vint64m1_t v4 = __riscv_vsbc_vxm_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, mask, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +void f6 (void * in, void *out, int64_t x, int n) +{ + vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4); + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsbc_vxm_i64m1 (v2, x, mask, 4); + vint64m1_t v4 = __riscv_vsbc_vxm_i64m1 (v3, x, mask, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*zero,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 8 } } */ +/* { dg-final { scan-assembler-times {vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-1.c new file mode 100644 index 00000000000..6cc2acbcd78 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc_vvm_i8mf8(vint8mf8_t op1,vint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8mf8(op1,op2,borrowin,vl); +} + + +vint8mf4_t test___riscv_vsbc_vvm_i8mf4(vint8mf4_t op1,vint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8mf4(op1,op2,borrowin,vl); +} + + +vint8mf2_t test___riscv_vsbc_vvm_i8mf2(vint8mf2_t op1,vint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8mf2(op1,op2,borrowin,vl); +} + + +vint8m1_t test___riscv_vsbc_vvm_i8m1(vint8m1_t op1,vint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m1(op1,op2,borrowin,vl); +} + + +vint8m2_t test___riscv_vsbc_vvm_i8m2(vint8m2_t op1,vint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m2(op1,op2,borrowin,vl); +} + + +vint8m4_t test___riscv_vsbc_vvm_i8m4(vint8m4_t op1,vint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m4(op1,op2,borrowin,vl); +} + + +vint8m8_t test___riscv_vsbc_vvm_i8m8(vint8m8_t op1,vint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m8(op1,op2,borrowin,vl); +} + + +vint16mf4_t test___riscv_vsbc_vvm_i16mf4(vint16mf4_t op1,vint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16mf4(op1,op2,borrowin,vl); +} + + +vint16mf2_t test___riscv_vsbc_vvm_i16mf2(vint16mf2_t op1,vint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16mf2(op1,op2,borrowin,vl); +} + + +vint16m1_t test___riscv_vsbc_vvm_i16m1(vint16m1_t op1,vint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m1(op1,op2,borrowin,vl); +} + + +vint16m2_t test___riscv_vsbc_vvm_i16m2(vint16m2_t op1,vint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m2(op1,op2,borrowin,vl); +} + + +vint16m4_t test___riscv_vsbc_vvm_i16m4(vint16m4_t op1,vint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m4(op1,op2,borrowin,vl); +} + + +vint16m8_t test___riscv_vsbc_vvm_i16m8(vint16m8_t op1,vint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m8(op1,op2,borrowin,vl); +} + + +vint32mf2_t test___riscv_vsbc_vvm_i32mf2(vint32mf2_t op1,vint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32mf2(op1,op2,borrowin,vl); +} + + +vint32m1_t test___riscv_vsbc_vvm_i32m1(vint32m1_t op1,vint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m1(op1,op2,borrowin,vl); +} + + +vint32m2_t test___riscv_vsbc_vvm_i32m2(vint32m2_t op1,vint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m2(op1,op2,borrowin,vl); +} + + +vint32m4_t test___riscv_vsbc_vvm_i32m4(vint32m4_t op1,vint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m4(op1,op2,borrowin,vl); +} + + +vint32m8_t test___riscv_vsbc_vvm_i32m8(vint32m8_t op1,vint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m8(op1,op2,borrowin,vl); +} + + +vint64m1_t test___riscv_vsbc_vvm_i64m1(vint64m1_t op1,vint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m1(op1,op2,borrowin,vl); +} + + +vint64m2_t test___riscv_vsbc_vvm_i64m2(vint64m2_t op1,vint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m2(op1,op2,borrowin,vl); +} + + +vint64m4_t test___riscv_vsbc_vvm_i64m4(vint64m4_t op1,vint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m4(op1,op2,borrowin,vl); +} + + +vint64m8_t test___riscv_vsbc_vvm_i64m8(vint64m8_t op1,vint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m8(op1,op2,borrowin,vl); +} + + +vuint8mf8_t test___riscv_vsbc_vvm_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8mf8(op1,op2,borrowin,vl); +} + + +vuint8mf4_t test___riscv_vsbc_vvm_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8mf4(op1,op2,borrowin,vl); +} + + +vuint8mf2_t test___riscv_vsbc_vvm_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8mf2(op1,op2,borrowin,vl); +} + + +vuint8m1_t test___riscv_vsbc_vvm_u8m1(vuint8m1_t op1,vuint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m1(op1,op2,borrowin,vl); +} + + +vuint8m2_t test___riscv_vsbc_vvm_u8m2(vuint8m2_t op1,vuint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m2(op1,op2,borrowin,vl); +} + + +vuint8m4_t test___riscv_vsbc_vvm_u8m4(vuint8m4_t op1,vuint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m4(op1,op2,borrowin,vl); +} + + +vuint8m8_t test___riscv_vsbc_vvm_u8m8(vuint8m8_t op1,vuint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m8(op1,op2,borrowin,vl); +} + + +vuint16mf4_t test___riscv_vsbc_vvm_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16mf4(op1,op2,borrowin,vl); +} + + +vuint16mf2_t test___riscv_vsbc_vvm_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16mf2(op1,op2,borrowin,vl); +} + + +vuint16m1_t test___riscv_vsbc_vvm_u16m1(vuint16m1_t op1,vuint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m1(op1,op2,borrowin,vl); +} + + +vuint16m2_t test___riscv_vsbc_vvm_u16m2(vuint16m2_t op1,vuint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m2(op1,op2,borrowin,vl); +} + + +vuint16m4_t test___riscv_vsbc_vvm_u16m4(vuint16m4_t op1,vuint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m4(op1,op2,borrowin,vl); +} + + +vuint16m8_t test___riscv_vsbc_vvm_u16m8(vuint16m8_t op1,vuint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m8(op1,op2,borrowin,vl); +} + + +vuint32mf2_t test___riscv_vsbc_vvm_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32mf2(op1,op2,borrowin,vl); +} + + +vuint32m1_t test___riscv_vsbc_vvm_u32m1(vuint32m1_t op1,vuint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m1(op1,op2,borrowin,vl); +} + + +vuint32m2_t test___riscv_vsbc_vvm_u32m2(vuint32m2_t op1,vuint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m2(op1,op2,borrowin,vl); +} + + +vuint32m4_t test___riscv_vsbc_vvm_u32m4(vuint32m4_t op1,vuint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m4(op1,op2,borrowin,vl); +} + + +vuint32m8_t test___riscv_vsbc_vvm_u32m8(vuint32m8_t op1,vuint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m8(op1,op2,borrowin,vl); +} + + +vuint64m1_t test___riscv_vsbc_vvm_u64m1(vuint64m1_t op1,vuint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m1(op1,op2,borrowin,vl); +} + + +vuint64m2_t test___riscv_vsbc_vvm_u64m2(vuint64m2_t op1,vuint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m2(op1,op2,borrowin,vl); +} + + +vuint64m4_t test___riscv_vsbc_vvm_u64m4(vuint64m4_t op1,vuint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m4(op1,op2,borrowin,vl); +} + + +vuint64m8_t test___riscv_vsbc_vvm_u64m8(vuint64m8_t op1,vuint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m8(op1,op2,borrowin,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-2.c new file mode 100644 index 00000000000..b9efdf9632e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc_vvm_i8mf8(vint8mf8_t op1,vint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8mf8(op1,op2,borrowin,31); +} + + +vint8mf4_t test___riscv_vsbc_vvm_i8mf4(vint8mf4_t op1,vint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8mf4(op1,op2,borrowin,31); +} + + +vint8mf2_t test___riscv_vsbc_vvm_i8mf2(vint8mf2_t op1,vint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8mf2(op1,op2,borrowin,31); +} + + +vint8m1_t test___riscv_vsbc_vvm_i8m1(vint8m1_t op1,vint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m1(op1,op2,borrowin,31); +} + + +vint8m2_t test___riscv_vsbc_vvm_i8m2(vint8m2_t op1,vint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m2(op1,op2,borrowin,31); +} + + +vint8m4_t test___riscv_vsbc_vvm_i8m4(vint8m4_t op1,vint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m4(op1,op2,borrowin,31); +} + + +vint8m8_t test___riscv_vsbc_vvm_i8m8(vint8m8_t op1,vint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m8(op1,op2,borrowin,31); +} + + +vint16mf4_t test___riscv_vsbc_vvm_i16mf4(vint16mf4_t op1,vint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16mf4(op1,op2,borrowin,31); +} + + +vint16mf2_t test___riscv_vsbc_vvm_i16mf2(vint16mf2_t op1,vint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16mf2(op1,op2,borrowin,31); +} + + +vint16m1_t test___riscv_vsbc_vvm_i16m1(vint16m1_t op1,vint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m1(op1,op2,borrowin,31); +} + + +vint16m2_t test___riscv_vsbc_vvm_i16m2(vint16m2_t op1,vint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m2(op1,op2,borrowin,31); +} + + +vint16m4_t test___riscv_vsbc_vvm_i16m4(vint16m4_t op1,vint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m4(op1,op2,borrowin,31); +} + + +vint16m8_t test___riscv_vsbc_vvm_i16m8(vint16m8_t op1,vint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m8(op1,op2,borrowin,31); +} + + +vint32mf2_t test___riscv_vsbc_vvm_i32mf2(vint32mf2_t op1,vint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32mf2(op1,op2,borrowin,31); +} + + +vint32m1_t test___riscv_vsbc_vvm_i32m1(vint32m1_t op1,vint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m1(op1,op2,borrowin,31); +} + + +vint32m2_t test___riscv_vsbc_vvm_i32m2(vint32m2_t op1,vint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m2(op1,op2,borrowin,31); +} + + +vint32m4_t test___riscv_vsbc_vvm_i32m4(vint32m4_t op1,vint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m4(op1,op2,borrowin,31); +} + + +vint32m8_t test___riscv_vsbc_vvm_i32m8(vint32m8_t op1,vint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m8(op1,op2,borrowin,31); +} + + +vint64m1_t test___riscv_vsbc_vvm_i64m1(vint64m1_t op1,vint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m1(op1,op2,borrowin,31); +} + + +vint64m2_t test___riscv_vsbc_vvm_i64m2(vint64m2_t op1,vint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m2(op1,op2,borrowin,31); +} + + +vint64m4_t test___riscv_vsbc_vvm_i64m4(vint64m4_t op1,vint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m4(op1,op2,borrowin,31); +} + + +vint64m8_t test___riscv_vsbc_vvm_i64m8(vint64m8_t op1,vint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m8(op1,op2,borrowin,31); +} + + +vuint8mf8_t test___riscv_vsbc_vvm_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8mf8(op1,op2,borrowin,31); +} + + +vuint8mf4_t test___riscv_vsbc_vvm_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8mf4(op1,op2,borrowin,31); +} + + +vuint8mf2_t test___riscv_vsbc_vvm_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8mf2(op1,op2,borrowin,31); +} + + +vuint8m1_t test___riscv_vsbc_vvm_u8m1(vuint8m1_t op1,vuint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m1(op1,op2,borrowin,31); +} + + +vuint8m2_t test___riscv_vsbc_vvm_u8m2(vuint8m2_t op1,vuint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m2(op1,op2,borrowin,31); +} + + +vuint8m4_t test___riscv_vsbc_vvm_u8m4(vuint8m4_t op1,vuint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m4(op1,op2,borrowin,31); +} + + +vuint8m8_t test___riscv_vsbc_vvm_u8m8(vuint8m8_t op1,vuint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m8(op1,op2,borrowin,31); +} + + +vuint16mf4_t test___riscv_vsbc_vvm_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16mf4(op1,op2,borrowin,31); +} + + +vuint16mf2_t test___riscv_vsbc_vvm_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16mf2(op1,op2,borrowin,31); +} + + +vuint16m1_t test___riscv_vsbc_vvm_u16m1(vuint16m1_t op1,vuint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m1(op1,op2,borrowin,31); +} + + +vuint16m2_t test___riscv_vsbc_vvm_u16m2(vuint16m2_t op1,vuint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m2(op1,op2,borrowin,31); +} + + +vuint16m4_t test___riscv_vsbc_vvm_u16m4(vuint16m4_t op1,vuint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m4(op1,op2,borrowin,31); +} + + +vuint16m8_t test___riscv_vsbc_vvm_u16m8(vuint16m8_t op1,vuint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m8(op1,op2,borrowin,31); +} + + +vuint32mf2_t test___riscv_vsbc_vvm_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32mf2(op1,op2,borrowin,31); +} + + +vuint32m1_t test___riscv_vsbc_vvm_u32m1(vuint32m1_t op1,vuint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m1(op1,op2,borrowin,31); +} + + +vuint32m2_t test___riscv_vsbc_vvm_u32m2(vuint32m2_t op1,vuint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m2(op1,op2,borrowin,31); +} + + +vuint32m4_t test___riscv_vsbc_vvm_u32m4(vuint32m4_t op1,vuint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m4(op1,op2,borrowin,31); +} + + +vuint32m8_t test___riscv_vsbc_vvm_u32m8(vuint32m8_t op1,vuint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m8(op1,op2,borrowin,31); +} + + +vuint64m1_t test___riscv_vsbc_vvm_u64m1(vuint64m1_t op1,vuint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m1(op1,op2,borrowin,31); +} + + +vuint64m2_t test___riscv_vsbc_vvm_u64m2(vuint64m2_t op1,vuint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m2(op1,op2,borrowin,31); +} + + +vuint64m4_t test___riscv_vsbc_vvm_u64m4(vuint64m4_t op1,vuint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m4(op1,op2,borrowin,31); +} + + +vuint64m8_t test___riscv_vsbc_vvm_u64m8(vuint64m8_t op1,vuint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m8(op1,op2,borrowin,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-3.c new file mode 100644 index 00000000000..1dbb7b90c53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc_vvm_i8mf8(vint8mf8_t op1,vint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8mf8(op1,op2,borrowin,32); +} + + +vint8mf4_t test___riscv_vsbc_vvm_i8mf4(vint8mf4_t op1,vint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8mf4(op1,op2,borrowin,32); +} + + +vint8mf2_t test___riscv_vsbc_vvm_i8mf2(vint8mf2_t op1,vint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8mf2(op1,op2,borrowin,32); +} + + +vint8m1_t test___riscv_vsbc_vvm_i8m1(vint8m1_t op1,vint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m1(op1,op2,borrowin,32); +} + + +vint8m2_t test___riscv_vsbc_vvm_i8m2(vint8m2_t op1,vint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m2(op1,op2,borrowin,32); +} + + +vint8m4_t test___riscv_vsbc_vvm_i8m4(vint8m4_t op1,vint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m4(op1,op2,borrowin,32); +} + + +vint8m8_t test___riscv_vsbc_vvm_i8m8(vint8m8_t op1,vint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m8(op1,op2,borrowin,32); +} + + +vint16mf4_t test___riscv_vsbc_vvm_i16mf4(vint16mf4_t op1,vint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16mf4(op1,op2,borrowin,32); +} + + +vint16mf2_t test___riscv_vsbc_vvm_i16mf2(vint16mf2_t op1,vint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16mf2(op1,op2,borrowin,32); +} + + +vint16m1_t test___riscv_vsbc_vvm_i16m1(vint16m1_t op1,vint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m1(op1,op2,borrowin,32); +} + + +vint16m2_t test___riscv_vsbc_vvm_i16m2(vint16m2_t op1,vint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m2(op1,op2,borrowin,32); +} + + +vint16m4_t test___riscv_vsbc_vvm_i16m4(vint16m4_t op1,vint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m4(op1,op2,borrowin,32); +} + + +vint16m8_t test___riscv_vsbc_vvm_i16m8(vint16m8_t op1,vint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m8(op1,op2,borrowin,32); +} + + +vint32mf2_t test___riscv_vsbc_vvm_i32mf2(vint32mf2_t op1,vint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32mf2(op1,op2,borrowin,32); +} + + +vint32m1_t test___riscv_vsbc_vvm_i32m1(vint32m1_t op1,vint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m1(op1,op2,borrowin,32); +} + + +vint32m2_t test___riscv_vsbc_vvm_i32m2(vint32m2_t op1,vint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m2(op1,op2,borrowin,32); +} + + +vint32m4_t test___riscv_vsbc_vvm_i32m4(vint32m4_t op1,vint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m4(op1,op2,borrowin,32); +} + + +vint32m8_t test___riscv_vsbc_vvm_i32m8(vint32m8_t op1,vint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m8(op1,op2,borrowin,32); +} + + +vint64m1_t test___riscv_vsbc_vvm_i64m1(vint64m1_t op1,vint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m1(op1,op2,borrowin,32); +} + + +vint64m2_t test___riscv_vsbc_vvm_i64m2(vint64m2_t op1,vint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m2(op1,op2,borrowin,32); +} + + +vint64m4_t test___riscv_vsbc_vvm_i64m4(vint64m4_t op1,vint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m4(op1,op2,borrowin,32); +} + + +vint64m8_t test___riscv_vsbc_vvm_i64m8(vint64m8_t op1,vint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m8(op1,op2,borrowin,32); +} + + +vuint8mf8_t test___riscv_vsbc_vvm_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8mf8(op1,op2,borrowin,32); +} + + +vuint8mf4_t test___riscv_vsbc_vvm_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8mf4(op1,op2,borrowin,32); +} + + +vuint8mf2_t test___riscv_vsbc_vvm_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8mf2(op1,op2,borrowin,32); +} + + +vuint8m1_t test___riscv_vsbc_vvm_u8m1(vuint8m1_t op1,vuint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m1(op1,op2,borrowin,32); +} + + +vuint8m2_t test___riscv_vsbc_vvm_u8m2(vuint8m2_t op1,vuint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m2(op1,op2,borrowin,32); +} + + +vuint8m4_t test___riscv_vsbc_vvm_u8m4(vuint8m4_t op1,vuint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m4(op1,op2,borrowin,32); +} + + +vuint8m8_t test___riscv_vsbc_vvm_u8m8(vuint8m8_t op1,vuint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m8(op1,op2,borrowin,32); +} + + +vuint16mf4_t test___riscv_vsbc_vvm_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16mf4(op1,op2,borrowin,32); +} + + +vuint16mf2_t test___riscv_vsbc_vvm_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16mf2(op1,op2,borrowin,32); +} + + +vuint16m1_t test___riscv_vsbc_vvm_u16m1(vuint16m1_t op1,vuint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m1(op1,op2,borrowin,32); +} + + +vuint16m2_t test___riscv_vsbc_vvm_u16m2(vuint16m2_t op1,vuint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m2(op1,op2,borrowin,32); +} + + +vuint16m4_t test___riscv_vsbc_vvm_u16m4(vuint16m4_t op1,vuint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m4(op1,op2,borrowin,32); +} + + +vuint16m8_t test___riscv_vsbc_vvm_u16m8(vuint16m8_t op1,vuint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m8(op1,op2,borrowin,32); +} + + +vuint32mf2_t test___riscv_vsbc_vvm_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32mf2(op1,op2,borrowin,32); +} + + +vuint32m1_t test___riscv_vsbc_vvm_u32m1(vuint32m1_t op1,vuint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m1(op1,op2,borrowin,32); +} + + +vuint32m2_t test___riscv_vsbc_vvm_u32m2(vuint32m2_t op1,vuint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m2(op1,op2,borrowin,32); +} + + +vuint32m4_t test___riscv_vsbc_vvm_u32m4(vuint32m4_t op1,vuint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m4(op1,op2,borrowin,32); +} + + +vuint32m8_t test___riscv_vsbc_vvm_u32m8(vuint32m8_t op1,vuint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m8(op1,op2,borrowin,32); +} + + +vuint64m1_t test___riscv_vsbc_vvm_u64m1(vuint64m1_t op1,vuint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m1(op1,op2,borrowin,32); +} + + +vuint64m2_t test___riscv_vsbc_vvm_u64m2(vuint64m2_t op1,vuint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m2(op1,op2,borrowin,32); +} + + +vuint64m4_t test___riscv_vsbc_vvm_u64m4(vuint64m4_t op1,vuint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m4(op1,op2,borrowin,32); +} + + +vuint64m8_t test___riscv_vsbc_vvm_u64m8(vuint64m8_t op1,vuint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m8(op1,op2,borrowin,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-1.c new file mode 100644 index 00000000000..f45a90a2720 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc_vvm_i8mf8_tu(vint8mf8_t maskedoff,vint8mf8_t op1,vint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8mf8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8mf4_t test___riscv_vsbc_vvm_i8mf4_tu(vint8mf4_t maskedoff,vint8mf4_t op1,vint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8mf4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8mf2_t test___riscv_vsbc_vvm_i8mf2_tu(vint8mf2_t maskedoff,vint8mf2_t op1,vint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8mf2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m1_t test___riscv_vsbc_vvm_i8m1_tu(vint8m1_t maskedoff,vint8m1_t op1,vint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m2_t test___riscv_vsbc_vvm_i8m2_tu(vint8m2_t maskedoff,vint8m2_t op1,vint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m4_t test___riscv_vsbc_vvm_i8m4_tu(vint8m4_t maskedoff,vint8m4_t op1,vint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m8_t test___riscv_vsbc_vvm_i8m8_tu(vint8m8_t maskedoff,vint8m8_t op1,vint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16mf4_t test___riscv_vsbc_vvm_i16mf4_tu(vint16mf4_t maskedoff,vint16mf4_t op1,vint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16mf4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16mf2_t test___riscv_vsbc_vvm_i16mf2_tu(vint16mf2_t maskedoff,vint16mf2_t op1,vint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16mf2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m1_t test___riscv_vsbc_vvm_i16m1_tu(vint16m1_t maskedoff,vint16m1_t op1,vint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m2_t test___riscv_vsbc_vvm_i16m2_tu(vint16m2_t maskedoff,vint16m2_t op1,vint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m4_t test___riscv_vsbc_vvm_i16m4_tu(vint16m4_t maskedoff,vint16m4_t op1,vint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m8_t test___riscv_vsbc_vvm_i16m8_tu(vint16m8_t maskedoff,vint16m8_t op1,vint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32mf2_t test___riscv_vsbc_vvm_i32mf2_tu(vint32mf2_t maskedoff,vint32mf2_t op1,vint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32mf2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m1_t test___riscv_vsbc_vvm_i32m1_tu(vint32m1_t maskedoff,vint32m1_t op1,vint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m2_t test___riscv_vsbc_vvm_i32m2_tu(vint32m2_t maskedoff,vint32m2_t op1,vint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m4_t test___riscv_vsbc_vvm_i32m4_tu(vint32m4_t maskedoff,vint32m4_t op1,vint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m8_t test___riscv_vsbc_vvm_i32m8_tu(vint32m8_t maskedoff,vint32m8_t op1,vint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m1_t test___riscv_vsbc_vvm_i64m1_tu(vint64m1_t maskedoff,vint64m1_t op1,vint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m2_t test___riscv_vsbc_vvm_i64m2_tu(vint64m2_t maskedoff,vint64m2_t op1,vint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m4_t test___riscv_vsbc_vvm_i64m4_tu(vint64m4_t maskedoff,vint64m4_t op1,vint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m8_t test___riscv_vsbc_vvm_i64m8_tu(vint64m8_t maskedoff,vint64m8_t op1,vint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8mf8_t test___riscv_vsbc_vvm_u8mf8_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8mf8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8mf4_t test___riscv_vsbc_vvm_u8mf4_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8mf4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8mf2_t test___riscv_vsbc_vvm_u8mf2_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8mf2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m1_t test___riscv_vsbc_vvm_u8m1_tu(vuint8m1_t maskedoff,vuint8m1_t op1,vuint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m2_t test___riscv_vsbc_vvm_u8m2_tu(vuint8m2_t maskedoff,vuint8m2_t op1,vuint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m4_t test___riscv_vsbc_vvm_u8m4_tu(vuint8m4_t maskedoff,vuint8m4_t op1,vuint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m8_t test___riscv_vsbc_vvm_u8m8_tu(vuint8m8_t maskedoff,vuint8m8_t op1,vuint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16mf4_t test___riscv_vsbc_vvm_u16mf4_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16mf4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16mf2_t test___riscv_vsbc_vvm_u16mf2_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16mf2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m1_t test___riscv_vsbc_vvm_u16m1_tu(vuint16m1_t maskedoff,vuint16m1_t op1,vuint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m2_t test___riscv_vsbc_vvm_u16m2_tu(vuint16m2_t maskedoff,vuint16m2_t op1,vuint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m4_t test___riscv_vsbc_vvm_u16m4_tu(vuint16m4_t maskedoff,vuint16m4_t op1,vuint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m8_t test___riscv_vsbc_vvm_u16m8_tu(vuint16m8_t maskedoff,vuint16m8_t op1,vuint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32mf2_t test___riscv_vsbc_vvm_u32mf2_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32mf2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m1_t test___riscv_vsbc_vvm_u32m1_tu(vuint32m1_t maskedoff,vuint32m1_t op1,vuint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m2_t test___riscv_vsbc_vvm_u32m2_tu(vuint32m2_t maskedoff,vuint32m2_t op1,vuint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m4_t test___riscv_vsbc_vvm_u32m4_tu(vuint32m4_t maskedoff,vuint32m4_t op1,vuint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m8_t test___riscv_vsbc_vvm_u32m8_tu(vuint32m8_t maskedoff,vuint32m8_t op1,vuint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m1_t test___riscv_vsbc_vvm_u64m1_tu(vuint64m1_t maskedoff,vuint64m1_t op1,vuint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m2_t test___riscv_vsbc_vvm_u64m2_tu(vuint64m2_t maskedoff,vuint64m2_t op1,vuint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m4_t test___riscv_vsbc_vvm_u64m4_tu(vuint64m4_t maskedoff,vuint64m4_t op1,vuint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m8_t test___riscv_vsbc_vvm_u64m8_tu(vuint64m8_t maskedoff,vuint64m8_t op1,vuint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-2.c new file mode 100644 index 00000000000..e646d336544 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc_vvm_i8mf8_tu(vint8mf8_t maskedoff,vint8mf8_t op1,vint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8mf8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8mf4_t test___riscv_vsbc_vvm_i8mf4_tu(vint8mf4_t maskedoff,vint8mf4_t op1,vint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8mf4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8mf2_t test___riscv_vsbc_vvm_i8mf2_tu(vint8mf2_t maskedoff,vint8mf2_t op1,vint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8mf2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m1_t test___riscv_vsbc_vvm_i8m1_tu(vint8m1_t maskedoff,vint8m1_t op1,vint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m2_t test___riscv_vsbc_vvm_i8m2_tu(vint8m2_t maskedoff,vint8m2_t op1,vint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m4_t test___riscv_vsbc_vvm_i8m4_tu(vint8m4_t maskedoff,vint8m4_t op1,vint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m8_t test___riscv_vsbc_vvm_i8m8_tu(vint8m8_t maskedoff,vint8m8_t op1,vint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16mf4_t test___riscv_vsbc_vvm_i16mf4_tu(vint16mf4_t maskedoff,vint16mf4_t op1,vint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16mf4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16mf2_t test___riscv_vsbc_vvm_i16mf2_tu(vint16mf2_t maskedoff,vint16mf2_t op1,vint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16mf2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m1_t test___riscv_vsbc_vvm_i16m1_tu(vint16m1_t maskedoff,vint16m1_t op1,vint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m2_t test___riscv_vsbc_vvm_i16m2_tu(vint16m2_t maskedoff,vint16m2_t op1,vint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m4_t test___riscv_vsbc_vvm_i16m4_tu(vint16m4_t maskedoff,vint16m4_t op1,vint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m8_t test___riscv_vsbc_vvm_i16m8_tu(vint16m8_t maskedoff,vint16m8_t op1,vint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32mf2_t test___riscv_vsbc_vvm_i32mf2_tu(vint32mf2_t maskedoff,vint32mf2_t op1,vint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32mf2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m1_t test___riscv_vsbc_vvm_i32m1_tu(vint32m1_t maskedoff,vint32m1_t op1,vint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m2_t test___riscv_vsbc_vvm_i32m2_tu(vint32m2_t maskedoff,vint32m2_t op1,vint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m4_t test___riscv_vsbc_vvm_i32m4_tu(vint32m4_t maskedoff,vint32m4_t op1,vint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m8_t test___riscv_vsbc_vvm_i32m8_tu(vint32m8_t maskedoff,vint32m8_t op1,vint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m1_t test___riscv_vsbc_vvm_i64m1_tu(vint64m1_t maskedoff,vint64m1_t op1,vint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m2_t test___riscv_vsbc_vvm_i64m2_tu(vint64m2_t maskedoff,vint64m2_t op1,vint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m4_t test___riscv_vsbc_vvm_i64m4_tu(vint64m4_t maskedoff,vint64m4_t op1,vint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m8_t test___riscv_vsbc_vvm_i64m8_tu(vint64m8_t maskedoff,vint64m8_t op1,vint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8mf8_t test___riscv_vsbc_vvm_u8mf8_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8mf8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8mf4_t test___riscv_vsbc_vvm_u8mf4_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8mf4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8mf2_t test___riscv_vsbc_vvm_u8mf2_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8mf2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m1_t test___riscv_vsbc_vvm_u8m1_tu(vuint8m1_t maskedoff,vuint8m1_t op1,vuint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m2_t test___riscv_vsbc_vvm_u8m2_tu(vuint8m2_t maskedoff,vuint8m2_t op1,vuint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m4_t test___riscv_vsbc_vvm_u8m4_tu(vuint8m4_t maskedoff,vuint8m4_t op1,vuint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m8_t test___riscv_vsbc_vvm_u8m8_tu(vuint8m8_t maskedoff,vuint8m8_t op1,vuint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16mf4_t test___riscv_vsbc_vvm_u16mf4_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16mf4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16mf2_t test___riscv_vsbc_vvm_u16mf2_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16mf2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m1_t test___riscv_vsbc_vvm_u16m1_tu(vuint16m1_t maskedoff,vuint16m1_t op1,vuint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m2_t test___riscv_vsbc_vvm_u16m2_tu(vuint16m2_t maskedoff,vuint16m2_t op1,vuint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m4_t test___riscv_vsbc_vvm_u16m4_tu(vuint16m4_t maskedoff,vuint16m4_t op1,vuint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m8_t test___riscv_vsbc_vvm_u16m8_tu(vuint16m8_t maskedoff,vuint16m8_t op1,vuint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32mf2_t test___riscv_vsbc_vvm_u32mf2_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32mf2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m1_t test___riscv_vsbc_vvm_u32m1_tu(vuint32m1_t maskedoff,vuint32m1_t op1,vuint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m2_t test___riscv_vsbc_vvm_u32m2_tu(vuint32m2_t maskedoff,vuint32m2_t op1,vuint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m4_t test___riscv_vsbc_vvm_u32m4_tu(vuint32m4_t maskedoff,vuint32m4_t op1,vuint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m8_t test___riscv_vsbc_vvm_u32m8_tu(vuint32m8_t maskedoff,vuint32m8_t op1,vuint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m1_t test___riscv_vsbc_vvm_u64m1_tu(vuint64m1_t maskedoff,vuint64m1_t op1,vuint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m2_t test___riscv_vsbc_vvm_u64m2_tu(vuint64m2_t maskedoff,vuint64m2_t op1,vuint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m4_t test___riscv_vsbc_vvm_u64m4_tu(vuint64m4_t maskedoff,vuint64m4_t op1,vuint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m8_t test___riscv_vsbc_vvm_u64m8_tu(vuint64m8_t maskedoff,vuint64m8_t op1,vuint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m8_tu(maskedoff,op1,op2,borrowin,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-3.c new file mode 100644 index 00000000000..6bf79680fc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc_vvm_i8mf8_tu(vint8mf8_t maskedoff,vint8mf8_t op1,vint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8mf8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8mf4_t test___riscv_vsbc_vvm_i8mf4_tu(vint8mf4_t maskedoff,vint8mf4_t op1,vint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8mf4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8mf2_t test___riscv_vsbc_vvm_i8mf2_tu(vint8mf2_t maskedoff,vint8mf2_t op1,vint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8mf2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m1_t test___riscv_vsbc_vvm_i8m1_tu(vint8m1_t maskedoff,vint8m1_t op1,vint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m2_t test___riscv_vsbc_vvm_i8m2_tu(vint8m2_t maskedoff,vint8m2_t op1,vint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m4_t test___riscv_vsbc_vvm_i8m4_tu(vint8m4_t maskedoff,vint8m4_t op1,vint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m8_t test___riscv_vsbc_vvm_i8m8_tu(vint8m8_t maskedoff,vint8m8_t op1,vint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i8m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16mf4_t test___riscv_vsbc_vvm_i16mf4_tu(vint16mf4_t maskedoff,vint16mf4_t op1,vint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16mf4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16mf2_t test___riscv_vsbc_vvm_i16mf2_tu(vint16mf2_t maskedoff,vint16mf2_t op1,vint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16mf2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m1_t test___riscv_vsbc_vvm_i16m1_tu(vint16m1_t maskedoff,vint16m1_t op1,vint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m2_t test___riscv_vsbc_vvm_i16m2_tu(vint16m2_t maskedoff,vint16m2_t op1,vint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m4_t test___riscv_vsbc_vvm_i16m4_tu(vint16m4_t maskedoff,vint16m4_t op1,vint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m8_t test___riscv_vsbc_vvm_i16m8_tu(vint16m8_t maskedoff,vint16m8_t op1,vint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i16m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32mf2_t test___riscv_vsbc_vvm_i32mf2_tu(vint32mf2_t maskedoff,vint32mf2_t op1,vint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32mf2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m1_t test___riscv_vsbc_vvm_i32m1_tu(vint32m1_t maskedoff,vint32m1_t op1,vint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m2_t test___riscv_vsbc_vvm_i32m2_tu(vint32m2_t maskedoff,vint32m2_t op1,vint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m4_t test___riscv_vsbc_vvm_i32m4_tu(vint32m4_t maskedoff,vint32m4_t op1,vint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m8_t test___riscv_vsbc_vvm_i32m8_tu(vint32m8_t maskedoff,vint32m8_t op1,vint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i32m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m1_t test___riscv_vsbc_vvm_i64m1_tu(vint64m1_t maskedoff,vint64m1_t op1,vint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m2_t test___riscv_vsbc_vvm_i64m2_tu(vint64m2_t maskedoff,vint64m2_t op1,vint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m4_t test___riscv_vsbc_vvm_i64m4_tu(vint64m4_t maskedoff,vint64m4_t op1,vint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m8_t test___riscv_vsbc_vvm_i64m8_tu(vint64m8_t maskedoff,vint64m8_t op1,vint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_i64m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8mf8_t test___riscv_vsbc_vvm_u8mf8_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8mf8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8mf4_t test___riscv_vsbc_vvm_u8mf4_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8mf4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8mf2_t test___riscv_vsbc_vvm_u8mf2_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8mf2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m1_t test___riscv_vsbc_vvm_u8m1_tu(vuint8m1_t maskedoff,vuint8m1_t op1,vuint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m2_t test___riscv_vsbc_vvm_u8m2_tu(vuint8m2_t maskedoff,vuint8m2_t op1,vuint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m4_t test___riscv_vsbc_vvm_u8m4_tu(vuint8m4_t maskedoff,vuint8m4_t op1,vuint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m8_t test___riscv_vsbc_vvm_u8m8_tu(vuint8m8_t maskedoff,vuint8m8_t op1,vuint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u8m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16mf4_t test___riscv_vsbc_vvm_u16mf4_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16mf4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16mf2_t test___riscv_vsbc_vvm_u16mf2_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16mf2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m1_t test___riscv_vsbc_vvm_u16m1_tu(vuint16m1_t maskedoff,vuint16m1_t op1,vuint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m2_t test___riscv_vsbc_vvm_u16m2_tu(vuint16m2_t maskedoff,vuint16m2_t op1,vuint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m4_t test___riscv_vsbc_vvm_u16m4_tu(vuint16m4_t maskedoff,vuint16m4_t op1,vuint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m8_t test___riscv_vsbc_vvm_u16m8_tu(vuint16m8_t maskedoff,vuint16m8_t op1,vuint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u16m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32mf2_t test___riscv_vsbc_vvm_u32mf2_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32mf2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m1_t test___riscv_vsbc_vvm_u32m1_tu(vuint32m1_t maskedoff,vuint32m1_t op1,vuint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m2_t test___riscv_vsbc_vvm_u32m2_tu(vuint32m2_t maskedoff,vuint32m2_t op1,vuint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m4_t test___riscv_vsbc_vvm_u32m4_tu(vuint32m4_t maskedoff,vuint32m4_t op1,vuint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m8_t test___riscv_vsbc_vvm_u32m8_tu(vuint32m8_t maskedoff,vuint32m8_t op1,vuint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u32m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m1_t test___riscv_vsbc_vvm_u64m1_tu(vuint64m1_t maskedoff,vuint64m1_t op1,vuint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m2_t test___riscv_vsbc_vvm_u64m2_tu(vuint64m2_t maskedoff,vuint64m2_t op1,vuint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m4_t test___riscv_vsbc_vvm_u64m4_tu(vuint64m4_t maskedoff,vuint64m4_t op1,vuint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m8_t test___riscv_vsbc_vvm_u64m8_tu(vuint64m8_t maskedoff,vuint64m8_t op1,vuint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vvm_u64m8_tu(maskedoff,op1,op2,borrowin,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-1.c new file mode 100644 index 00000000000..327dcd98c63 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-1.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc_vxm_i8mf8(vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf8(op1,op2,borrowin,vl); +} + + +vint8mf4_t test___riscv_vsbc_vxm_i8mf4(vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf4(op1,op2,borrowin,vl); +} + + +vint8mf2_t test___riscv_vsbc_vxm_i8mf2(vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf2(op1,op2,borrowin,vl); +} + + +vint8m1_t test___riscv_vsbc_vxm_i8m1(vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m1(op1,op2,borrowin,vl); +} + + +vint8m2_t test___riscv_vsbc_vxm_i8m2(vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m2(op1,op2,borrowin,vl); +} + + +vint8m4_t test___riscv_vsbc_vxm_i8m4(vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m4(op1,op2,borrowin,vl); +} + + +vint8m8_t test___riscv_vsbc_vxm_i8m8(vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m8(op1,op2,borrowin,vl); +} + + +vint16mf4_t test___riscv_vsbc_vxm_i16mf4(vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf4(op1,op2,borrowin,vl); +} + + +vint16mf2_t test___riscv_vsbc_vxm_i16mf2(vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf2(op1,op2,borrowin,vl); +} + + +vint16m1_t test___riscv_vsbc_vxm_i16m1(vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m1(op1,op2,borrowin,vl); +} + + +vint16m2_t test___riscv_vsbc_vxm_i16m2(vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m2(op1,op2,borrowin,vl); +} + + +vint16m4_t test___riscv_vsbc_vxm_i16m4(vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m4(op1,op2,borrowin,vl); +} + + +vint16m8_t test___riscv_vsbc_vxm_i16m8(vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m8(op1,op2,borrowin,vl); +} + + +vint32mf2_t test___riscv_vsbc_vxm_i32mf2(vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32mf2(op1,op2,borrowin,vl); +} + + +vint32m1_t test___riscv_vsbc_vxm_i32m1(vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m1(op1,op2,borrowin,vl); +} + + +vint32m2_t test___riscv_vsbc_vxm_i32m2(vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m2(op1,op2,borrowin,vl); +} + + +vint32m4_t test___riscv_vsbc_vxm_i32m4(vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m4(op1,op2,borrowin,vl); +} + + +vint32m8_t test___riscv_vsbc_vxm_i32m8(vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m8(op1,op2,borrowin,vl); +} + + +vint64m1_t test___riscv_vsbc_vxm_i64m1(vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m1(op1,op2,borrowin,vl); +} + + +vint64m2_t test___riscv_vsbc_vxm_i64m2(vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m2(op1,op2,borrowin,vl); +} + + +vint64m4_t test___riscv_vsbc_vxm_i64m4(vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m4(op1,op2,borrowin,vl); +} + + +vint64m8_t test___riscv_vsbc_vxm_i64m8(vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m8(op1,op2,borrowin,vl); +} + + +vuint8mf8_t test___riscv_vsbc_vxm_u8mf8(vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf8(op1,op2,borrowin,vl); +} + + +vuint8mf4_t test___riscv_vsbc_vxm_u8mf4(vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf4(op1,op2,borrowin,vl); +} + + +vuint8mf2_t test___riscv_vsbc_vxm_u8mf2(vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf2(op1,op2,borrowin,vl); +} + + +vuint8m1_t test___riscv_vsbc_vxm_u8m1(vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m1(op1,op2,borrowin,vl); +} + + +vuint8m2_t test___riscv_vsbc_vxm_u8m2(vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m2(op1,op2,borrowin,vl); +} + + +vuint8m4_t test___riscv_vsbc_vxm_u8m4(vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m4(op1,op2,borrowin,vl); +} + + +vuint8m8_t test___riscv_vsbc_vxm_u8m8(vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m8(op1,op2,borrowin,vl); +} + + +vuint16mf4_t test___riscv_vsbc_vxm_u16mf4(vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf4(op1,op2,borrowin,vl); +} + + +vuint16mf2_t test___riscv_vsbc_vxm_u16mf2(vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf2(op1,op2,borrowin,vl); +} + + +vuint16m1_t test___riscv_vsbc_vxm_u16m1(vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m1(op1,op2,borrowin,vl); +} + + +vuint16m2_t test___riscv_vsbc_vxm_u16m2(vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m2(op1,op2,borrowin,vl); +} + + +vuint16m4_t test___riscv_vsbc_vxm_u16m4(vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m4(op1,op2,borrowin,vl); +} + + +vuint16m8_t test___riscv_vsbc_vxm_u16m8(vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m8(op1,op2,borrowin,vl); +} + + +vuint32mf2_t test___riscv_vsbc_vxm_u32mf2(vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32mf2(op1,op2,borrowin,vl); +} + + +vuint32m1_t test___riscv_vsbc_vxm_u32m1(vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m1(op1,op2,borrowin,vl); +} + + +vuint32m2_t test___riscv_vsbc_vxm_u32m2(vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m2(op1,op2,borrowin,vl); +} + + +vuint32m4_t test___riscv_vsbc_vxm_u32m4(vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m4(op1,op2,borrowin,vl); +} + + +vuint32m8_t test___riscv_vsbc_vxm_u32m8(vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m8(op1,op2,borrowin,vl); +} + + +vuint64m1_t test___riscv_vsbc_vxm_u64m1(vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m1(op1,op2,borrowin,vl); +} + + +vuint64m2_t test___riscv_vsbc_vxm_u64m2(vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m2(op1,op2,borrowin,vl); +} + + +vuint64m4_t test___riscv_vsbc_vxm_u64m4(vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m4(op1,op2,borrowin,vl); +} + + +vuint64m8_t test___riscv_vsbc_vxm_u64m8(vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m8(op1,op2,borrowin,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-2.c new file mode 100644 index 00000000000..1a2cdac3de4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-2.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc_vxm_i8mf8(vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf8(op1,op2,borrowin,31); +} + + +vint8mf4_t test___riscv_vsbc_vxm_i8mf4(vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf4(op1,op2,borrowin,31); +} + + +vint8mf2_t test___riscv_vsbc_vxm_i8mf2(vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf2(op1,op2,borrowin,31); +} + + +vint8m1_t test___riscv_vsbc_vxm_i8m1(vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m1(op1,op2,borrowin,31); +} + + +vint8m2_t test___riscv_vsbc_vxm_i8m2(vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m2(op1,op2,borrowin,31); +} + + +vint8m4_t test___riscv_vsbc_vxm_i8m4(vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m4(op1,op2,borrowin,31); +} + + +vint8m8_t test___riscv_vsbc_vxm_i8m8(vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m8(op1,op2,borrowin,31); +} + + +vint16mf4_t test___riscv_vsbc_vxm_i16mf4(vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf4(op1,op2,borrowin,31); +} + + +vint16mf2_t test___riscv_vsbc_vxm_i16mf2(vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf2(op1,op2,borrowin,31); +} + + +vint16m1_t test___riscv_vsbc_vxm_i16m1(vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m1(op1,op2,borrowin,31); +} + + +vint16m2_t test___riscv_vsbc_vxm_i16m2(vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m2(op1,op2,borrowin,31); +} + + +vint16m4_t test___riscv_vsbc_vxm_i16m4(vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m4(op1,op2,borrowin,31); +} + + +vint16m8_t test___riscv_vsbc_vxm_i16m8(vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m8(op1,op2,borrowin,31); +} + + +vint32mf2_t test___riscv_vsbc_vxm_i32mf2(vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32mf2(op1,op2,borrowin,31); +} + + +vint32m1_t test___riscv_vsbc_vxm_i32m1(vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m1(op1,op2,borrowin,31); +} + + +vint32m2_t test___riscv_vsbc_vxm_i32m2(vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m2(op1,op2,borrowin,31); +} + + +vint32m4_t test___riscv_vsbc_vxm_i32m4(vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m4(op1,op2,borrowin,31); +} + + +vint32m8_t test___riscv_vsbc_vxm_i32m8(vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m8(op1,op2,borrowin,31); +} + + +vint64m1_t test___riscv_vsbc_vxm_i64m1(vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m1(op1,op2,borrowin,31); +} + + +vint64m2_t test___riscv_vsbc_vxm_i64m2(vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m2(op1,op2,borrowin,31); +} + + +vint64m4_t test___riscv_vsbc_vxm_i64m4(vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m4(op1,op2,borrowin,31); +} + + +vint64m8_t test___riscv_vsbc_vxm_i64m8(vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m8(op1,op2,borrowin,31); +} + + +vuint8mf8_t test___riscv_vsbc_vxm_u8mf8(vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf8(op1,op2,borrowin,31); +} + + +vuint8mf4_t test___riscv_vsbc_vxm_u8mf4(vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf4(op1,op2,borrowin,31); +} + + +vuint8mf2_t test___riscv_vsbc_vxm_u8mf2(vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf2(op1,op2,borrowin,31); +} + + +vuint8m1_t test___riscv_vsbc_vxm_u8m1(vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m1(op1,op2,borrowin,31); +} + + +vuint8m2_t test___riscv_vsbc_vxm_u8m2(vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m2(op1,op2,borrowin,31); +} + + +vuint8m4_t test___riscv_vsbc_vxm_u8m4(vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m4(op1,op2,borrowin,31); +} + + +vuint8m8_t test___riscv_vsbc_vxm_u8m8(vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m8(op1,op2,borrowin,31); +} + + +vuint16mf4_t test___riscv_vsbc_vxm_u16mf4(vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf4(op1,op2,borrowin,31); +} + + +vuint16mf2_t test___riscv_vsbc_vxm_u16mf2(vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf2(op1,op2,borrowin,31); +} + + +vuint16m1_t test___riscv_vsbc_vxm_u16m1(vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m1(op1,op2,borrowin,31); +} + + +vuint16m2_t test___riscv_vsbc_vxm_u16m2(vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m2(op1,op2,borrowin,31); +} + + +vuint16m4_t test___riscv_vsbc_vxm_u16m4(vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m4(op1,op2,borrowin,31); +} + + +vuint16m8_t test___riscv_vsbc_vxm_u16m8(vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m8(op1,op2,borrowin,31); +} + + +vuint32mf2_t test___riscv_vsbc_vxm_u32mf2(vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32mf2(op1,op2,borrowin,31); +} + + +vuint32m1_t test___riscv_vsbc_vxm_u32m1(vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m1(op1,op2,borrowin,31); +} + + +vuint32m2_t test___riscv_vsbc_vxm_u32m2(vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m2(op1,op2,borrowin,31); +} + + +vuint32m4_t test___riscv_vsbc_vxm_u32m4(vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m4(op1,op2,borrowin,31); +} + + +vuint32m8_t test___riscv_vsbc_vxm_u32m8(vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m8(op1,op2,borrowin,31); +} + + +vuint64m1_t test___riscv_vsbc_vxm_u64m1(vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m1(op1,op2,borrowin,31); +} + + +vuint64m2_t test___riscv_vsbc_vxm_u64m2(vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m2(op1,op2,borrowin,31); +} + + +vuint64m4_t test___riscv_vsbc_vxm_u64m4(vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m4(op1,op2,borrowin,31); +} + + +vuint64m8_t test___riscv_vsbc_vxm_u64m8(vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m8(op1,op2,borrowin,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-3.c new file mode 100644 index 00000000000..113857fe89e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-3.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc_vxm_i8mf8(vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf8(op1,op2,borrowin,32); +} + + +vint8mf4_t test___riscv_vsbc_vxm_i8mf4(vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf4(op1,op2,borrowin,32); +} + + +vint8mf2_t test___riscv_vsbc_vxm_i8mf2(vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf2(op1,op2,borrowin,32); +} + + +vint8m1_t test___riscv_vsbc_vxm_i8m1(vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m1(op1,op2,borrowin,32); +} + + +vint8m2_t test___riscv_vsbc_vxm_i8m2(vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m2(op1,op2,borrowin,32); +} + + +vint8m4_t test___riscv_vsbc_vxm_i8m4(vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m4(op1,op2,borrowin,32); +} + + +vint8m8_t test___riscv_vsbc_vxm_i8m8(vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m8(op1,op2,borrowin,32); +} + + +vint16mf4_t test___riscv_vsbc_vxm_i16mf4(vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf4(op1,op2,borrowin,32); +} + + +vint16mf2_t test___riscv_vsbc_vxm_i16mf2(vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf2(op1,op2,borrowin,32); +} + + +vint16m1_t test___riscv_vsbc_vxm_i16m1(vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m1(op1,op2,borrowin,32); +} + + +vint16m2_t test___riscv_vsbc_vxm_i16m2(vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m2(op1,op2,borrowin,32); +} + + +vint16m4_t test___riscv_vsbc_vxm_i16m4(vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m4(op1,op2,borrowin,32); +} + + +vint16m8_t test___riscv_vsbc_vxm_i16m8(vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m8(op1,op2,borrowin,32); +} + + +vint32mf2_t test___riscv_vsbc_vxm_i32mf2(vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32mf2(op1,op2,borrowin,32); +} + + +vint32m1_t test___riscv_vsbc_vxm_i32m1(vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m1(op1,op2,borrowin,32); +} + + +vint32m2_t test___riscv_vsbc_vxm_i32m2(vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m2(op1,op2,borrowin,32); +} + + +vint32m4_t test___riscv_vsbc_vxm_i32m4(vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m4(op1,op2,borrowin,32); +} + + +vint32m8_t test___riscv_vsbc_vxm_i32m8(vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m8(op1,op2,borrowin,32); +} + + +vint64m1_t test___riscv_vsbc_vxm_i64m1(vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m1(op1,op2,borrowin,32); +} + + +vint64m2_t test___riscv_vsbc_vxm_i64m2(vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m2(op1,op2,borrowin,32); +} + + +vint64m4_t test___riscv_vsbc_vxm_i64m4(vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m4(op1,op2,borrowin,32); +} + + +vint64m8_t test___riscv_vsbc_vxm_i64m8(vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m8(op1,op2,borrowin,32); +} + + +vuint8mf8_t test___riscv_vsbc_vxm_u8mf8(vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf8(op1,op2,borrowin,32); +} + + +vuint8mf4_t test___riscv_vsbc_vxm_u8mf4(vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf4(op1,op2,borrowin,32); +} + + +vuint8mf2_t test___riscv_vsbc_vxm_u8mf2(vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf2(op1,op2,borrowin,32); +} + + +vuint8m1_t test___riscv_vsbc_vxm_u8m1(vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m1(op1,op2,borrowin,32); +} + + +vuint8m2_t test___riscv_vsbc_vxm_u8m2(vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m2(op1,op2,borrowin,32); +} + + +vuint8m4_t test___riscv_vsbc_vxm_u8m4(vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m4(op1,op2,borrowin,32); +} + + +vuint8m8_t test___riscv_vsbc_vxm_u8m8(vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m8(op1,op2,borrowin,32); +} + + +vuint16mf4_t test___riscv_vsbc_vxm_u16mf4(vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf4(op1,op2,borrowin,32); +} + + +vuint16mf2_t test___riscv_vsbc_vxm_u16mf2(vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf2(op1,op2,borrowin,32); +} + + +vuint16m1_t test___riscv_vsbc_vxm_u16m1(vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m1(op1,op2,borrowin,32); +} + + +vuint16m2_t test___riscv_vsbc_vxm_u16m2(vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m2(op1,op2,borrowin,32); +} + + +vuint16m4_t test___riscv_vsbc_vxm_u16m4(vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m4(op1,op2,borrowin,32); +} + + +vuint16m8_t test___riscv_vsbc_vxm_u16m8(vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m8(op1,op2,borrowin,32); +} + + +vuint32mf2_t test___riscv_vsbc_vxm_u32mf2(vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32mf2(op1,op2,borrowin,32); +} + + +vuint32m1_t test___riscv_vsbc_vxm_u32m1(vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m1(op1,op2,borrowin,32); +} + + +vuint32m2_t test___riscv_vsbc_vxm_u32m2(vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m2(op1,op2,borrowin,32); +} + + +vuint32m4_t test___riscv_vsbc_vxm_u32m4(vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m4(op1,op2,borrowin,32); +} + + +vuint32m8_t test___riscv_vsbc_vxm_u32m8(vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m8(op1,op2,borrowin,32); +} + + +vuint64m1_t test___riscv_vsbc_vxm_u64m1(vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m1(op1,op2,borrowin,32); +} + + +vuint64m2_t test___riscv_vsbc_vxm_u64m2(vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m2(op1,op2,borrowin,32); +} + + +vuint64m4_t test___riscv_vsbc_vxm_u64m4(vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m4(op1,op2,borrowin,32); +} + + +vuint64m8_t test___riscv_vsbc_vxm_u64m8(vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m8(op1,op2,borrowin,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-1.c new file mode 100644 index 00000000000..7fab8c30cf1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc_vxm_i8mf8(vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf8(op1,op2,borrowin,vl); +} + + +vint8mf4_t test___riscv_vsbc_vxm_i8mf4(vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf4(op1,op2,borrowin,vl); +} + + +vint8mf2_t test___riscv_vsbc_vxm_i8mf2(vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf2(op1,op2,borrowin,vl); +} + + +vint8m1_t test___riscv_vsbc_vxm_i8m1(vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m1(op1,op2,borrowin,vl); +} + + +vint8m2_t test___riscv_vsbc_vxm_i8m2(vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m2(op1,op2,borrowin,vl); +} + + +vint8m4_t test___riscv_vsbc_vxm_i8m4(vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m4(op1,op2,borrowin,vl); +} + + +vint8m8_t test___riscv_vsbc_vxm_i8m8(vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m8(op1,op2,borrowin,vl); +} + + +vint16mf4_t test___riscv_vsbc_vxm_i16mf4(vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf4(op1,op2,borrowin,vl); +} + + +vint16mf2_t test___riscv_vsbc_vxm_i16mf2(vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf2(op1,op2,borrowin,vl); +} + + +vint16m1_t test___riscv_vsbc_vxm_i16m1(vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m1(op1,op2,borrowin,vl); +} + + +vint16m2_t test___riscv_vsbc_vxm_i16m2(vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m2(op1,op2,borrowin,vl); +} + + +vint16m4_t test___riscv_vsbc_vxm_i16m4(vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m4(op1,op2,borrowin,vl); +} + + +vint16m8_t test___riscv_vsbc_vxm_i16m8(vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m8(op1,op2,borrowin,vl); +} + + +vint32mf2_t test___riscv_vsbc_vxm_i32mf2(vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32mf2(op1,op2,borrowin,vl); +} + + +vint32m1_t test___riscv_vsbc_vxm_i32m1(vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m1(op1,op2,borrowin,vl); +} + + +vint32m2_t test___riscv_vsbc_vxm_i32m2(vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m2(op1,op2,borrowin,vl); +} + + +vint32m4_t test___riscv_vsbc_vxm_i32m4(vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m4(op1,op2,borrowin,vl); +} + + +vint32m8_t test___riscv_vsbc_vxm_i32m8(vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m8(op1,op2,borrowin,vl); +} + + +vint64m1_t test___riscv_vsbc_vxm_i64m1(vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m1(op1,op2,borrowin,vl); +} + + +vint64m2_t test___riscv_vsbc_vxm_i64m2(vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m2(op1,op2,borrowin,vl); +} + + +vint64m4_t test___riscv_vsbc_vxm_i64m4(vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m4(op1,op2,borrowin,vl); +} + + +vint64m8_t test___riscv_vsbc_vxm_i64m8(vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m8(op1,op2,borrowin,vl); +} + + +vuint8mf8_t test___riscv_vsbc_vxm_u8mf8(vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf8(op1,op2,borrowin,vl); +} + + +vuint8mf4_t test___riscv_vsbc_vxm_u8mf4(vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf4(op1,op2,borrowin,vl); +} + + +vuint8mf2_t test___riscv_vsbc_vxm_u8mf2(vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf2(op1,op2,borrowin,vl); +} + + +vuint8m1_t test___riscv_vsbc_vxm_u8m1(vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m1(op1,op2,borrowin,vl); +} + + +vuint8m2_t test___riscv_vsbc_vxm_u8m2(vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m2(op1,op2,borrowin,vl); +} + + +vuint8m4_t test___riscv_vsbc_vxm_u8m4(vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m4(op1,op2,borrowin,vl); +} + + +vuint8m8_t test___riscv_vsbc_vxm_u8m8(vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m8(op1,op2,borrowin,vl); +} + + +vuint16mf4_t test___riscv_vsbc_vxm_u16mf4(vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf4(op1,op2,borrowin,vl); +} + + +vuint16mf2_t test___riscv_vsbc_vxm_u16mf2(vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf2(op1,op2,borrowin,vl); +} + + +vuint16m1_t test___riscv_vsbc_vxm_u16m1(vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m1(op1,op2,borrowin,vl); +} + + +vuint16m2_t test___riscv_vsbc_vxm_u16m2(vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m2(op1,op2,borrowin,vl); +} + + +vuint16m4_t test___riscv_vsbc_vxm_u16m4(vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m4(op1,op2,borrowin,vl); +} + + +vuint16m8_t test___riscv_vsbc_vxm_u16m8(vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m8(op1,op2,borrowin,vl); +} + + +vuint32mf2_t test___riscv_vsbc_vxm_u32mf2(vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32mf2(op1,op2,borrowin,vl); +} + + +vuint32m1_t test___riscv_vsbc_vxm_u32m1(vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m1(op1,op2,borrowin,vl); +} + + +vuint32m2_t test___riscv_vsbc_vxm_u32m2(vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m2(op1,op2,borrowin,vl); +} + + +vuint32m4_t test___riscv_vsbc_vxm_u32m4(vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m4(op1,op2,borrowin,vl); +} + + +vuint32m8_t test___riscv_vsbc_vxm_u32m8(vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m8(op1,op2,borrowin,vl); +} + + +vuint64m1_t test___riscv_vsbc_vxm_u64m1(vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m1(op1,op2,borrowin,vl); +} + + +vuint64m2_t test___riscv_vsbc_vxm_u64m2(vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m2(op1,op2,borrowin,vl); +} + + +vuint64m4_t test___riscv_vsbc_vxm_u64m4(vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m4(op1,op2,borrowin,vl); +} + + +vuint64m8_t test___riscv_vsbc_vxm_u64m8(vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m8(op1,op2,borrowin,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-2.c new file mode 100644 index 00000000000..6603e2a1746 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc_vxm_i8mf8(vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf8(op1,op2,borrowin,31); +} + + +vint8mf4_t test___riscv_vsbc_vxm_i8mf4(vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf4(op1,op2,borrowin,31); +} + + +vint8mf2_t test___riscv_vsbc_vxm_i8mf2(vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf2(op1,op2,borrowin,31); +} + + +vint8m1_t test___riscv_vsbc_vxm_i8m1(vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m1(op1,op2,borrowin,31); +} + + +vint8m2_t test___riscv_vsbc_vxm_i8m2(vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m2(op1,op2,borrowin,31); +} + + +vint8m4_t test___riscv_vsbc_vxm_i8m4(vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m4(op1,op2,borrowin,31); +} + + +vint8m8_t test___riscv_vsbc_vxm_i8m8(vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m8(op1,op2,borrowin,31); +} + + +vint16mf4_t test___riscv_vsbc_vxm_i16mf4(vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf4(op1,op2,borrowin,31); +} + + +vint16mf2_t test___riscv_vsbc_vxm_i16mf2(vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf2(op1,op2,borrowin,31); +} + + +vint16m1_t test___riscv_vsbc_vxm_i16m1(vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m1(op1,op2,borrowin,31); +} + + +vint16m2_t test___riscv_vsbc_vxm_i16m2(vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m2(op1,op2,borrowin,31); +} + + +vint16m4_t test___riscv_vsbc_vxm_i16m4(vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m4(op1,op2,borrowin,31); +} + + +vint16m8_t test___riscv_vsbc_vxm_i16m8(vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m8(op1,op2,borrowin,31); +} + + +vint32mf2_t test___riscv_vsbc_vxm_i32mf2(vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32mf2(op1,op2,borrowin,31); +} + + +vint32m1_t test___riscv_vsbc_vxm_i32m1(vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m1(op1,op2,borrowin,31); +} + + +vint32m2_t test___riscv_vsbc_vxm_i32m2(vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m2(op1,op2,borrowin,31); +} + + +vint32m4_t test___riscv_vsbc_vxm_i32m4(vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m4(op1,op2,borrowin,31); +} + + +vint32m8_t test___riscv_vsbc_vxm_i32m8(vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m8(op1,op2,borrowin,31); +} + + +vint64m1_t test___riscv_vsbc_vxm_i64m1(vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m1(op1,op2,borrowin,31); +} + + +vint64m2_t test___riscv_vsbc_vxm_i64m2(vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m2(op1,op2,borrowin,31); +} + + +vint64m4_t test___riscv_vsbc_vxm_i64m4(vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m4(op1,op2,borrowin,31); +} + + +vint64m8_t test___riscv_vsbc_vxm_i64m8(vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m8(op1,op2,borrowin,31); +} + + +vuint8mf8_t test___riscv_vsbc_vxm_u8mf8(vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf8(op1,op2,borrowin,31); +} + + +vuint8mf4_t test___riscv_vsbc_vxm_u8mf4(vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf4(op1,op2,borrowin,31); +} + + +vuint8mf2_t test___riscv_vsbc_vxm_u8mf2(vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf2(op1,op2,borrowin,31); +} + + +vuint8m1_t test___riscv_vsbc_vxm_u8m1(vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m1(op1,op2,borrowin,31); +} + + +vuint8m2_t test___riscv_vsbc_vxm_u8m2(vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m2(op1,op2,borrowin,31); +} + + +vuint8m4_t test___riscv_vsbc_vxm_u8m4(vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m4(op1,op2,borrowin,31); +} + + +vuint8m8_t test___riscv_vsbc_vxm_u8m8(vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m8(op1,op2,borrowin,31); +} + + +vuint16mf4_t test___riscv_vsbc_vxm_u16mf4(vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf4(op1,op2,borrowin,31); +} + + +vuint16mf2_t test___riscv_vsbc_vxm_u16mf2(vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf2(op1,op2,borrowin,31); +} + + +vuint16m1_t test___riscv_vsbc_vxm_u16m1(vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m1(op1,op2,borrowin,31); +} + + +vuint16m2_t test___riscv_vsbc_vxm_u16m2(vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m2(op1,op2,borrowin,31); +} + + +vuint16m4_t test___riscv_vsbc_vxm_u16m4(vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m4(op1,op2,borrowin,31); +} + + +vuint16m8_t test___riscv_vsbc_vxm_u16m8(vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m8(op1,op2,borrowin,31); +} + + +vuint32mf2_t test___riscv_vsbc_vxm_u32mf2(vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32mf2(op1,op2,borrowin,31); +} + + +vuint32m1_t test___riscv_vsbc_vxm_u32m1(vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m1(op1,op2,borrowin,31); +} + + +vuint32m2_t test___riscv_vsbc_vxm_u32m2(vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m2(op1,op2,borrowin,31); +} + + +vuint32m4_t test___riscv_vsbc_vxm_u32m4(vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m4(op1,op2,borrowin,31); +} + + +vuint32m8_t test___riscv_vsbc_vxm_u32m8(vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m8(op1,op2,borrowin,31); +} + + +vuint64m1_t test___riscv_vsbc_vxm_u64m1(vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m1(op1,op2,borrowin,31); +} + + +vuint64m2_t test___riscv_vsbc_vxm_u64m2(vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m2(op1,op2,borrowin,31); +} + + +vuint64m4_t test___riscv_vsbc_vxm_u64m4(vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m4(op1,op2,borrowin,31); +} + + +vuint64m8_t test___riscv_vsbc_vxm_u64m8(vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m8(op1,op2,borrowin,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-3.c new file mode 100644 index 00000000000..4a1d42d71e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc_vxm_i8mf8(vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf8(op1,op2,borrowin,32); +} + + +vint8mf4_t test___riscv_vsbc_vxm_i8mf4(vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf4(op1,op2,borrowin,32); +} + + +vint8mf2_t test___riscv_vsbc_vxm_i8mf2(vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf2(op1,op2,borrowin,32); +} + + +vint8m1_t test___riscv_vsbc_vxm_i8m1(vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m1(op1,op2,borrowin,32); +} + + +vint8m2_t test___riscv_vsbc_vxm_i8m2(vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m2(op1,op2,borrowin,32); +} + + +vint8m4_t test___riscv_vsbc_vxm_i8m4(vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m4(op1,op2,borrowin,32); +} + + +vint8m8_t test___riscv_vsbc_vxm_i8m8(vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m8(op1,op2,borrowin,32); +} + + +vint16mf4_t test___riscv_vsbc_vxm_i16mf4(vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf4(op1,op2,borrowin,32); +} + + +vint16mf2_t test___riscv_vsbc_vxm_i16mf2(vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf2(op1,op2,borrowin,32); +} + + +vint16m1_t test___riscv_vsbc_vxm_i16m1(vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m1(op1,op2,borrowin,32); +} + + +vint16m2_t test___riscv_vsbc_vxm_i16m2(vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m2(op1,op2,borrowin,32); +} + + +vint16m4_t test___riscv_vsbc_vxm_i16m4(vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m4(op1,op2,borrowin,32); +} + + +vint16m8_t test___riscv_vsbc_vxm_i16m8(vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m8(op1,op2,borrowin,32); +} + + +vint32mf2_t test___riscv_vsbc_vxm_i32mf2(vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32mf2(op1,op2,borrowin,32); +} + + +vint32m1_t test___riscv_vsbc_vxm_i32m1(vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m1(op1,op2,borrowin,32); +} + + +vint32m2_t test___riscv_vsbc_vxm_i32m2(vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m2(op1,op2,borrowin,32); +} + + +vint32m4_t test___riscv_vsbc_vxm_i32m4(vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m4(op1,op2,borrowin,32); +} + + +vint32m8_t test___riscv_vsbc_vxm_i32m8(vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m8(op1,op2,borrowin,32); +} + + +vint64m1_t test___riscv_vsbc_vxm_i64m1(vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m1(op1,op2,borrowin,32); +} + + +vint64m2_t test___riscv_vsbc_vxm_i64m2(vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m2(op1,op2,borrowin,32); +} + + +vint64m4_t test___riscv_vsbc_vxm_i64m4(vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m4(op1,op2,borrowin,32); +} + + +vint64m8_t test___riscv_vsbc_vxm_i64m8(vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m8(op1,op2,borrowin,32); +} + + +vuint8mf8_t test___riscv_vsbc_vxm_u8mf8(vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf8(op1,op2,borrowin,32); +} + + +vuint8mf4_t test___riscv_vsbc_vxm_u8mf4(vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf4(op1,op2,borrowin,32); +} + + +vuint8mf2_t test___riscv_vsbc_vxm_u8mf2(vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf2(op1,op2,borrowin,32); +} + + +vuint8m1_t test___riscv_vsbc_vxm_u8m1(vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m1(op1,op2,borrowin,32); +} + + +vuint8m2_t test___riscv_vsbc_vxm_u8m2(vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m2(op1,op2,borrowin,32); +} + + +vuint8m4_t test___riscv_vsbc_vxm_u8m4(vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m4(op1,op2,borrowin,32); +} + + +vuint8m8_t test___riscv_vsbc_vxm_u8m8(vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m8(op1,op2,borrowin,32); +} + + +vuint16mf4_t test___riscv_vsbc_vxm_u16mf4(vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf4(op1,op2,borrowin,32); +} + + +vuint16mf2_t test___riscv_vsbc_vxm_u16mf2(vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf2(op1,op2,borrowin,32); +} + + +vuint16m1_t test___riscv_vsbc_vxm_u16m1(vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m1(op1,op2,borrowin,32); +} + + +vuint16m2_t test___riscv_vsbc_vxm_u16m2(vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m2(op1,op2,borrowin,32); +} + + +vuint16m4_t test___riscv_vsbc_vxm_u16m4(vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m4(op1,op2,borrowin,32); +} + + +vuint16m8_t test___riscv_vsbc_vxm_u16m8(vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m8(op1,op2,borrowin,32); +} + + +vuint32mf2_t test___riscv_vsbc_vxm_u32mf2(vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32mf2(op1,op2,borrowin,32); +} + + +vuint32m1_t test___riscv_vsbc_vxm_u32m1(vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m1(op1,op2,borrowin,32); +} + + +vuint32m2_t test___riscv_vsbc_vxm_u32m2(vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m2(op1,op2,borrowin,32); +} + + +vuint32m4_t test___riscv_vsbc_vxm_u32m4(vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m4(op1,op2,borrowin,32); +} + + +vuint32m8_t test___riscv_vsbc_vxm_u32m8(vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m8(op1,op2,borrowin,32); +} + + +vuint64m1_t test___riscv_vsbc_vxm_u64m1(vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m1(op1,op2,borrowin,32); +} + + +vuint64m2_t test___riscv_vsbc_vxm_u64m2(vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m2(op1,op2,borrowin,32); +} + + +vuint64m4_t test___riscv_vsbc_vxm_u64m4(vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m4(op1,op2,borrowin,32); +} + + +vuint64m8_t test___riscv_vsbc_vxm_u64m8(vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m8(op1,op2,borrowin,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.c new file mode 100644 index 00000000000..11adfa8a7ea --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc_vxm_i8mf8_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8mf4_t test___riscv_vsbc_vxm_i8mf4_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8mf2_t test___riscv_vsbc_vxm_i8mf2_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m1_t test___riscv_vsbc_vxm_i8m1_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m2_t test___riscv_vsbc_vxm_i8m2_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m4_t test___riscv_vsbc_vxm_i8m4_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m8_t test___riscv_vsbc_vxm_i8m8_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16mf4_t test___riscv_vsbc_vxm_i16mf4_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16mf2_t test___riscv_vsbc_vxm_i16mf2_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m1_t test___riscv_vsbc_vxm_i16m1_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m2_t test___riscv_vsbc_vxm_i16m2_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m4_t test___riscv_vsbc_vxm_i16m4_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m8_t test___riscv_vsbc_vxm_i16m8_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32mf2_t test___riscv_vsbc_vxm_i32mf2_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32mf2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m1_t test___riscv_vsbc_vxm_i32m1_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m2_t test___riscv_vsbc_vxm_i32m2_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m4_t test___riscv_vsbc_vxm_i32m4_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m8_t test___riscv_vsbc_vxm_i32m8_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m1_t test___riscv_vsbc_vxm_i64m1_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m2_t test___riscv_vsbc_vxm_i64m2_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m4_t test___riscv_vsbc_vxm_i64m4_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m8_t test___riscv_vsbc_vxm_i64m8_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8mf8_t test___riscv_vsbc_vxm_u8mf8_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8mf4_t test___riscv_vsbc_vxm_u8mf4_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8mf2_t test___riscv_vsbc_vxm_u8mf2_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m1_t test___riscv_vsbc_vxm_u8m1_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m2_t test___riscv_vsbc_vxm_u8m2_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m4_t test___riscv_vsbc_vxm_u8m4_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m8_t test___riscv_vsbc_vxm_u8m8_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16mf4_t test___riscv_vsbc_vxm_u16mf4_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16mf2_t test___riscv_vsbc_vxm_u16mf2_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m1_t test___riscv_vsbc_vxm_u16m1_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m2_t test___riscv_vsbc_vxm_u16m2_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m4_t test___riscv_vsbc_vxm_u16m4_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m8_t test___riscv_vsbc_vxm_u16m8_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32mf2_t test___riscv_vsbc_vxm_u32mf2_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32mf2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m1_t test___riscv_vsbc_vxm_u32m1_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m2_t test___riscv_vsbc_vxm_u32m2_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m4_t test___riscv_vsbc_vxm_u32m4_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m8_t test___riscv_vsbc_vxm_u32m8_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m1_t test___riscv_vsbc_vxm_u64m1_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m2_t test___riscv_vsbc_vxm_u64m2_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m4_t test___riscv_vsbc_vxm_u64m4_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m8_t test___riscv_vsbc_vxm_u64m8_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.c new file mode 100644 index 00000000000..72ce96b7600 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc_vxm_i8mf8_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8mf4_t test___riscv_vsbc_vxm_i8mf4_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8mf2_t test___riscv_vsbc_vxm_i8mf2_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m1_t test___riscv_vsbc_vxm_i8m1_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m2_t test___riscv_vsbc_vxm_i8m2_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m4_t test___riscv_vsbc_vxm_i8m4_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m8_t test___riscv_vsbc_vxm_i8m8_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16mf4_t test___riscv_vsbc_vxm_i16mf4_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16mf2_t test___riscv_vsbc_vxm_i16mf2_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m1_t test___riscv_vsbc_vxm_i16m1_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m2_t test___riscv_vsbc_vxm_i16m2_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m4_t test___riscv_vsbc_vxm_i16m4_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m8_t test___riscv_vsbc_vxm_i16m8_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32mf2_t test___riscv_vsbc_vxm_i32mf2_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32mf2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m1_t test___riscv_vsbc_vxm_i32m1_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m2_t test___riscv_vsbc_vxm_i32m2_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m4_t test___riscv_vsbc_vxm_i32m4_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m8_t test___riscv_vsbc_vxm_i32m8_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m1_t test___riscv_vsbc_vxm_i64m1_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m2_t test___riscv_vsbc_vxm_i64m2_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m4_t test___riscv_vsbc_vxm_i64m4_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m8_t test___riscv_vsbc_vxm_i64m8_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8mf8_t test___riscv_vsbc_vxm_u8mf8_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8mf4_t test___riscv_vsbc_vxm_u8mf4_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8mf2_t test___riscv_vsbc_vxm_u8mf2_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m1_t test___riscv_vsbc_vxm_u8m1_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m2_t test___riscv_vsbc_vxm_u8m2_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m4_t test___riscv_vsbc_vxm_u8m4_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m8_t test___riscv_vsbc_vxm_u8m8_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16mf4_t test___riscv_vsbc_vxm_u16mf4_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16mf2_t test___riscv_vsbc_vxm_u16mf2_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m1_t test___riscv_vsbc_vxm_u16m1_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m2_t test___riscv_vsbc_vxm_u16m2_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m4_t test___riscv_vsbc_vxm_u16m4_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m8_t test___riscv_vsbc_vxm_u16m8_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32mf2_t test___riscv_vsbc_vxm_u32mf2_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32mf2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m1_t test___riscv_vsbc_vxm_u32m1_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m2_t test___riscv_vsbc_vxm_u32m2_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m4_t test___riscv_vsbc_vxm_u32m4_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m8_t test___riscv_vsbc_vxm_u32m8_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m1_t test___riscv_vsbc_vxm_u64m1_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m2_t test___riscv_vsbc_vxm_u64m2_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m4_t test___riscv_vsbc_vxm_u64m4_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m8_t test___riscv_vsbc_vxm_u64m8_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m8_tu(maskedoff,op1,op2,borrowin,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.c new file mode 100644 index 00000000000..501101a7c2d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc_vxm_i8mf8_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8mf4_t test___riscv_vsbc_vxm_i8mf4_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8mf2_t test___riscv_vsbc_vxm_i8mf2_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m1_t test___riscv_vsbc_vxm_i8m1_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m2_t test___riscv_vsbc_vxm_i8m2_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m4_t test___riscv_vsbc_vxm_i8m4_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m8_t test___riscv_vsbc_vxm_i8m8_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16mf4_t test___riscv_vsbc_vxm_i16mf4_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16mf2_t test___riscv_vsbc_vxm_i16mf2_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m1_t test___riscv_vsbc_vxm_i16m1_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m2_t test___riscv_vsbc_vxm_i16m2_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m4_t test___riscv_vsbc_vxm_i16m4_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m8_t test___riscv_vsbc_vxm_i16m8_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32mf2_t test___riscv_vsbc_vxm_i32mf2_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32mf2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m1_t test___riscv_vsbc_vxm_i32m1_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m2_t test___riscv_vsbc_vxm_i32m2_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m4_t test___riscv_vsbc_vxm_i32m4_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m8_t test___riscv_vsbc_vxm_i32m8_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m1_t test___riscv_vsbc_vxm_i64m1_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m2_t test___riscv_vsbc_vxm_i64m2_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m4_t test___riscv_vsbc_vxm_i64m4_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m8_t test___riscv_vsbc_vxm_i64m8_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8mf8_t test___riscv_vsbc_vxm_u8mf8_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8mf4_t test___riscv_vsbc_vxm_u8mf4_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8mf2_t test___riscv_vsbc_vxm_u8mf2_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m1_t test___riscv_vsbc_vxm_u8m1_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m2_t test___riscv_vsbc_vxm_u8m2_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m4_t test___riscv_vsbc_vxm_u8m4_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m8_t test___riscv_vsbc_vxm_u8m8_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16mf4_t test___riscv_vsbc_vxm_u16mf4_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16mf2_t test___riscv_vsbc_vxm_u16mf2_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m1_t test___riscv_vsbc_vxm_u16m1_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m2_t test___riscv_vsbc_vxm_u16m2_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m4_t test___riscv_vsbc_vxm_u16m4_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m8_t test___riscv_vsbc_vxm_u16m8_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32mf2_t test___riscv_vsbc_vxm_u32mf2_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32mf2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m1_t test___riscv_vsbc_vxm_u32m1_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m2_t test___riscv_vsbc_vxm_u32m2_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m4_t test___riscv_vsbc_vxm_u32m4_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m8_t test___riscv_vsbc_vxm_u32m8_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m1_t test___riscv_vsbc_vxm_u64m1_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m2_t test___riscv_vsbc_vxm_u64m2_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m4_t test___riscv_vsbc_vxm_u64m4_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m8_t test___riscv_vsbc_vxm_u64m8_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m8_tu(maskedoff,op1,op2,borrowin,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.c new file mode 100644 index 00000000000..5822314efa3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc_vxm_i8mf8_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8mf4_t test___riscv_vsbc_vxm_i8mf4_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8mf2_t test___riscv_vsbc_vxm_i8mf2_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m1_t test___riscv_vsbc_vxm_i8m1_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m2_t test___riscv_vsbc_vxm_i8m2_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m4_t test___riscv_vsbc_vxm_i8m4_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m8_t test___riscv_vsbc_vxm_i8m8_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16mf4_t test___riscv_vsbc_vxm_i16mf4_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16mf2_t test___riscv_vsbc_vxm_i16mf2_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m1_t test___riscv_vsbc_vxm_i16m1_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m2_t test___riscv_vsbc_vxm_i16m2_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m4_t test___riscv_vsbc_vxm_i16m4_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m8_t test___riscv_vsbc_vxm_i16m8_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32mf2_t test___riscv_vsbc_vxm_i32mf2_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32mf2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m1_t test___riscv_vsbc_vxm_i32m1_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m2_t test___riscv_vsbc_vxm_i32m2_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m4_t test___riscv_vsbc_vxm_i32m4_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m8_t test___riscv_vsbc_vxm_i32m8_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m1_t test___riscv_vsbc_vxm_i64m1_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m2_t test___riscv_vsbc_vxm_i64m2_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m4_t test___riscv_vsbc_vxm_i64m4_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m8_t test___riscv_vsbc_vxm_i64m8_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8mf8_t test___riscv_vsbc_vxm_u8mf8_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8mf4_t test___riscv_vsbc_vxm_u8mf4_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8mf2_t test___riscv_vsbc_vxm_u8mf2_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m1_t test___riscv_vsbc_vxm_u8m1_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m2_t test___riscv_vsbc_vxm_u8m2_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m4_t test___riscv_vsbc_vxm_u8m4_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m8_t test___riscv_vsbc_vxm_u8m8_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16mf4_t test___riscv_vsbc_vxm_u16mf4_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16mf2_t test___riscv_vsbc_vxm_u16mf2_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m1_t test___riscv_vsbc_vxm_u16m1_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m2_t test___riscv_vsbc_vxm_u16m2_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m4_t test___riscv_vsbc_vxm_u16m4_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m8_t test___riscv_vsbc_vxm_u16m8_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32mf2_t test___riscv_vsbc_vxm_u32mf2_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32mf2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m1_t test___riscv_vsbc_vxm_u32m1_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m2_t test___riscv_vsbc_vxm_u32m2_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m4_t test___riscv_vsbc_vxm_u32m4_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m8_t test___riscv_vsbc_vxm_u32m8_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m1_t test___riscv_vsbc_vxm_u64m1_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m1_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m2_t test___riscv_vsbc_vxm_u64m2_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m2_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m4_t test___riscv_vsbc_vxm_u64m4_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m4_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m8_t test___riscv_vsbc_vxm_u64m8_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m8_tu(maskedoff,op1,op2,borrowin,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.c new file mode 100644 index 00000000000..a8894fd484d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc_vxm_i8mf8_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8mf4_t test___riscv_vsbc_vxm_i8mf4_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8mf2_t test___riscv_vsbc_vxm_i8mf2_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m1_t test___riscv_vsbc_vxm_i8m1_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m2_t test___riscv_vsbc_vxm_i8m2_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m4_t test___riscv_vsbc_vxm_i8m4_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m8_t test___riscv_vsbc_vxm_i8m8_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16mf4_t test___riscv_vsbc_vxm_i16mf4_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16mf2_t test___riscv_vsbc_vxm_i16mf2_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m1_t test___riscv_vsbc_vxm_i16m1_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m2_t test___riscv_vsbc_vxm_i16m2_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m4_t test___riscv_vsbc_vxm_i16m4_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m8_t test___riscv_vsbc_vxm_i16m8_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32mf2_t test___riscv_vsbc_vxm_i32mf2_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32mf2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m1_t test___riscv_vsbc_vxm_i32m1_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m2_t test___riscv_vsbc_vxm_i32m2_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m4_t test___riscv_vsbc_vxm_i32m4_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m8_t test___riscv_vsbc_vxm_i32m8_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m1_t test___riscv_vsbc_vxm_i64m1_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m2_t test___riscv_vsbc_vxm_i64m2_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m4_t test___riscv_vsbc_vxm_i64m4_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m8_t test___riscv_vsbc_vxm_i64m8_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8mf8_t test___riscv_vsbc_vxm_u8mf8_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8mf4_t test___riscv_vsbc_vxm_u8mf4_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8mf2_t test___riscv_vsbc_vxm_u8mf2_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m1_t test___riscv_vsbc_vxm_u8m1_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m2_t test___riscv_vsbc_vxm_u8m2_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m4_t test___riscv_vsbc_vxm_u8m4_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m8_t test___riscv_vsbc_vxm_u8m8_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16mf4_t test___riscv_vsbc_vxm_u16mf4_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16mf2_t test___riscv_vsbc_vxm_u16mf2_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m1_t test___riscv_vsbc_vxm_u16m1_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m2_t test___riscv_vsbc_vxm_u16m2_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m4_t test___riscv_vsbc_vxm_u16m4_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m8_t test___riscv_vsbc_vxm_u16m8_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32mf2_t test___riscv_vsbc_vxm_u32mf2_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32mf2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m1_t test___riscv_vsbc_vxm_u32m1_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m2_t test___riscv_vsbc_vxm_u32m2_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m4_t test___riscv_vsbc_vxm_u32m4_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m8_t test___riscv_vsbc_vxm_u32m8_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m8_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m1_t test___riscv_vsbc_vxm_u64m1_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m1_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m2_t test___riscv_vsbc_vxm_u64m2_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m2_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m4_t test___riscv_vsbc_vxm_u64m4_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m4_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m8_t test___riscv_vsbc_vxm_u64m8_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m8_tu(maskedoff,op1,op2,borrowin,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.c new file mode 100644 index 00000000000..4e17ef285a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc_vxm_i8mf8_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8mf4_t test___riscv_vsbc_vxm_i8mf4_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8mf2_t test___riscv_vsbc_vxm_i8mf2_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8mf2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m1_t test___riscv_vsbc_vxm_i8m1_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m2_t test___riscv_vsbc_vxm_i8m2_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m4_t test___riscv_vsbc_vxm_i8m4_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m8_t test___riscv_vsbc_vxm_i8m8_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i8m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16mf4_t test___riscv_vsbc_vxm_i16mf4_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16mf2_t test___riscv_vsbc_vxm_i16mf2_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16mf2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m1_t test___riscv_vsbc_vxm_i16m1_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m2_t test___riscv_vsbc_vxm_i16m2_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m4_t test___riscv_vsbc_vxm_i16m4_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m8_t test___riscv_vsbc_vxm_i16m8_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i16m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32mf2_t test___riscv_vsbc_vxm_i32mf2_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32mf2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m1_t test___riscv_vsbc_vxm_i32m1_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m2_t test___riscv_vsbc_vxm_i32m2_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m4_t test___riscv_vsbc_vxm_i32m4_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m8_t test___riscv_vsbc_vxm_i32m8_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i32m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m1_t test___riscv_vsbc_vxm_i64m1_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m2_t test___riscv_vsbc_vxm_i64m2_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m4_t test___riscv_vsbc_vxm_i64m4_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m8_t test___riscv_vsbc_vxm_i64m8_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_i64m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8mf8_t test___riscv_vsbc_vxm_u8mf8_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8mf4_t test___riscv_vsbc_vxm_u8mf4_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8mf2_t test___riscv_vsbc_vxm_u8mf2_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8mf2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m1_t test___riscv_vsbc_vxm_u8m1_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m2_t test___riscv_vsbc_vxm_u8m2_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m4_t test___riscv_vsbc_vxm_u8m4_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m8_t test___riscv_vsbc_vxm_u8m8_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u8m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16mf4_t test___riscv_vsbc_vxm_u16mf4_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16mf2_t test___riscv_vsbc_vxm_u16mf2_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16mf2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m1_t test___riscv_vsbc_vxm_u16m1_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m2_t test___riscv_vsbc_vxm_u16m2_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m4_t test___riscv_vsbc_vxm_u16m4_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m8_t test___riscv_vsbc_vxm_u16m8_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u16m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32mf2_t test___riscv_vsbc_vxm_u32mf2_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32mf2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m1_t test___riscv_vsbc_vxm_u32m1_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m2_t test___riscv_vsbc_vxm_u32m2_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m4_t test___riscv_vsbc_vxm_u32m4_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m8_t test___riscv_vsbc_vxm_u32m8_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u32m8_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m1_t test___riscv_vsbc_vxm_u64m1_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m1_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m2_t test___riscv_vsbc_vxm_u64m2_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m2_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m4_t test___riscv_vsbc_vxm_u64m4_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m4_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m8_t test___riscv_vsbc_vxm_u64m8_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_vxm_u64m8_tu(maskedoff,op1,op2,borrowin,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */