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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id h3-20020a17090791c300b0078dbd939dacsi13763955ejz.545.2023.02.06.23.50.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 23:50:01 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 59329385843D for ; Tue, 7 Feb 2023 07:49:55 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) by sourceware.org (Postfix) with ESMTPS id 4F6623858D1E for ; Tue, 7 Feb 2023 07:49:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4F6623858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp86t1675756158tpv96zb8 Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 07 Feb 2023 15:49:17 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: LrCnY+iDm+NUO5Ik1ilKaN3GpM6XUtKb6jgA1TBend0rJoxuEpwWToiGxAKTi rgD5u276SlhDLQG51gZAWHIFPdOJ5201nHSZgV1GX9oniouorWiAOvr2a94ZMCJtR6ongZy Q0EXfdShcLeaJ7ZULS8Vi85YaNy6FJdMAPWlsMaj5DB+JdV4Gjf7HVNesTIQJiwoJ1oDZUN KpUm/5oEATqaOgOWXW4Kumt8ff5H8CCkhwssEuQzdd6jKyCHZbKsE5xkn7CtfwTZObgBHVQ /KLEYWHzUkjh+hNGm8BOseEKvgjIXmE7GI5NS6A8M/QDJj7WC7J4RVghaBBcIcbQdv/O0mH IB6YNQ7/CYQ/nlD9gQ4vSZO2zilVmVI62tJW8LVkTVi7cSjN2J+tSm0qtmKNV0n+eqEDnT6 CpNwutk+vMz2LhBrLO6WRA== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: allow vx instruction use "zero" as scalar register. Date: Tue, 7 Feb 2023 15:49:16 +0800 Message-Id: <20230207074916.116648-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757157734266425376?= X-GMAIL-MSGID: =?utf-8?q?1757157734266425376?= From: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/vector.md: use "zero" reg. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/binop_vx_constraint-121.c: New test. li a5,0 vdiv.vx v0,v1,a5 =======> vdiv.vx v0,v1,zero --- gcc/config/riscv/vector.md | 57 +++++++++++-------- .../riscv/rvv/base/binop_vx_constraint-121.c | 55 ++++++++++++++++++ 2 files changed, 88 insertions(+), 24 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-121.c diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index ec177fa7efb..d526c1fc5f1 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1247,11 +1247,11 @@ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_commutative_binop:VI_QHS (vec_duplicate:VI_QHS - (match_operand: 4 "register_operand" " r, r")) + (match_operand: 4 "reg_or_0_operand" " rJ, rJ")) (match_operand:VI_QHS 3 "register_operand" " vr, vr")) (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))] "TARGET_VECTOR" - "v.vx\t%0,%3,%4%p1" + "v.vx\t%0,%3,%z4%p1" [(set_attr "type" "") (set_attr "mode" "")]) @@ -1269,10 +1269,10 @@ (any_non_commutative_binop:VI_QHS (match_operand:VI_QHS 3 "register_operand" " vr, vr") (vec_duplicate:VI_QHS - (match_operand: 4 "register_operand" " r, r"))) + (match_operand: 4 "reg_or_0_operand" " rJ, rJ"))) (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))] "TARGET_VECTOR" - "v.vx\t%0,%3,%4%p1" + "v.vx\t%0,%3,%z4%p1" [(set_attr "type" "") (set_attr "mode" "")]) @@ -1324,8 +1324,11 @@ rtx v = gen_reg_rtx (mode); if (riscv_vector::simm32_p (operands[4])) - operands[4] = gen_rtx_SIGN_EXTEND (mode, - force_reg (Pmode, operands[4])); + { + if (!rtx_equal_p (operands[4], const0_rtx)) + operands[4] = force_reg (Pmode, operands[4]); + operands[4] = gen_rtx_SIGN_EXTEND (mode, operands[4]); + } else { if (CONST_INT_P (operands[4])) @@ -1356,11 +1359,11 @@ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_commutative_binop:VI_D (vec_duplicate:VI_D - (match_operand: 4 "register_operand" " r, r")) + (match_operand: 4 "reg_or_0_operand" " rJ, rJ")) (match_operand:VI_D 3 "register_operand" " vr, vr")) (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))] "TARGET_VECTOR" - "v.vx\t%0,%3,%4%p1" + "v.vx\t%0,%3,%z4%p1" [(set_attr "type" "") (set_attr "mode" "")]) @@ -1378,11 +1381,11 @@ (any_commutative_binop:VI_D (vec_duplicate:VI_D (sign_extend: - (match_operand: 4 "register_operand" " r, r"))) + (match_operand: 4 "reg_or_0_operand" " rJ, rJ"))) (match_operand:VI_D 3 "register_operand" " vr, vr")) (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))] "TARGET_VECTOR" - "v.vx\t%0,%3,%4%p1" + "v.vx\t%0,%3,%z4%p1" [(set_attr "type" "") (set_attr "mode" "")]) @@ -1411,8 +1414,11 @@ rtx v = gen_reg_rtx (mode); if (riscv_vector::simm32_p (operands[4])) - operands[4] = gen_rtx_SIGN_EXTEND (mode, - force_reg (Pmode, operands[4])); + { + if (!rtx_equal_p (operands[4], const0_rtx)) + operands[4] = force_reg (Pmode, operands[4]); + operands[4] = gen_rtx_SIGN_EXTEND (mode, operands[4]); + } else { if (CONST_INT_P (operands[4])) @@ -1444,10 +1450,10 @@ (any_non_commutative_binop:VI_D (match_operand:VI_D 3 "register_operand" " vr, vr") (vec_duplicate:VI_D - (match_operand: 4 "register_operand" " r, r"))) + (match_operand: 4 "reg_or_0_operand" " rJ, rJ"))) (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))] "TARGET_VECTOR" - "v.vx\t%0,%3,%4%p1" + "v.vx\t%0,%3,%z4%p1" [(set_attr "type" "") (set_attr "mode" "")]) @@ -1466,10 +1472,10 @@ (match_operand:VI_D 3 "register_operand" " vr, vr") (vec_duplicate:VI_D (sign_extend: - (match_operand: 4 "register_operand" " r, r")))) + (match_operand: 4 "reg_or_0_operand" " rJ, rJ")))) (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))] "TARGET_VECTOR" - "v.vx\t%0,%3,%4%p1" + "v.vx\t%0,%3,%z4%p1" [(set_attr "type" "") (set_attr "mode" "")]) @@ -1836,11 +1842,11 @@ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VI_QHS [(vec_duplicate:VI_QHS - (match_operand: 4 "register_operand" " r, r")) + (match_operand: 4 "reg_or_0_operand" " rJ, rJ")) (match_operand:VI_QHS 3 "register_operand" " vr, vr")] VMULH) (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))] "TARGET_VECTOR" - "vmulh.vx\t%0,%3,%4%p1" + "vmulh.vx\t%0,%3,%z4%p1" [(set_attr "type" "vimul") (set_attr "mode" "")]) @@ -1867,8 +1873,11 @@ rtx v = gen_reg_rtx (mode); if (riscv_vector::simm32_p (operands[4])) - operands[4] = gen_rtx_SIGN_EXTEND (mode, - force_reg (Pmode, operands[4])); + { + if (!rtx_equal_p (operands[4], const0_rtx)) + operands[4] = force_reg (Pmode, operands[4]); + operands[4] = gen_rtx_SIGN_EXTEND (mode, operands[4]); + } else { if (CONST_INT_P (operands[4])) @@ -1899,11 +1908,11 @@ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VFULLI_D [(vec_duplicate:VFULLI_D - (match_operand: 4 "register_operand" " r, r")) + (match_operand: 4 "register_operand" " rJ, rJ")) (match_operand:VFULLI_D 3 "register_operand" " vr, vr")] VMULH) (match_operand:VFULLI_D 2 "vector_merge_operand" "0vu,0vu")))] "TARGET_VECTOR" - "vmulh.vx\t%0,%3,%4%p1" + "vmulh.vx\t%0,%3,%z4%p1" [(set_attr "type" "vimul") (set_attr "mode" "")]) @@ -1921,11 +1930,11 @@ (unspec:VFULLI_D [(vec_duplicate:VFULLI_D (sign_extend: - (match_operand: 4 "register_operand" " r, r"))) + (match_operand: 4 "reg_or_0_operand" " rJ, rJ"))) (match_operand:VFULLI_D 3 "register_operand" " vr, vr")] VMULH) (match_operand:VFULLI_D 2 "vector_merge_operand" "0vu,0vu")))] "TARGET_VECTOR" - "vmulh.vx\t%0,%3,%4%p1" + "vmulh.vx\t%0,%3,%z4%p1" [(set_attr "type" "vimul") (set_attr "mode" "")]) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-121.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-121.c new file mode 100644 index 00000000000..4d2de91bc14 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-121.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f1 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vmulh_vx_i32m1 (v2, 0, 4); + __riscv_vse32_v_i32m1 (out, v3, 4); +} + +void f2 (void * in, void *out, int32_t x) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in, 4); + vint64m1_t v3 = __riscv_vmulh_vx_i64m1 (v2, 0, 4); + __riscv_vse64_v_i64m1 (out, v3, 4); +} + +void f3 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vdiv_vx_i32m1 (v2, 0, 4); + __riscv_vse32_v_i32m1 (out, v3, 4); +} + +void f4 (void * in, void *out, int32_t x) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in, 4); + vint64m1_t v3 = __riscv_vdiv_vx_i64m1 (v2, 0, 4); + __riscv_vse64_v_i64m1 (out, v3, 4); +} + +void f5 (void * in, void *out, int32_t x) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vrem_vx_i32m1 (v2, 0, 4); + __riscv_vse32_v_i32m1 (out, v3, 4); +} + +void f6 (void * in, void *out, int32_t x) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in, 4); + vint64m1_t v3 = __riscv_vrem_vx_i64m1 (v2, 0, 4); + __riscv_vse64_v_i64m1 (out, v3, 4); +} + +/* { dg-final { scan-assembler-times {vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,zero} 2 } } */ +/* { dg-final { scan-assembler-times {vdiv\.vx\s+v[0-9]+,\s*v[0-9]+,zero} 2 } } */ +/* { dg-final { scan-assembler-times {vrem\.vx\s+v[0-9]+,\s*v[0-9]+,zero} 2 } } */