diff mbox series

RISC-V: Add vwmulsu.v C++ API tests

Message ID 20230207064648.45113-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Add vwmulsu.v C++ API tests |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai Feb. 7, 2023, 6:46 a.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vwmulsu_vv-1.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vv-2.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vv-3.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vv_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vv_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vv_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vv_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vv_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vv_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vv_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vv_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vv_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vv_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vv_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vv_tumu-3.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vx-1.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vx-2.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vx-3.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vx_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vx_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vx_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vx_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vx_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vx_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vx_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vx_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vx_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vx_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vx_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmulsu_vx_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vwmulsu_vv-1.C  | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwmulsu_vv-2.C  | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwmulsu_vv-3.C  | 216 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vv_mu-1.C          | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vv_mu-2.C          | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vv_mu-3.C          | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vv_tu-1.C          | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vv_tu-2.C          | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vv_tu-3.C          | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vv_tum-1.C         | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vv_tum-2.C         | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vv_tum-3.C         | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vv_tumu-1.C        | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vv_tumu-2.C        | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vv_tumu-3.C        | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwmulsu_vx-1.C  | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwmulsu_vx-2.C  | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwmulsu_vx-3.C  | 216 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vx_mu-1.C          | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vx_mu-2.C          | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vx_mu-3.C          | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vx_tu-1.C          | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vx_tu-2.C          | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vx_tu-3.C          | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vx_tum-1.C         | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vx_tum-2.C         | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vx_tum-3.C         | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vx_tumu-1.C        | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vx_tumu-2.C        | 111 +++++++++
 .../riscv/rvv/base/vwmulsu_vx_tumu-3.C        | 111 +++++++++
 30 files changed, 3960 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-3.C
diff mbox series

Patch

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-1.C
new file mode 100644
index 00000000000..3fc5597750a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-1.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu(vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu(vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu(vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu(vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu(vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu(vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu(vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu(vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu(vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu(vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu(vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu(vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu(vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu(vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu(vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vwmulsu(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu(vbool8_t mask,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu(vbool4_t mask,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu(vbool2_t mask,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu(vbool16_t mask,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu(vbool8_t mask,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu(vbool4_t mask,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu(vbool32_t mask,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu(vbool16_t mask,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu(vbool8_t mask,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-2.C
new file mode 100644
index 00000000000..0bfa1ed0d7a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-2.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu(vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu(vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu(vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu(vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu(vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu(vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu(vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu(vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu(vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu(vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu(vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu(vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu(vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu(vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu(vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vwmulsu(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu(vbool8_t mask,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu(vbool4_t mask,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu(vbool2_t mask,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu(vbool16_t mask,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu(vbool8_t mask,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu(vbool4_t mask,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu(vbool32_t mask,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu(vbool16_t mask,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu(vbool8_t mask,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-3.C
new file mode 100644
index 00000000000..e5651eb1158
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-3.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu(vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu(vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu(vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu(vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu(vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu(vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu(vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu(vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu(vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu(vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu(vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu(vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu(vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu(vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu(vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vwmulsu(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu(vbool8_t mask,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu(vbool4_t mask,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu(vbool2_t mask,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu(vbool16_t mask,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu(vbool8_t mask,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu(vbool4_t mask,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu(vbool32_t mask,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu(vbool16_t mask,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu(vbool8_t mask,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-1.C
new file mode 100644
index 00000000000..4c0c93dedd9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-2.C
new file mode 100644
index 00000000000..3728d13f59f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-3.C
new file mode 100644
index 00000000000..efc18cdf0a0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-1.C
new file mode 100644
index 00000000000..7133c9efe97
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_tu(vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_tu(vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_tu(vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_tu(vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_tu(vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_tu(vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_tu(vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_tu(vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_tu(vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_tu(vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_tu(vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_tu(vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_tu(vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_tu(vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_tu(vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-2.C
new file mode 100644
index 00000000000..70254246d06
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_tu(vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_tu(vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_tu(vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_tu(vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_tu(vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_tu(vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_tu(vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_tu(vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_tu(vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_tu(vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_tu(vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_tu(vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_tu(vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_tu(vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_tu(vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-3.C
new file mode 100644
index 00000000000..1c5fd72ad92
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_tu(vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_tu(vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_tu(vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_tu(vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_tu(vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_tu(vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_tu(vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_tu(vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_tu(vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_tu(vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_tu(vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_tu(vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_tu(vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_tu(vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_tu(vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-1.C
new file mode 100644
index 00000000000..3cf1259177f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-2.C
new file mode 100644
index 00000000000..9d506dd33f2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-3.C
new file mode 100644
index 00000000000..d17ddcb612a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-1.C
new file mode 100644
index 00000000000..24cb1dfe22a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-2.C
new file mode 100644
index 00000000000..af588dfb6bf
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-3.C
new file mode 100644
index 00000000000..e8878d41891
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-1.C
new file mode 100644
index 00000000000..d45e1752626
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-1.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu(vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu(vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu(vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu(vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu(vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu(vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu(vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu(vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu(vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu(vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu(vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu(vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu(vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu(vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu(vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vwmulsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-2.C
new file mode 100644
index 00000000000..af185c29fb2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-2.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu(vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu(vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu(vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu(vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu(vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu(vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu(vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu(vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu(vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu(vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu(vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu(vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu(vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu(vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu(vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vwmulsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-3.C
new file mode 100644
index 00000000000..245fab88866
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-3.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu(vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu(vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu(vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu(vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu(vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu(vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu(vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu(vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu(vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu(vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu(vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu(vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu(vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu(vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu(vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vwmulsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-1.C
new file mode 100644
index 00000000000..8293e972175
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-2.C
new file mode 100644
index 00000000000..42989e0186c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-3.C
new file mode 100644
index 00000000000..b098a587138
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-1.C
new file mode 100644
index 00000000000..71933e4e41d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_tu(vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_tu(vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_tu(vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_tu(vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_tu(vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_tu(vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_tu(vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_tu(vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_tu(vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_tu(vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_tu(vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_tu(vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_tu(vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_tu(vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_tu(vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-2.C
new file mode 100644
index 00000000000..78f2a3441b3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_tu(vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_tu(vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_tu(vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_tu(vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_tu(vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_tu(vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_tu(vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_tu(vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_tu(vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_tu(vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_tu(vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_tu(vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_tu(vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_tu(vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_tu(vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-3.C
new file mode 100644
index 00000000000..60f1f0589e9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_tu(vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_tu(vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_tu(vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_tu(vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_tu(vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_tu(vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_tu(vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_tu(vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_tu(vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_tu(vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_tu(vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_tu(vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_tu(vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_tu(vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_tu(vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-1.C
new file mode 100644
index 00000000000..78a817d3f7d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-2.C
new file mode 100644
index 00000000000..ac739573593
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-3.C
new file mode 100644
index 00000000000..9d1ce8327ad
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-1.C
new file mode 100644
index 00000000000..c5880edf5e3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-2.C
new file mode 100644
index 00000000000..fe37f4bab12
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-3.C
new file mode 100644
index 00000000000..d760b8e8b0b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */