From patchwork Tue Feb 7 06:33:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 53716 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2682647wrn; Mon, 6 Feb 2023 22:34:26 -0800 (PST) X-Google-Smtp-Source: AK7set8gvE1+fMUQ05uPjbcwF8T4GeN0efzqpFuEi32fojser0M9hYsAC1KmdlXvXtGwzx1tmw7U X-Received: by 2002:a17:906:6a27:b0:88d:ba89:1833 with SMTP id qw39-20020a1709066a2700b0088dba891833mr22502469ejc.4.1675751666352; Mon, 06 Feb 2023 22:34:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675751666; cv=none; d=google.com; s=arc-20160816; b=lVL6bagKHimfhDMQsA3GbWWv0QwfQDhoNnGGp/pr1hsKXzEdf052y1fsSURr3RyIXA Wn0Wr6E0e1jsu0+cpzYbGJRnxyD3zDh6fWHfhHtz1l/IliDz9DnGip/RcDoN8BwYBS15 RqLFqixsIbMqlY61e0swfODH9zNRIssVHo6/qifiop4X2pKmqN4swbKx00Nul9TnS9ba vvt6cC+TiyXtoJ/WqsRORNNRjirhVgQk5lCFtgV6jPrDROE0Ivx2fhY+utojG43/Znvq hOVDJOTjPdRwVIXjUiFSrwh9NPyjFX41ywUt1kfuM4YVyc2CvsJaRp3RBoz/FD7NEyxF qmQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:feedback-id :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:dmarc-filter:delivered-to; bh=BEWPnf86p0ZqbkhTHgTY2L2v1+eEtYzfRInp/e7TRAo=; b=OuXtfk1CfrR1JvcATQCqqHL2ovQ5c+Z+UqbIZpyHktTDvWet5pHHe9jQla1edsluDK IT6hUjdIN+3v9I0iv79auKKLFVrSIPASp13nzFmqxyDGLZ3W+pr3/aaOv9FB+zGbAtRD kAR9jFSd0tkBMJ4tMWQghCjJn9BRdCGLGlajC2bgYsHqfrveWBZXD/07uqUTLXmfA/0j AAwbiMCuUuS3dNLGiu/u5sp2hAHpdu2mLveppKtSSzzIlC3Ho14NG5uW2BHFsWbCg3v1 lx3lFW4KZv04Lt1Lna7lJw+aEDNvk4quDaWeGEU3CQM4BrivXjbC5W994EDav885keJV ls0g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id 13-20020a170906024d00b008aa27cc624csi593400ejl.669.2023.02.06.22.34.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 22:34:26 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CE60F385842A for ; Tue, 7 Feb 2023 06:34:20 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) by sourceware.org (Postfix) with ESMTPS id 4E1C23858D1E for ; Tue, 7 Feb 2023 06:33:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4E1C23858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp89t1675751610tf62j6xq Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 07 Feb 2023 14:33:29 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: jUz4x+AhIZmkAb2ASdNjy0wf1zRH5KhnCVWO3Aty/xw03hzKSINuM75SRlhIS O3u7plnidQ1k3YTT8/owRVORyQnmDA3CtvY1Yv11XtdYlnNmX/E3aDnd+aSpeTxTfebnaiN KPU5ThOIODGFMD99st64zKcsMlEsUkmkyuAGam2cN2HNl2Tu4CyVZFZ9S1By6SWROzyYBf6 BPB2T6ROjkkmqL70vtEAaHYtB6XvN8tHeKgOSSUlqk8QhE7nn6JpoFwkYW7Ssv12BW4esaf 4G3NsVT5lK6ivhSdQ9UhR0QEKIqVgvfLxSO7S0s5L63t4/o306oKwTAmALjQKnd14TLLkhI ZTlocN5z4n+CK6V3DwtqJSMipQCOUTZkxT2lsj2RcgLduD3docW2JMf/ARpCYboqSxgbnmA X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vwcvt C API test Date: Tue, 7 Feb 2023 14:33:28 +0800 Message-Id: <20230207063328.39329-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757152979262375650?= X-GMAIL-MSGID: =?utf-8?q?1757152979262375650?= From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vwcvt_x-1.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x-2.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x-3.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_m-1.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_m-2.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_m-3.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_tumu-3.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x-1.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x-2.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x-3.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_m-1.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_m-2.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_m-3.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_tumu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vwcvt_x-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_m-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_m-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_m-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_mu-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_mu-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_mu-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tu-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tu-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tu-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tum-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tum-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tum-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwcvt_x_tumu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwcvt_x_tumu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwcvt_x_tumu-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_m-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_m-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_m-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_mu-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_mu-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_mu-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_tu-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_tu-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_tu-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwcvtu_x_tum-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwcvtu_x_tum-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwcvtu_x_tum-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwcvtu_x_tumu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwcvtu_x_tumu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwcvtu_x_tumu-3.c | 111 ++++++++++++++++++ 36 files changed, 3996 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-1.c new file mode 100644 index 00000000000..43b38ac1563 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4(vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4(src,vl); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2(vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2(src,vl); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1(vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1(src,vl); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2(vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2(src,vl); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4(vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4(src,vl); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8(vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8(src,vl); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2(vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2(src,vl); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1(vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1(src,vl); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2(vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2(src,vl); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4(vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4(src,vl); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8(vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8(src,vl); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1(vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1(src,vl); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2(vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2(src,vl); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4(vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4(src,vl); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8(vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8(src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-2.c new file mode 100644 index 00000000000..6b03c04bc1e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4(vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4(src,31); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2(vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2(src,31); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1(vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1(src,31); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2(vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2(src,31); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4(vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4(src,31); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8(vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8(src,31); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2(vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2(src,31); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1(vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1(src,31); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2(vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2(src,31); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4(vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4(src,31); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8(vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8(src,31); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1(vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1(src,31); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2(vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2(src,31); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4(vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4(src,31); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8(vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8(src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-3.c new file mode 100644 index 00000000000..15eae6769d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4(vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4(src,32); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2(vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2(src,32); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1(vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1(src,32); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2(vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2(src,32); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4(vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4(src,32); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8(vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8(src,32); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2(vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2(src,32); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1(vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1(src,32); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2(vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2(src,32); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4(vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4(src,32); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8(vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8(src,32); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1(vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1(src,32); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2(vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2(src,32); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4(vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4(src,32); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8(vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8(src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-1.c new file mode 100644 index 00000000000..4809bd72265 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_m(vbool64_t mask,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_m(mask,src,vl); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_m(vbool32_t mask,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_m(mask,src,vl); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_m(vbool16_t mask,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_m(mask,src,vl); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_m(vbool8_t mask,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_m(mask,src,vl); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_m(vbool4_t mask,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_m(mask,src,vl); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_m(vbool2_t mask,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_m(mask,src,vl); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_m(vbool64_t mask,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_m(mask,src,vl); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_m(vbool32_t mask,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_m(mask,src,vl); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_m(vbool16_t mask,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_m(mask,src,vl); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_m(vbool8_t mask,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_m(mask,src,vl); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_m(vbool4_t mask,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_m(mask,src,vl); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_m(vbool64_t mask,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_m(mask,src,vl); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_m(vbool32_t mask,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_m(mask,src,vl); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_m(vbool16_t mask,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_m(mask,src,vl); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_m(vbool8_t mask,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_m(mask,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-2.c new file mode 100644 index 00000000000..ac6f904a02e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_m(vbool64_t mask,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_m(mask,src,31); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_m(vbool32_t mask,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_m(mask,src,31); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_m(vbool16_t mask,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_m(mask,src,31); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_m(vbool8_t mask,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_m(mask,src,31); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_m(vbool4_t mask,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_m(mask,src,31); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_m(vbool2_t mask,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_m(mask,src,31); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_m(vbool64_t mask,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_m(mask,src,31); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_m(vbool32_t mask,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_m(mask,src,31); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_m(vbool16_t mask,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_m(mask,src,31); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_m(vbool8_t mask,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_m(mask,src,31); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_m(vbool4_t mask,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_m(mask,src,31); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_m(vbool64_t mask,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_m(mask,src,31); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_m(vbool32_t mask,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_m(mask,src,31); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_m(vbool16_t mask,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_m(mask,src,31); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_m(vbool8_t mask,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_m(mask,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-3.c new file mode 100644 index 00000000000..cbbbb258283 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_m(vbool64_t mask,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_m(mask,src,32); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_m(vbool32_t mask,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_m(mask,src,32); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_m(vbool16_t mask,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_m(mask,src,32); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_m(vbool8_t mask,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_m(mask,src,32); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_m(vbool4_t mask,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_m(mask,src,32); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_m(vbool2_t mask,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_m(mask,src,32); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_m(vbool64_t mask,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_m(mask,src,32); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_m(vbool32_t mask,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_m(mask,src,32); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_m(vbool16_t mask,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_m(mask,src,32); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_m(vbool8_t mask,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_m(mask,src,32); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_m(vbool4_t mask,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_m(mask,src,32); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_m(vbool64_t mask,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_m(mask,src,32); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_m(vbool32_t mask,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_m(mask,src,32); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_m(vbool16_t mask,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_m(mask,src,32); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_m(vbool8_t mask,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_m(mask,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-1.c new file mode 100644 index 00000000000..2f635736b28 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_mu(mask,merge,src,vl); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_mu(mask,merge,src,vl); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_mu(mask,merge,src,vl); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_mu(mask,merge,src,vl); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_mu(mask,merge,src,vl); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_mu(mask,merge,src,vl); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_mu(mask,merge,src,vl); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_mu(mask,merge,src,vl); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_mu(mask,merge,src,vl); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_mu(mask,merge,src,vl); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_mu(mask,merge,src,vl); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_mu(mask,merge,src,vl); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_mu(mask,merge,src,vl); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_mu(mask,merge,src,vl); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_mu(mask,merge,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-2.c new file mode 100644 index 00000000000..27a834cde4b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_mu(mask,merge,src,31); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_mu(mask,merge,src,31); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_mu(mask,merge,src,31); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_mu(mask,merge,src,31); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_mu(mask,merge,src,31); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_mu(mask,merge,src,31); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_mu(mask,merge,src,31); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_mu(mask,merge,src,31); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_mu(mask,merge,src,31); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_mu(mask,merge,src,31); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_mu(mask,merge,src,31); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_mu(mask,merge,src,31); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_mu(mask,merge,src,31); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_mu(mask,merge,src,31); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_mu(mask,merge,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-3.c new file mode 100644 index 00000000000..a323f50af96 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_mu(mask,merge,src,32); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_mu(mask,merge,src,32); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_mu(mask,merge,src,32); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_mu(mask,merge,src,32); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_mu(mask,merge,src,32); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_mu(mask,merge,src,32); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_mu(mask,merge,src,32); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_mu(mask,merge,src,32); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_mu(mask,merge,src,32); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_mu(mask,merge,src,32); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_mu(mask,merge,src,32); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_mu(mask,merge,src,32); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_mu(mask,merge,src,32); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_mu(mask,merge,src,32); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_mu(mask,merge,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-1.c new file mode 100644 index 00000000000..9547f9206d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_tu(vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_tu(merge,src,vl); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_tu(vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_tu(merge,src,vl); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_tu(vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_tu(merge,src,vl); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_tu(vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_tu(merge,src,vl); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_tu(vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_tu(merge,src,vl); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_tu(vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_tu(merge,src,vl); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_tu(vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_tu(merge,src,vl); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_tu(vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_tu(merge,src,vl); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_tu(vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_tu(merge,src,vl); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_tu(vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_tu(merge,src,vl); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_tu(vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_tu(merge,src,vl); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_tu(vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_tu(merge,src,vl); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_tu(vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_tu(merge,src,vl); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_tu(vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_tu(merge,src,vl); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_tu(vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_tu(merge,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-2.c new file mode 100644 index 00000000000..f0fcdfab0c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_tu(vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_tu(merge,src,31); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_tu(vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_tu(merge,src,31); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_tu(vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_tu(merge,src,31); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_tu(vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_tu(merge,src,31); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_tu(vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_tu(merge,src,31); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_tu(vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_tu(merge,src,31); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_tu(vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_tu(merge,src,31); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_tu(vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_tu(merge,src,31); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_tu(vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_tu(merge,src,31); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_tu(vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_tu(merge,src,31); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_tu(vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_tu(merge,src,31); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_tu(vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_tu(merge,src,31); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_tu(vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_tu(merge,src,31); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_tu(vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_tu(merge,src,31); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_tu(vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_tu(merge,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-3.c new file mode 100644 index 00000000000..f279382b3d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_tu(vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_tu(merge,src,32); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_tu(vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_tu(merge,src,32); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_tu(vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_tu(merge,src,32); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_tu(vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_tu(merge,src,32); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_tu(vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_tu(merge,src,32); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_tu(vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_tu(merge,src,32); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_tu(vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_tu(merge,src,32); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_tu(vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_tu(merge,src,32); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_tu(vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_tu(merge,src,32); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_tu(vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_tu(merge,src,32); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_tu(vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_tu(merge,src,32); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_tu(vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_tu(merge,src,32); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_tu(vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_tu(merge,src,32); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_tu(vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_tu(merge,src,32); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_tu(vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_tu(merge,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-1.c new file mode 100644 index 00000000000..573a1f1c416 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_tum(mask,merge,src,vl); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_tum(mask,merge,src,vl); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_tum(mask,merge,src,vl); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_tum(mask,merge,src,vl); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_tum(mask,merge,src,vl); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_tum(mask,merge,src,vl); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_tum(mask,merge,src,vl); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_tum(mask,merge,src,vl); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_tum(mask,merge,src,vl); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_tum(mask,merge,src,vl); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_tum(mask,merge,src,vl); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_tum(mask,merge,src,vl); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_tum(mask,merge,src,vl); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_tum(mask,merge,src,vl); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_tum(mask,merge,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-2.c new file mode 100644 index 00000000000..c18da782ff3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_tum(mask,merge,src,31); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_tum(mask,merge,src,31); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_tum(mask,merge,src,31); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_tum(mask,merge,src,31); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_tum(mask,merge,src,31); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_tum(mask,merge,src,31); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_tum(mask,merge,src,31); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_tum(mask,merge,src,31); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_tum(mask,merge,src,31); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_tum(mask,merge,src,31); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_tum(mask,merge,src,31); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_tum(mask,merge,src,31); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_tum(mask,merge,src,31); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_tum(mask,merge,src,31); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_tum(mask,merge,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-3.c new file mode 100644 index 00000000000..5ac16b4c213 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_tum(mask,merge,src,32); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_tum(mask,merge,src,32); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_tum(mask,merge,src,32); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_tum(mask,merge,src,32); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_tum(mask,merge,src,32); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_tum(mask,merge,src,32); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_tum(mask,merge,src,32); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_tum(mask,merge,src,32); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_tum(mask,merge,src,32); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_tum(mask,merge,src,32); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_tum(mask,merge,src,32); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_tum(mask,merge,src,32); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_tum(mask,merge,src,32); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_tum(mask,merge,src,32); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_tum(mask,merge,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-1.c new file mode 100644 index 00000000000..4fe5a55f5d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_tumu(mask,merge,src,vl); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_tumu(mask,merge,src,vl); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_tumu(mask,merge,src,vl); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_tumu(mask,merge,src,vl); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_tumu(mask,merge,src,vl); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_tumu(mask,merge,src,vl); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_tumu(mask,merge,src,vl); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_tumu(mask,merge,src,vl); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_tumu(mask,merge,src,vl); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_tumu(mask,merge,src,vl); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_tumu(mask,merge,src,vl); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_tumu(mask,merge,src,vl); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_tumu(mask,merge,src,vl); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_tumu(mask,merge,src,vl); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_tumu(mask,merge,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-2.c new file mode 100644 index 00000000000..ae292da32df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_tumu(mask,merge,src,31); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_tumu(mask,merge,src,31); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_tumu(mask,merge,src,31); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_tumu(mask,merge,src,31); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_tumu(mask,merge,src,31); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_tumu(mask,merge,src,31); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_tumu(mask,merge,src,31); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_tumu(mask,merge,src,31); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_tumu(mask,merge,src,31); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_tumu(mask,merge,src,31); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_tumu(mask,merge,src,31); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_tumu(mask,merge,src,31); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_tumu(mask,merge,src,31); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_tumu(mask,merge,src,31); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_tumu(mask,merge,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-3.c new file mode 100644 index 00000000000..4e26fa30f53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_tumu(mask,merge,src,32); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_tumu(mask,merge,src,32); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_tumu(mask,merge,src,32); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_tumu(mask,merge,src,32); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_tumu(mask,merge,src,32); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_tumu(mask,merge,src,32); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_tumu(mask,merge,src,32); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_tumu(mask,merge,src,32); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_tumu(mask,merge,src,32); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_tumu(mask,merge,src,32); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_tumu(mask,merge,src,32); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_tumu(mask,merge,src,32); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_tumu(mask,merge,src,32); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_tumu(mask,merge,src,32); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_tumu(mask,merge,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-1.c new file mode 100644 index 00000000000..614b2f6cc81 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4(vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4(src,vl); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2(vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2(src,vl); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1(vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1(src,vl); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2(vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2(src,vl); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4(vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4(src,vl); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8(vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8(src,vl); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2(vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2(src,vl); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1(vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1(src,vl); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2(vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2(src,vl); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4(vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4(src,vl); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8(vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8(src,vl); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1(vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1(src,vl); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2(vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2(src,vl); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4(vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4(src,vl); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8(vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8(src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-2.c new file mode 100644 index 00000000000..0f331b1ed98 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4(vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4(src,31); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2(vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2(src,31); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1(vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1(src,31); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2(vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2(src,31); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4(vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4(src,31); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8(vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8(src,31); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2(vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2(src,31); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1(vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1(src,31); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2(vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2(src,31); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4(vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4(src,31); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8(vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8(src,31); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1(vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1(src,31); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2(vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2(src,31); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4(vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4(src,31); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8(vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8(src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-3.c new file mode 100644 index 00000000000..00d6f3cd2df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4(vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4(src,32); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2(vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2(src,32); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1(vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1(src,32); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2(vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2(src,32); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4(vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4(src,32); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8(vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8(src,32); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2(vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2(src,32); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1(vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1(src,32); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2(vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2(src,32); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4(vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4(src,32); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8(vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8(src,32); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1(vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1(src,32); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2(vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2(src,32); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4(vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4(src,32); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8(vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8(src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-1.c new file mode 100644 index 00000000000..a328f719658 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_m(vbool64_t mask,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_m(mask,src,vl); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_m(vbool32_t mask,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_m(mask,src,vl); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_m(vbool16_t mask,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_m(mask,src,vl); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_m(vbool8_t mask,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_m(mask,src,vl); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_m(vbool4_t mask,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_m(mask,src,vl); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_m(vbool2_t mask,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_m(mask,src,vl); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_m(vbool64_t mask,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_m(mask,src,vl); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_m(vbool32_t mask,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_m(mask,src,vl); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_m(vbool16_t mask,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_m(mask,src,vl); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_m(vbool8_t mask,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_m(mask,src,vl); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_m(vbool4_t mask,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_m(mask,src,vl); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_m(vbool64_t mask,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_m(mask,src,vl); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_m(vbool32_t mask,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_m(mask,src,vl); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_m(vbool16_t mask,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_m(mask,src,vl); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_m(vbool8_t mask,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_m(mask,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-2.c new file mode 100644 index 00000000000..87e26214809 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_m(vbool64_t mask,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_m(mask,src,31); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_m(vbool32_t mask,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_m(mask,src,31); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_m(vbool16_t mask,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_m(mask,src,31); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_m(vbool8_t mask,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_m(mask,src,31); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_m(vbool4_t mask,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_m(mask,src,31); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_m(vbool2_t mask,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_m(mask,src,31); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_m(vbool64_t mask,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_m(mask,src,31); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_m(vbool32_t mask,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_m(mask,src,31); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_m(vbool16_t mask,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_m(mask,src,31); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_m(vbool8_t mask,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_m(mask,src,31); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_m(vbool4_t mask,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_m(mask,src,31); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_m(vbool64_t mask,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_m(mask,src,31); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_m(vbool32_t mask,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_m(mask,src,31); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_m(vbool16_t mask,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_m(mask,src,31); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_m(vbool8_t mask,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_m(mask,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-3.c new file mode 100644 index 00000000000..49d5713fe1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_m(vbool64_t mask,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_m(mask,src,32); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_m(vbool32_t mask,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_m(mask,src,32); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_m(vbool16_t mask,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_m(mask,src,32); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_m(vbool8_t mask,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_m(mask,src,32); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_m(vbool4_t mask,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_m(mask,src,32); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_m(vbool2_t mask,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_m(mask,src,32); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_m(vbool64_t mask,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_m(mask,src,32); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_m(vbool32_t mask,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_m(mask,src,32); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_m(vbool16_t mask,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_m(mask,src,32); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_m(vbool8_t mask,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_m(mask,src,32); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_m(vbool4_t mask,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_m(mask,src,32); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_m(vbool64_t mask,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_m(mask,src,32); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_m(vbool32_t mask,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_m(mask,src,32); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_m(vbool16_t mask,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_m(mask,src,32); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_m(vbool8_t mask,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_m(mask,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-1.c new file mode 100644 index 00000000000..96c14911e7c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_mu(mask,merge,src,vl); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_mu(mask,merge,src,vl); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_mu(mask,merge,src,vl); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_mu(mask,merge,src,vl); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_mu(mask,merge,src,vl); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_mu(mask,merge,src,vl); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_mu(mask,merge,src,vl); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_mu(mask,merge,src,vl); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_mu(mask,merge,src,vl); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_mu(mask,merge,src,vl); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_mu(mask,merge,src,vl); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_mu(mask,merge,src,vl); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_mu(mask,merge,src,vl); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_mu(mask,merge,src,vl); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_mu(mask,merge,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-2.c new file mode 100644 index 00000000000..7ce833acebe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_mu(mask,merge,src,31); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_mu(mask,merge,src,31); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_mu(mask,merge,src,31); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_mu(mask,merge,src,31); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_mu(mask,merge,src,31); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_mu(mask,merge,src,31); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_mu(mask,merge,src,31); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_mu(mask,merge,src,31); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_mu(mask,merge,src,31); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_mu(mask,merge,src,31); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_mu(mask,merge,src,31); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_mu(mask,merge,src,31); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_mu(mask,merge,src,31); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_mu(mask,merge,src,31); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_mu(mask,merge,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-3.c new file mode 100644 index 00000000000..6bc2904cae9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_mu(mask,merge,src,32); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_mu(mask,merge,src,32); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_mu(mask,merge,src,32); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_mu(mask,merge,src,32); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_mu(mask,merge,src,32); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_mu(mask,merge,src,32); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_mu(mask,merge,src,32); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_mu(mask,merge,src,32); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_mu(mask,merge,src,32); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_mu(mask,merge,src,32); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_mu(mask,merge,src,32); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_mu(mask,merge,src,32); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_mu(mask,merge,src,32); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_mu(mask,merge,src,32); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_mu(mask,merge,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-1.c new file mode 100644 index 00000000000..481384ea6cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_tu(merge,src,vl); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_tu(merge,src,vl); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_tu(vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_tu(merge,src,vl); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_tu(vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_tu(merge,src,vl); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_tu(vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_tu(merge,src,vl); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_tu(vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_tu(merge,src,vl); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_tu(merge,src,vl); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_tu(vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_tu(merge,src,vl); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_tu(vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_tu(merge,src,vl); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_tu(vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_tu(merge,src,vl); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_tu(vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_tu(merge,src,vl); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_tu(vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_tu(merge,src,vl); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_tu(vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_tu(merge,src,vl); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_tu(vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_tu(merge,src,vl); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_tu(vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_tu(merge,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-2.c new file mode 100644 index 00000000000..decca0134b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_tu(merge,src,31); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_tu(merge,src,31); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_tu(vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_tu(merge,src,31); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_tu(vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_tu(merge,src,31); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_tu(vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_tu(merge,src,31); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_tu(vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_tu(merge,src,31); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_tu(merge,src,31); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_tu(vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_tu(merge,src,31); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_tu(vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_tu(merge,src,31); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_tu(vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_tu(merge,src,31); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_tu(vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_tu(merge,src,31); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_tu(vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_tu(merge,src,31); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_tu(vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_tu(merge,src,31); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_tu(vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_tu(merge,src,31); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_tu(vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_tu(merge,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-3.c new file mode 100644 index 00000000000..12956462bc0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_tu(merge,src,32); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_tu(merge,src,32); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_tu(vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_tu(merge,src,32); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_tu(vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_tu(merge,src,32); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_tu(vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_tu(merge,src,32); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_tu(vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_tu(merge,src,32); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_tu(merge,src,32); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_tu(vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_tu(merge,src,32); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_tu(vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_tu(merge,src,32); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_tu(vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_tu(merge,src,32); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_tu(vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_tu(merge,src,32); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_tu(vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_tu(merge,src,32); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_tu(vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_tu(merge,src,32); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_tu(vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_tu(merge,src,32); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_tu(vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_tu(merge,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-1.c new file mode 100644 index 00000000000..0c0f5139761 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_tum(mask,merge,src,vl); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_tum(mask,merge,src,vl); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_tum(mask,merge,src,vl); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_tum(mask,merge,src,vl); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_tum(mask,merge,src,vl); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_tum(mask,merge,src,vl); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_tum(mask,merge,src,vl); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_tum(mask,merge,src,vl); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_tum(mask,merge,src,vl); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_tum(mask,merge,src,vl); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_tum(mask,merge,src,vl); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_tum(mask,merge,src,vl); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_tum(mask,merge,src,vl); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_tum(mask,merge,src,vl); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_tum(mask,merge,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-2.c new file mode 100644 index 00000000000..37981fedc85 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_tum(mask,merge,src,31); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_tum(mask,merge,src,31); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_tum(mask,merge,src,31); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_tum(mask,merge,src,31); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_tum(mask,merge,src,31); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_tum(mask,merge,src,31); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_tum(mask,merge,src,31); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_tum(mask,merge,src,31); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_tum(mask,merge,src,31); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_tum(mask,merge,src,31); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_tum(mask,merge,src,31); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_tum(mask,merge,src,31); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_tum(mask,merge,src,31); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_tum(mask,merge,src,31); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_tum(mask,merge,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-3.c new file mode 100644 index 00000000000..9320c6f1c77 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_tum(mask,merge,src,32); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_tum(mask,merge,src,32); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_tum(mask,merge,src,32); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_tum(mask,merge,src,32); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_tum(mask,merge,src,32); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_tum(mask,merge,src,32); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_tum(mask,merge,src,32); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_tum(mask,merge,src,32); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_tum(mask,merge,src,32); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_tum(mask,merge,src,32); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_tum(mask,merge,src,32); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_tum(mask,merge,src,32); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_tum(mask,merge,src,32); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_tum(mask,merge,src,32); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_tum(mask,merge,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-1.c new file mode 100644 index 00000000000..aaf285c333c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_tumu(mask,merge,src,vl); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_tumu(mask,merge,src,vl); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_tumu(mask,merge,src,vl); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_tumu(mask,merge,src,vl); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_tumu(mask,merge,src,vl); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_tumu(mask,merge,src,vl); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_tumu(mask,merge,src,vl); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_tumu(mask,merge,src,vl); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_tumu(mask,merge,src,vl); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_tumu(mask,merge,src,vl); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_tumu(mask,merge,src,vl); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_tumu(mask,merge,src,vl); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_tumu(mask,merge,src,vl); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_tumu(mask,merge,src,vl); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_tumu(mask,merge,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-2.c new file mode 100644 index 00000000000..4acf2a0c159 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_tumu(mask,merge,src,31); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_tumu(mask,merge,src,31); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_tumu(mask,merge,src,31); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_tumu(mask,merge,src,31); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_tumu(mask,merge,src,31); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_tumu(mask,merge,src,31); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_tumu(mask,merge,src,31); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_tumu(mask,merge,src,31); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_tumu(mask,merge,src,31); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_tumu(mask,merge,src,31); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_tumu(mask,merge,src,31); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_tumu(mask,merge,src,31); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_tumu(mask,merge,src,31); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_tumu(mask,merge,src,31); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_tumu(mask,merge,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-3.c new file mode 100644 index 00000000000..05dbe843405 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_tumu(mask,merge,src,32); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_tumu(mask,merge,src,32); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_tumu(mask,merge,src,32); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_tumu(mask,merge,src,32); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_tumu(mask,merge,src,32); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_tumu(mask,merge,src,32); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_tumu(mask,merge,src,32); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_tumu(mask,merge,src,32); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_tumu(mask,merge,src,32); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_tumu(mask,merge,src,32); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_tumu(mask,merge,src,32); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_tumu(mask,merge,src,32); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_tumu(mask,merge,src,32); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_tumu(mask,merge,src,32); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_tumu(mask,merge,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */