From patchwork Tue Feb 7 06:16:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 53702 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2677064wrn; Mon, 6 Feb 2023 22:16:53 -0800 (PST) X-Google-Smtp-Source: AK7set/WLzEWfhUz8rqEV4OlQ6Fa1QbTphoP59dJHxhZTQxJDBznknQb5kOMTPhQREHMwXg42PmU X-Received: by 2002:a17:906:608a:b0:888:4e73:b71d with SMTP id t10-20020a170906608a00b008884e73b71dmr2094731ejj.47.1675750613060; Mon, 06 Feb 2023 22:16:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675750613; cv=none; d=google.com; s=arc-20160816; b=BDxjF/XJjqHu1k4a2CB925/3TifZA1la3wNOZs8h9jOFyu2qfTSCg7K5RzZajAGaXk vhhNCH4owPE+9jpeF5gMSOVrTPnz5jHxExj86DmqjJJsmcWX8VIHWRrflqCEUGSh01QC la5qnINNOehn3LoSX3Ieorn76dpuQ3tdCzb4rjJCZ54eUcm+MiAXMDES1ZZ+GABPrTXG 7T3/lWP5HbLfyb0jWiR1BG+Uia2L9KECn/a3/K4dRn6nmZai9k4vetMWg/6wS0CpLXCk rfxdgK9xnM8YUhlnC5sblczKnyPEW95ibb5Kw4C0vt+GjEMz0nOHFw9AxlezMe4MDqRo lOqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:feedback-id :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:dmarc-filter:delivered-to; bh=Ed8KtlmNhKQR7hdHtcoi/yFp1/6RQmWalP2ZVzAy9io=; b=Xi3l2k02m/jR9wyeTmV3xbOnCaBlpwr91HcrN31w3vGOKvET8tJJY5AO/TIbIBKExY s95WInRDDuKwWBPdZkSTa3P018+oFwBbnSFa0jERYGelPL94+Traipeyftqz5yDnAiet K0YPQOCRbzj5L5F6EujGCTDrC5wPDe7fonkjg5hagJYbRxxMR1nNOR/NPiEksd8Xj5qB WYNUE2IV0ffLnop0RjAQSByNWp3QOJBvmx8CqMNO7hfZHrxdfhEV6LACwVYl3zs3g454 zD9hxkY/YBgn/X3etFu/5vUrtVYZ48QT9Y7yTpmoke7pgYkcBqigxuG/4qneSBUTLtls s5LA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id ek18-20020a056402371200b004a0a7c80997si15090801edb.191.2023.02.06.22.16.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 22:16:53 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EBE7C3858C20 for ; Tue, 7 Feb 2023 06:16:39 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) by sourceware.org (Postfix) with ESMTPS id 148DA3858D1E for ; Tue, 7 Feb 2023 06:16:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 148DA3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp68t1675750562t7lkoyin Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 07 Feb 2023 14:16:01 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: +Odi5FkUgBk1ji5vow/BGHQRqg15YB5u/7Oj6HAzkCA8GyGE5fgpUpj/O9Oh1 EK3BKa3UNa4WvcU8CPKpp2UF0VTOGCO4xO2S2bd5vndeWgB/nWNBoTmxrtm72sZo7gSM0EE Hcg6PAYu9y7weftBMLRKFZzsXWL7pq9r5KveX7pHg0UVbOsbaPEVPofNCwl0rY7ooTRTUPW WgimiGCJvTg14cF6C5Jm63FcMk0HMtxDLES3Mw0LXukkioekP7XTyAhr7M04Gln1mRtwJ6Y QfUbC+mL8QLxZfhlwS/RzVlgqCzhMn/VG/I0uh86RTOex524gcv1vy4MI/vfB7O7/WSnF5e 26bM4mpegyFYm0CKdyMhcFi6YOweafPP389e7UOPxRb6LMc+pPaurqMPrY2r4EGUVtCx764 X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vwsubu.wx C API tests Date: Tue, 7 Feb 2023 14:16:01 +0800 Message-Id: <20230207061601.33379-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757151875082569386?= X-GMAIL-MSGID: =?utf-8?q?1757151875082569386?= From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vwsubu_wx-1.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wx-2.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wx-3.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wx_m-1.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wx_m-2.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wx_m-3.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wx_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wx_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wx_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wx_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wx_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wx_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wx_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wx_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wx_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wx_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wx_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwsubu_wx_tumu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vwsubu_wx-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx_m-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx_m-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwsubu_wx_m-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wx_mu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wx_mu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wx_mu-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wx_tu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wx_tu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wx_tu-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wx_tum-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wx_tum-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wx_tum-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wx_tumu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wx_tumu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_wx_tumu-3.c | 111 ++++++++++++++++++ 18 files changed, 1998 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-1.c new file mode 100644 index 00000000000..7c41784b3ec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_u16mf4(vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf4(op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_u16mf2(vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf2(op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wx_u16m1(vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m1(op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wx_u16m2(vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m2(op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wx_u16m4(vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m4(op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wx_u16m8(vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m8(op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_u32mf2(vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32mf2(op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wx_u32m1(vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m1(op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wx_u32m2(vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m2(op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wx_u32m4(vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m4(op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wx_u32m8(vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m8(op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wx_u64m1(vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m1(op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wx_u64m2(vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m2(op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wx_u64m4(vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m4(op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wx_u64m8(vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m8(op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-2.c new file mode 100644 index 00000000000..bd00cca488b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_u16mf4(vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf4(op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_u16mf2(vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf2(op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwsubu_wx_u16m1(vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m1(op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwsubu_wx_u16m2(vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m2(op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwsubu_wx_u16m4(vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m4(op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwsubu_wx_u16m8(vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m8(op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_u32mf2(vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32mf2(op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwsubu_wx_u32m1(vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m1(op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwsubu_wx_u32m2(vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m2(op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwsubu_wx_u32m4(vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m4(op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwsubu_wx_u32m8(vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m8(op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwsubu_wx_u64m1(vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m1(op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwsubu_wx_u64m2(vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m2(op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwsubu_wx_u64m4(vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m4(op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwsubu_wx_u64m8(vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m8(op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-3.c new file mode 100644 index 00000000000..b3773e65fd1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_u16mf4(vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf4(op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_u16mf2(vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf2(op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwsubu_wx_u16m1(vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m1(op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwsubu_wx_u16m2(vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m2(op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwsubu_wx_u16m4(vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m4(op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwsubu_wx_u16m8(vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m8(op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_u32mf2(vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32mf2(op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwsubu_wx_u32m1(vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m1(op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwsubu_wx_u32m2(vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m2(op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwsubu_wx_u32m4(vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m4(op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwsubu_wx_u32m8(vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m8(op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwsubu_wx_u64m1(vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m1(op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwsubu_wx_u64m2(vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m2(op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwsubu_wx_u64m4(vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m4(op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwsubu_wx_u64m8(vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m8(op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-1.c new file mode 100644 index 00000000000..92ee0af56bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf4_m(mask,op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf2_m(mask,op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m1_m(mask,op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m2_m(mask,op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m4_m(mask,op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m8_m(mask,op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32mf2_m(mask,op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m1_m(mask,op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m2_m(mask,op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m4_m(mask,op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m8_m(mask,op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m1_m(mask,op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m2_m(mask,op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m4_m(mask,op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m8_m(mask,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-2.c new file mode 100644 index 00000000000..593f65f8e6d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf4_m(mask,op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf2_m(mask,op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwsubu_wx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m1_m(mask,op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwsubu_wx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m2_m(mask,op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwsubu_wx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m4_m(mask,op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwsubu_wx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m8_m(mask,op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32mf2_m(mask,op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwsubu_wx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m1_m(mask,op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwsubu_wx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m2_m(mask,op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwsubu_wx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m4_m(mask,op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwsubu_wx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m8_m(mask,op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwsubu_wx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m1_m(mask,op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwsubu_wx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m2_m(mask,op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwsubu_wx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m4_m(mask,op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwsubu_wx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m8_m(mask,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-3.c new file mode 100644 index 00000000000..04cc98d1eea --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf4_m(mask,op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf2_m(mask,op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwsubu_wx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m1_m(mask,op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwsubu_wx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m2_m(mask,op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwsubu_wx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m4_m(mask,op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwsubu_wx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m8_m(mask,op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32mf2_m(mask,op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwsubu_wx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m1_m(mask,op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwsubu_wx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m2_m(mask,op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwsubu_wx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m4_m(mask,op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwsubu_wx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m8_m(mask,op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwsubu_wx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m1_m(mask,op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwsubu_wx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m2_m(mask,op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwsubu_wx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m4_m(mask,op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwsubu_wx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m8_m(mask,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-1.c new file mode 100644 index 00000000000..3ae20d21bcd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf4_mu(mask,merge,op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf2_mu(mask,merge,op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m1_mu(mask,merge,op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m2_mu(mask,merge,op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m4_mu(mask,merge,op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m8_mu(mask,merge,op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32mf2_mu(mask,merge,op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m1_mu(mask,merge,op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m2_mu(mask,merge,op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m4_mu(mask,merge,op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m8_mu(mask,merge,op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m1_mu(mask,merge,op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m2_mu(mask,merge,op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m4_mu(mask,merge,op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m8_mu(mask,merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-2.c new file mode 100644 index 00000000000..68fcc3b789e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf4_mu(mask,merge,op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf2_mu(mask,merge,op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwsubu_wx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m1_mu(mask,merge,op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwsubu_wx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m2_mu(mask,merge,op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwsubu_wx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m4_mu(mask,merge,op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwsubu_wx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m8_mu(mask,merge,op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32mf2_mu(mask,merge,op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwsubu_wx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m1_mu(mask,merge,op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwsubu_wx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m2_mu(mask,merge,op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwsubu_wx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m4_mu(mask,merge,op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwsubu_wx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m8_mu(mask,merge,op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwsubu_wx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m1_mu(mask,merge,op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwsubu_wx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m2_mu(mask,merge,op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwsubu_wx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m4_mu(mask,merge,op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwsubu_wx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m8_mu(mask,merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-3.c new file mode 100644 index 00000000000..a8f29a9dff6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf4_mu(mask,merge,op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf2_mu(mask,merge,op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwsubu_wx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m1_mu(mask,merge,op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwsubu_wx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m2_mu(mask,merge,op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwsubu_wx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m4_mu(mask,merge,op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwsubu_wx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m8_mu(mask,merge,op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32mf2_mu(mask,merge,op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwsubu_wx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m1_mu(mask,merge,op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwsubu_wx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m2_mu(mask,merge,op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwsubu_wx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m4_mu(mask,merge,op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwsubu_wx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m8_mu(mask,merge,op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwsubu_wx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m1_mu(mask,merge,op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwsubu_wx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m2_mu(mask,merge,op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwsubu_wx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m4_mu(mask,merge,op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwsubu_wx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m8_mu(mask,merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-1.c new file mode 100644 index 00000000000..6b5e8ae5d80 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf4_tu(merge,op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf2_tu(merge,op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m1_tu(merge,op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m2_tu(merge,op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m4_tu(merge,op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m8_tu(merge,op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32mf2_tu(merge,op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m1_tu(merge,op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m2_tu(merge,op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m4_tu(merge,op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m8_tu(merge,op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m1_tu(merge,op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m2_tu(merge,op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m4_tu(merge,op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m8_tu(merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-2.c new file mode 100644 index 00000000000..07cfee7b0c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf4_tu(merge,op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf2_tu(merge,op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwsubu_wx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m1_tu(merge,op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwsubu_wx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m2_tu(merge,op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwsubu_wx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m4_tu(merge,op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwsubu_wx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m8_tu(merge,op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32mf2_tu(merge,op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwsubu_wx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m1_tu(merge,op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwsubu_wx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m2_tu(merge,op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwsubu_wx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m4_tu(merge,op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwsubu_wx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m8_tu(merge,op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwsubu_wx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m1_tu(merge,op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwsubu_wx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m2_tu(merge,op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwsubu_wx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m4_tu(merge,op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwsubu_wx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m8_tu(merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-3.c new file mode 100644 index 00000000000..c8d1ccb1c56 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf4_tu(merge,op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf2_tu(merge,op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwsubu_wx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m1_tu(merge,op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwsubu_wx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m2_tu(merge,op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwsubu_wx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m4_tu(merge,op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwsubu_wx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m8_tu(merge,op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32mf2_tu(merge,op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwsubu_wx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m1_tu(merge,op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwsubu_wx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m2_tu(merge,op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwsubu_wx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m4_tu(merge,op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwsubu_wx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m8_tu(merge,op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwsubu_wx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m1_tu(merge,op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwsubu_wx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m2_tu(merge,op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwsubu_wx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m4_tu(merge,op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwsubu_wx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m8_tu(merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-1.c new file mode 100644 index 00000000000..7e5ed5faabe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf4_tum(mask,merge,op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf2_tum(mask,merge,op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m1_tum(mask,merge,op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m2_tum(mask,merge,op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m4_tum(mask,merge,op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m8_tum(mask,merge,op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32mf2_tum(mask,merge,op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m1_tum(mask,merge,op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m2_tum(mask,merge,op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m4_tum(mask,merge,op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m8_tum(mask,merge,op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m1_tum(mask,merge,op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m2_tum(mask,merge,op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m4_tum(mask,merge,op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m8_tum(mask,merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-2.c new file mode 100644 index 00000000000..1ba985e96fc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf4_tum(mask,merge,op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf2_tum(mask,merge,op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwsubu_wx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m1_tum(mask,merge,op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwsubu_wx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m2_tum(mask,merge,op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwsubu_wx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m4_tum(mask,merge,op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwsubu_wx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m8_tum(mask,merge,op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32mf2_tum(mask,merge,op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwsubu_wx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m1_tum(mask,merge,op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwsubu_wx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m2_tum(mask,merge,op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwsubu_wx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m4_tum(mask,merge,op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwsubu_wx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m8_tum(mask,merge,op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwsubu_wx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m1_tum(mask,merge,op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwsubu_wx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m2_tum(mask,merge,op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwsubu_wx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m4_tum(mask,merge,op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwsubu_wx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m8_tum(mask,merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-3.c new file mode 100644 index 00000000000..2d367ef5c0f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf4_tum(mask,merge,op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf2_tum(mask,merge,op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwsubu_wx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m1_tum(mask,merge,op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwsubu_wx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m2_tum(mask,merge,op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwsubu_wx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m4_tum(mask,merge,op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwsubu_wx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m8_tum(mask,merge,op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32mf2_tum(mask,merge,op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwsubu_wx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m1_tum(mask,merge,op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwsubu_wx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m2_tum(mask,merge,op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwsubu_wx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m4_tum(mask,merge,op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwsubu_wx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m8_tum(mask,merge,op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwsubu_wx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m1_tum(mask,merge,op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwsubu_wx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m2_tum(mask,merge,op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwsubu_wx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m4_tum(mask,merge,op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwsubu_wx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m8_tum(mask,merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-1.c new file mode 100644 index 00000000000..98b345e9161 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf4_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf2_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwsubu_wx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m1_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwsubu_wx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m2_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwsubu_wx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m4_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwsubu_wx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m8_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32mf2_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwsubu_wx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m1_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwsubu_wx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m2_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwsubu_wx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m4_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwsubu_wx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m8_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwsubu_wx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m1_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwsubu_wx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m2_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwsubu_wx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m4_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwsubu_wx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m8_tumu(mask,merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-2.c new file mode 100644 index 00000000000..e70a1b92e1b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf4_tumu(mask,merge,op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf2_tumu(mask,merge,op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwsubu_wx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m1_tumu(mask,merge,op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwsubu_wx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m2_tumu(mask,merge,op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwsubu_wx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m4_tumu(mask,merge,op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwsubu_wx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m8_tumu(mask,merge,op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32mf2_tumu(mask,merge,op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwsubu_wx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m1_tumu(mask,merge,op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwsubu_wx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m2_tumu(mask,merge,op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwsubu_wx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m4_tumu(mask,merge,op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwsubu_wx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m8_tumu(mask,merge,op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwsubu_wx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m1_tumu(mask,merge,op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwsubu_wx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m2_tumu(mask,merge,op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwsubu_wx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m4_tumu(mask,merge,op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwsubu_wx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m8_tumu(mask,merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-3.c new file mode 100644 index 00000000000..e47c4fe0329 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf4_tumu(mask,merge,op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16mf2_tumu(mask,merge,op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwsubu_wx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m1_tumu(mask,merge,op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwsubu_wx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m2_tumu(mask,merge,op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwsubu_wx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m4_tumu(mask,merge,op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwsubu_wx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u16m8_tumu(mask,merge,op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32mf2_tumu(mask,merge,op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwsubu_wx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m1_tumu(mask,merge,op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwsubu_wx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m2_tumu(mask,merge,op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwsubu_wx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m4_tumu(mask,merge,op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwsubu_wx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u32m8_tumu(mask,merge,op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwsubu_wx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m1_tumu(mask,merge,op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwsubu_wx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m2_tumu(mask,merge,op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwsubu_wx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m4_tumu(mask,merge,op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwsubu_wx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_wx_u64m8_tumu(mask,merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */