RISC-V: Add vwsubu.wx C API tests

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-1.c
new file mode 100644
index 00000000000..7c41784b3ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wx_u16mf4(vuint16mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf4(op1,0xAA,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wx_u16mf2(vuint16mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf2(op1,0xAA,vl);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wx_u16m1(vuint16m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m1(op1,0xAA,vl);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wx_u16m2(vuint16m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m2(op1,0xAA,vl);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wx_u16m4(vuint16m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m4(op1,0xAA,vl);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wx_u16m8(vuint16m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m8(op1,0xAA,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wx_u32mf2(vuint32mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32mf2(op1,0xAA,vl);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wx_u32m1(vuint32m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m1(op1,0xAA,vl);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wx_u32m2(vuint32m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m2(op1,0xAA,vl);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wx_u32m4(vuint32m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m4(op1,0xAA,vl);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wx_u32m8(vuint32m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m8(op1,0xAA,vl);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wx_u64m1(vuint64m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m1(op1,0xAA,vl);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wx_u64m2(vuint64m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m2(op1,0xAA,vl);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wx_u64m4(vuint64m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m4(op1,0xAA,vl);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wx_u64m8(vuint64m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m8(op1,0xAA,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-2.c
new file mode 100644
index 00000000000..bd00cca488b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wx_u16mf4(vuint16mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf4(op1,0xAA,31);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wx_u16mf2(vuint16mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf2(op1,0xAA,31);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wx_u16m1(vuint16m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m1(op1,0xAA,31);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wx_u16m2(vuint16m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m2(op1,0xAA,31);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wx_u16m4(vuint16m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m4(op1,0xAA,31);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wx_u16m8(vuint16m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m8(op1,0xAA,31);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wx_u32mf2(vuint32mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32mf2(op1,0xAA,31);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wx_u32m1(vuint32m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m1(op1,0xAA,31);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wx_u32m2(vuint32m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m2(op1,0xAA,31);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wx_u32m4(vuint32m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m4(op1,0xAA,31);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wx_u32m8(vuint32m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m8(op1,0xAA,31);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wx_u64m1(vuint64m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m1(op1,0xAA,31);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wx_u64m2(vuint64m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m2(op1,0xAA,31);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wx_u64m4(vuint64m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m4(op1,0xAA,31);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wx_u64m8(vuint64m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m8(op1,0xAA,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-3.c
new file mode 100644
index 00000000000..b3773e65fd1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wx_u16mf4(vuint16mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf4(op1,0xAA,32);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wx_u16mf2(vuint16mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf2(op1,0xAA,32);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wx_u16m1(vuint16m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m1(op1,0xAA,32);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wx_u16m2(vuint16m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m2(op1,0xAA,32);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wx_u16m4(vuint16m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m4(op1,0xAA,32);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wx_u16m8(vuint16m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m8(op1,0xAA,32);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wx_u32mf2(vuint32mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32mf2(op1,0xAA,32);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wx_u32m1(vuint32m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m1(op1,0xAA,32);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wx_u32m2(vuint32m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m2(op1,0xAA,32);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wx_u32m4(vuint32m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m4(op1,0xAA,32);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wx_u32m8(vuint32m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m8(op1,0xAA,32);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wx_u64m1(vuint64m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m1(op1,0xAA,32);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wx_u64m2(vuint64m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m2(op1,0xAA,32);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wx_u64m4(vuint64m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m4(op1,0xAA,32);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wx_u64m8(vuint64m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m8(op1,0xAA,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-1.c
new file mode 100644
index 00000000000..92ee0af56bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf4_m(mask,op1,0xAA,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf2_m(mask,op1,0xAA,vl);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m1_m(mask,op1,0xAA,vl);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m2_m(mask,op1,0xAA,vl);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m4_m(mask,op1,0xAA,vl);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m8_m(mask,op1,0xAA,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32mf2_m(mask,op1,0xAA,vl);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m1_m(mask,op1,0xAA,vl);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m2_m(mask,op1,0xAA,vl);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m4_m(mask,op1,0xAA,vl);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m8_m(mask,op1,0xAA,vl);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m1_m(mask,op1,0xAA,vl);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m2_m(mask,op1,0xAA,vl);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m4_m(mask,op1,0xAA,vl);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m8_m(mask,op1,0xAA,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-2.c
new file mode 100644
index 00000000000..593f65f8e6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf4_m(mask,op1,0xAA,31);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf2_m(mask,op1,0xAA,31);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m1_m(mask,op1,0xAA,31);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m2_m(mask,op1,0xAA,31);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m4_m(mask,op1,0xAA,31);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m8_m(mask,op1,0xAA,31);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32mf2_m(mask,op1,0xAA,31);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m1_m(mask,op1,0xAA,31);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m2_m(mask,op1,0xAA,31);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m4_m(mask,op1,0xAA,31);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m8_m(mask,op1,0xAA,31);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m1_m(mask,op1,0xAA,31);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m2_m(mask,op1,0xAA,31);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m4_m(mask,op1,0xAA,31);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m8_m(mask,op1,0xAA,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-3.c
new file mode 100644
index 00000000000..04cc98d1eea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf4_m(mask,op1,0xAA,32);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf2_m(mask,op1,0xAA,32);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m1_m(mask,op1,0xAA,32);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m2_m(mask,op1,0xAA,32);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m4_m(mask,op1,0xAA,32);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m8_m(mask,op1,0xAA,32);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32mf2_m(mask,op1,0xAA,32);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m1_m(mask,op1,0xAA,32);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m2_m(mask,op1,0xAA,32);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m4_m(mask,op1,0xAA,32);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m8_m(mask,op1,0xAA,32);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m1_m(mask,op1,0xAA,32);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m2_m(mask,op1,0xAA,32);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m4_m(mask,op1,0xAA,32);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m8_m(mask,op1,0xAA,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-1.c
new file mode 100644
index 00000000000..3ae20d21bcd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf4_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf2_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m1_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m2_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m4_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m8_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32mf2_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m1_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m2_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m4_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m8_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m1_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m2_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m4_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m8_mu(mask,merge,op1,0xAA,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-2.c
new file mode 100644
index 00000000000..68fcc3b789e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf4_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf2_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m1_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m2_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m4_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m8_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32mf2_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m1_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m2_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m4_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m8_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m1_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m2_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m4_mu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m8_mu(mask,merge,op1,0xAA,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-3.c
new file mode 100644
index 00000000000..a8f29a9dff6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf4_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf2_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m1_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m2_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m4_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m8_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32mf2_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m1_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m2_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m4_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m8_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m1_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m2_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m4_mu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m8_mu(mask,merge,op1,0xAA,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-1.c
new file mode 100644
index 00000000000..6b5e8ae5d80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf4_tu(merge,op1,0xAA,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf2_tu(merge,op1,0xAA,vl);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m1_tu(merge,op1,0xAA,vl);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m2_tu(merge,op1,0xAA,vl);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m4_tu(merge,op1,0xAA,vl);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m8_tu(merge,op1,0xAA,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32mf2_tu(merge,op1,0xAA,vl);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m1_tu(merge,op1,0xAA,vl);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m2_tu(merge,op1,0xAA,vl);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m4_tu(merge,op1,0xAA,vl);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m8_tu(merge,op1,0xAA,vl);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m1_tu(merge,op1,0xAA,vl);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m2_tu(merge,op1,0xAA,vl);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m4_tu(merge,op1,0xAA,vl);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m8_tu(merge,op1,0xAA,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-2.c
new file mode 100644
index 00000000000..07cfee7b0c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf4_tu(merge,op1,0xAA,31);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf2_tu(merge,op1,0xAA,31);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m1_tu(merge,op1,0xAA,31);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m2_tu(merge,op1,0xAA,31);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m4_tu(merge,op1,0xAA,31);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m8_tu(merge,op1,0xAA,31);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32mf2_tu(merge,op1,0xAA,31);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m1_tu(merge,op1,0xAA,31);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m2_tu(merge,op1,0xAA,31);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m4_tu(merge,op1,0xAA,31);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m8_tu(merge,op1,0xAA,31);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m1_tu(merge,op1,0xAA,31);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m2_tu(merge,op1,0xAA,31);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m4_tu(merge,op1,0xAA,31);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m8_tu(merge,op1,0xAA,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-3.c
new file mode 100644
index 00000000000..c8d1ccb1c56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf4_tu(merge,op1,0xAA,32);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf2_tu(merge,op1,0xAA,32);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m1_tu(merge,op1,0xAA,32);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m2_tu(merge,op1,0xAA,32);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m4_tu(merge,op1,0xAA,32);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m8_tu(merge,op1,0xAA,32);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32mf2_tu(merge,op1,0xAA,32);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m1_tu(merge,op1,0xAA,32);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m2_tu(merge,op1,0xAA,32);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m4_tu(merge,op1,0xAA,32);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m8_tu(merge,op1,0xAA,32);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m1_tu(merge,op1,0xAA,32);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m2_tu(merge,op1,0xAA,32);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m4_tu(merge,op1,0xAA,32);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m8_tu(merge,op1,0xAA,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-1.c
new file mode 100644
index 00000000000..7e5ed5faabe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf4_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf2_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m1_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m2_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m4_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m8_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32mf2_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m1_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m2_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m4_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m8_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m1_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m2_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m4_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m8_tum(mask,merge,op1,0xAA,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-2.c
new file mode 100644
index 00000000000..1ba985e96fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf4_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf2_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m1_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m2_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m4_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m8_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32mf2_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m1_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m2_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m4_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m8_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m1_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m2_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m4_tum(mask,merge,op1,0xAA,31);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m8_tum(mask,merge,op1,0xAA,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-3.c
new file mode 100644
index 00000000000..2d367ef5c0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf4_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf2_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m1_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m2_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m4_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m8_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32mf2_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m1_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m2_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m4_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m8_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m1_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m2_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m4_tum(mask,merge,op1,0xAA,32);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m8_tum(mask,merge,op1,0xAA,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-1.c
new file mode 100644
index 00000000000..98b345e9161
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf4_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf2_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m1_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m2_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m4_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m8_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32mf2_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m1_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m2_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m4_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m8_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m1_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m2_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m4_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m8_tumu(mask,merge,op1,0xAA,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-2.c
new file mode 100644
index 00000000000..e70a1b92e1b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf4_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf2_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m1_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m2_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m4_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m8_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32mf2_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m1_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m2_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m4_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m8_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m1_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m2_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m4_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m8_tumu(mask,merge,op1,0xAA,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-3.c
new file mode 100644
index 00000000000..e47c4fe0329
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf4_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16mf2_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m1_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m2_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m4_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u16m8_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32mf2_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m1_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m2_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m4_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u32m8_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m1_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m2_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m4_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wx_u64m8_tumu(mask,merge,op1,0xAA,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */