diff mbox series

RISC-V: Add vmulhsu.vx C++ API tests

Message ID 20230206125551.89879-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Add vmulhsu.vx C++ API tests |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai Feb. 6, 2023, 12:55 p.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.C: New test.

---
 .../riscv/rvv/base/vmulhsu_vx_mu_rv32-1.C     | 157 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_mu_rv32-2.C     | 157 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_mu_rv32-3.C     | 157 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_mu_rv64-1.C     | 160 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_mu_rv64-2.C     | 160 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_mu_rv64-3.C     | 160 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_rv32-1.C        | 308 +++++++++++++++++
 .../riscv/rvv/base/vmulhsu_vx_rv32-2.C        | 308 +++++++++++++++++
 .../riscv/rvv/base/vmulhsu_vx_rv32-3.C        | 308 +++++++++++++++++
 .../riscv/rvv/base/vmulhsu_vx_rv64-1.C        | 314 ++++++++++++++++++
 .../riscv/rvv/base/vmulhsu_vx_rv64-2.C        | 314 ++++++++++++++++++
 .../riscv/rvv/base/vmulhsu_vx_rv64-3.C        | 314 ++++++++++++++++++
 .../riscv/rvv/base/vmulhsu_vx_tu_rv32-1.C     | 157 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_tu_rv32-2.C     | 157 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_tu_rv32-3.C     | 157 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_tu_rv64-1.C     | 160 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_tu_rv64-2.C     | 160 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_tu_rv64-3.C     | 160 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_tum_rv32-1.C    | 157 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_tum_rv32-2.C    | 157 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_tum_rv32-3.C    | 157 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_tum_rv64-1.C    | 160 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_tum_rv64-2.C    | 160 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_tum_rv64-3.C    | 160 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.C   | 157 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.C   | 157 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.C   | 157 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.C   | 160 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.C   | 160 +++++++++
 .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.C   | 160 +++++++++
 30 files changed, 5670 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.C
diff mbox series

Patch

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.C
new file mode 100644
index 00000000000..50fba59af46
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.C
new file mode 100644
index 00000000000..bb26e7420d1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.C
new file mode 100644
index 00000000000..14fa0917de6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.C
new file mode 100644
index 00000000000..d882f34f19d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.C
new file mode 100644
index 00000000000..1e27032ee5a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.C
new file mode 100644
index 00000000000..a85e843e461
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-1.C
new file mode 100644
index 00000000000..8d875f983e8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-1.C
@@ -0,0 +1,308 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu(vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu(vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu(vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmulhsu(vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmulhsu(vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmulhsu(vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmulhsu(vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu(vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu(vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmulhsu(vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmulhsu(vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmulhsu(vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmulhsu(vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu(vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmulhsu(vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmulhsu(vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmulhsu(vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmulhsu(vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmulhsu(vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmulhsu(vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmulhsu(vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmulhsu(vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint8mf8_t test___riscv_vmulhsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmulhsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmulhsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmulhsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmulhsu(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmulhsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmulhsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmulhsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmulhsu(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmulhsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmulhsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmulhsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmulhsu(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmulhsu(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmulhsu(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmulhsu(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmulhsu(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-2.C
new file mode 100644
index 00000000000..03feada95a1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-2.C
@@ -0,0 +1,308 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu(vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu(vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu(vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmulhsu(vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmulhsu(vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmulhsu(vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmulhsu(vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu(vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu(vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmulhsu(vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmulhsu(vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmulhsu(vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmulhsu(vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu(vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmulhsu(vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmulhsu(vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmulhsu(vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmulhsu(vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmulhsu(vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmulhsu(vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmulhsu(vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmulhsu(vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint8mf8_t test___riscv_vmulhsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmulhsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmulhsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmulhsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmulhsu(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmulhsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmulhsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmulhsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmulhsu(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmulhsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmulhsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmulhsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmulhsu(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmulhsu(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmulhsu(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmulhsu(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmulhsu(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-3.C
new file mode 100644
index 00000000000..4b3c876016b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-3.C
@@ -0,0 +1,308 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu(vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu(vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu(vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmulhsu(vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmulhsu(vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmulhsu(vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmulhsu(vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu(vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu(vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmulhsu(vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmulhsu(vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmulhsu(vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmulhsu(vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu(vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmulhsu(vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmulhsu(vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmulhsu(vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmulhsu(vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmulhsu(vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmulhsu(vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmulhsu(vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmulhsu(vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint8mf8_t test___riscv_vmulhsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmulhsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmulhsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmulhsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmulhsu(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmulhsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmulhsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmulhsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmulhsu(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmulhsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmulhsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmulhsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmulhsu(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmulhsu(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmulhsu(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmulhsu(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmulhsu(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-1.C
new file mode 100644
index 00000000000..81c3b26e34f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-1.C
@@ -0,0 +1,314 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu(vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu(vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu(vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmulhsu(vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmulhsu(vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmulhsu(vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmulhsu(vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu(vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu(vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmulhsu(vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmulhsu(vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmulhsu(vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmulhsu(vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu(vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmulhsu(vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmulhsu(vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmulhsu(vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmulhsu(vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmulhsu(vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmulhsu(vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmulhsu(vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmulhsu(vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint8mf8_t test___riscv_vmulhsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmulhsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmulhsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmulhsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmulhsu(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmulhsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmulhsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmulhsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmulhsu(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmulhsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmulhsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmulhsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmulhsu(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmulhsu(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmulhsu(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmulhsu(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmulhsu(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-2.C
new file mode 100644
index 00000000000..833d463bac2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-2.C
@@ -0,0 +1,314 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu(vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu(vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu(vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmulhsu(vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmulhsu(vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmulhsu(vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmulhsu(vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu(vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu(vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmulhsu(vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmulhsu(vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmulhsu(vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmulhsu(vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu(vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmulhsu(vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmulhsu(vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmulhsu(vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmulhsu(vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmulhsu(vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmulhsu(vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmulhsu(vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmulhsu(vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,31);
+}
+
+
+vint8mf8_t test___riscv_vmulhsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmulhsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmulhsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmulhsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmulhsu(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmulhsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmulhsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmulhsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmulhsu(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmulhsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmulhsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmulhsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmulhsu(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmulhsu(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmulhsu(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmulhsu(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmulhsu(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-3.C
new file mode 100644
index 00000000000..bb575d319eb
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-3.C
@@ -0,0 +1,314 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu(vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu(vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu(vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmulhsu(vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmulhsu(vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmulhsu(vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmulhsu(vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu(vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu(vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmulhsu(vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmulhsu(vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmulhsu(vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmulhsu(vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu(vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmulhsu(vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmulhsu(vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmulhsu(vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmulhsu(vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmulhsu(vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmulhsu(vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmulhsu(vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmulhsu(vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(op1,op2,32);
+}
+
+
+vint8mf8_t test___riscv_vmulhsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmulhsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmulhsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmulhsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmulhsu(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmulhsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmulhsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmulhsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmulhsu(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmulhsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmulhsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmulhsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmulhsu(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmulhsu(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmulhsu(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmulhsu(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmulhsu(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.C
new file mode 100644
index 00000000000..febe18d4f0d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.C
new file mode 100644
index 00000000000..672533c682a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.C
new file mode 100644
index 00000000000..cd46ef1f6aa
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.C
new file mode 100644
index 00000000000..329a188285d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.C
new file mode 100644
index 00000000000..43dfe69f897
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.C
new file mode 100644
index 00000000000..66df249ce3d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.C
new file mode 100644
index 00000000000..430b18b10c8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.C
new file mode 100644
index 00000000000..0ddf21a6e0a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.C
new file mode 100644
index 00000000000..ab8a2ed74b9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.C
new file mode 100644
index 00000000000..52942c45a68
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.C
new file mode 100644
index 00000000000..5dbd3b35e07
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.C
new file mode 100644
index 00000000000..80d6565ff64
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.C
new file mode 100644
index 00000000000..2c6cf9ca1e6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.C
new file mode 100644
index 00000000000..f3fec8af9c6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.C
new file mode 100644
index 00000000000..edbcb78e19a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.C
new file mode 100644
index 00000000000..d3ffc1f3e4a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.C
new file mode 100644
index 00000000000..1aa19f2b51f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.C
new file mode 100644
index 00000000000..8c73d15b76d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmulhsu_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */