diff mbox series

RISC-V: Add vzext.vf2 C++ API tests

Message ID	20230206052429.234436-1-juzhe.zhong@rivai.ai
State	Accepted
Headers	Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BEFA83858D1E From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong <juzhe.zhong@rivai.ai> Subject: [PATCH] RISC-V: Add vzext.vf2 C++ API tests Date: Mon, 6 Feb 2023 13:24:29 +0800 Message-Id: <20230206052429.234436-1-juzhe.zhong@rivai.ai> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 Precedence: list Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org> X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?=
Series	RISC-V: Add vzext.vf2 C++ API tests \| RISC-V: Add vzext.vf2 C++ API tests

Checks

Context	Check	Description
snail/gcc-patch-check	success	Github commit url

Commit Message

juzhe.zhong@rivai.ai Feb. 6, 2023, 5:24 a.m. UTC

  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vzext_vf2-1.C: New test.
        * g++.target/riscv/rvv/base/vzext_vf2-2.C: New test.
        * g++.target/riscv/rvv/base/vzext_vf2-3.C: New test.
        * g++.target/riscv/rvv/base/vzext_vf2_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vzext_vf2_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vzext_vf2_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vzext_vf2_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vzext_vf2_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vzext_vf2_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vzext_vf2_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vzext_vf2_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vzext_vf2_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vzext_vf2_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vzext_vf2_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vzext_vf2_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vzext_vf2-1.C   | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vzext_vf2-2.C   | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vzext_vf2-3.C   | 216 ++++++++++++++++++
 .../riscv/rvv/base/vzext_vf2_mu-1.C           | 111 +++++++++
 .../riscv/rvv/base/vzext_vf2_mu-2.C           | 111 +++++++++
 .../riscv/rvv/base/vzext_vf2_mu-3.C           | 111 +++++++++
 .../riscv/rvv/base/vzext_vf2_tu-1.C           | 111 +++++++++
 .../riscv/rvv/base/vzext_vf2_tu-2.C           | 111 +++++++++
 .../riscv/rvv/base/vzext_vf2_tu-3.C           | 111 +++++++++
 .../riscv/rvv/base/vzext_vf2_tum-1.C          | 111 +++++++++
 .../riscv/rvv/base/vzext_vf2_tum-2.C          | 111 +++++++++
 .../riscv/rvv/base/vzext_vf2_tum-3.C          | 111 +++++++++
 .../riscv/rvv/base/vzext_vf2_tumu-1.C         | 111 +++++++++
 .../riscv/rvv/base/vzext_vf2_tumu-2.C         | 111 +++++++++
 .../riscv/rvv/base/vzext_vf2_tumu-3.C         | 111 +++++++++
 15 files changed, 1980 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-3.C

diff mbox series

Patch

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-1.C
new file mode 100644
index 00000000000..4e9c81cf87f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-1.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2(vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2(vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2(vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2(vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2(vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2(vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2(vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2(vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2(vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2(vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2(vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2(vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2(vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2(vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2(vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint16mf4_t test___riscv_vzext_vf2(vbool64_t mask,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,vl);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2(vbool32_t mask,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,vl);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2(vbool16_t mask,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,vl);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2(vbool8_t mask,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,vl);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2(vbool4_t mask,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,vl);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2(vbool2_t mask,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,vl);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2(vbool64_t mask,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,vl);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2(vbool32_t mask,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,vl);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2(vbool16_t mask,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,vl);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2(vbool8_t mask,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,vl);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2(vbool4_t mask,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,vl);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2(vbool64_t mask,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2(vbool32_t mask,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2(vbool16_t mask,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2(vbool8_t mask,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-2.C
new file mode 100644
index 00000000000..13a0756d03e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-2.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2(vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,31);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2(vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,31);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2(vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,31);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2(vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,31);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2(vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,31);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2(vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,31);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2(vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,31);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2(vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,31);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2(vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,31);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2(vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,31);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2(vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,31);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2(vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2(vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2(vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2(vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,31);
+}
+
+
+vuint16mf4_t test___riscv_vzext_vf2(vbool64_t mask,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,31);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2(vbool32_t mask,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,31);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2(vbool16_t mask,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,31);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2(vbool8_t mask,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,31);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2(vbool4_t mask,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,31);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2(vbool2_t mask,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,31);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2(vbool64_t mask,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,31);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2(vbool32_t mask,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,31);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2(vbool16_t mask,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,31);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2(vbool8_t mask,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,31);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2(vbool4_t mask,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,31);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2(vbool64_t mask,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2(vbool32_t mask,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2(vbool16_t mask,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2(vbool8_t mask,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-3.C
new file mode 100644
index 00000000000..fdc37d18ee2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-3.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2(vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,32);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2(vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,32);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2(vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,32);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2(vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,32);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2(vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,32);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2(vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,32);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2(vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,32);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2(vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,32);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2(vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,32);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2(vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,32);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2(vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,32);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2(vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2(vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2(vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2(vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(op1,32);
+}
+
+
+vuint16mf4_t test___riscv_vzext_vf2(vbool64_t mask,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,32);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2(vbool32_t mask,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,32);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2(vbool16_t mask,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,32);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2(vbool8_t mask,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,32);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2(vbool4_t mask,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,32);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2(vbool2_t mask,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,32);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2(vbool64_t mask,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,32);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2(vbool32_t mask,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,32);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2(vbool16_t mask,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,32);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2(vbool8_t mask,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,32);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2(vbool4_t mask,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,32);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2(vbool64_t mask,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2(vbool32_t mask,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2(vbool16_t mask,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2(vbool8_t mask,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2(mask,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-1.C
new file mode 100644
index 00000000000..fc136be7d95
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,vl);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,vl);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,vl);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,vl);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,vl);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,vl);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,vl);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,vl);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,vl);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,vl);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,vl);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-2.C
new file mode 100644
index 00000000000..08649144f7d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,31);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,31);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,31);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,31);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,31);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,31);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,31);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,31);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,31);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,31);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,31);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-3.C
new file mode 100644
index 00000000000..fceecc16742
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,32);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,32);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,32);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,32);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,32);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,32);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,32);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,32);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,32);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,32);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,32);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_mu(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-1.C
new file mode 100644
index 00000000000..a01c708cf4d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_tu(vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,vl);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,vl);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_tu(vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,vl);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_tu(vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,vl);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_tu(vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,vl);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_tu(vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,vl);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,vl);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_tu(vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,vl);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_tu(vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,vl);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_tu(vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,vl);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_tu(vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,vl);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_tu(vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_tu(vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_tu(vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_tu(vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-2.C
new file mode 100644
index 00000000000..cd76d77233f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_tu(vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,31);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,31);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_tu(vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,31);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_tu(vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,31);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_tu(vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,31);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_tu(vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,31);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,31);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_tu(vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,31);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_tu(vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,31);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_tu(vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,31);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_tu(vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,31);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_tu(vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_tu(vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_tu(vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_tu(vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-3.C
new file mode 100644
index 00000000000..c33e78d47c2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_tu(vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,32);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,32);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_tu(vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,32);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_tu(vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,32);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_tu(vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,32);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_tu(vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,32);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,32);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_tu(vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,32);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_tu(vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,32);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_tu(vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,32);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_tu(vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,32);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_tu(vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_tu(vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_tu(vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_tu(vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tu(merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-1.C
new file mode 100644
index 00000000000..953e4a14eda
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,vl);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,vl);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,vl);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,vl);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,vl);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,vl);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,vl);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,vl);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,vl);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,vl);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,vl);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-2.C
new file mode 100644
index 00000000000..4ef3abd0aca
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,31);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,31);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,31);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,31);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,31);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,31);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,31);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,31);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,31);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,31);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,31);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-3.C
new file mode 100644
index 00000000000..8bc1c93bbac
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,32);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,32);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,32);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,32);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,32);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,32);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,32);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,32);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,32);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,32);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,32);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tum(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-1.C
new file mode 100644
index 00000000000..febc64c5b3a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,vl);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,vl);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,vl);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,vl);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,vl);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,vl);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,vl);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,vl);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,vl);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,vl);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,vl);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-2.C
new file mode 100644
index 00000000000..ba33ba5b227
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,31);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,31);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,31);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,31);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,31);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,31);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,31);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,31);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,31);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,31);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,31);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-3.C
new file mode 100644
index 00000000000..d8b8b77f207
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,32);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,32);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,32);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,32);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,32);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,32);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,32);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,32);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,32);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,32);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,32);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_tumu(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */