diff mbox series

RISC-V: Add vzext.vf2 C API tests

Message ID 20230206051106.215903-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Add vzext.vf2 C API tests |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai Feb. 6, 2023, 5:11 a.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/vzext_vf2-1.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf2-2.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf2-3.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf2_m-1.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf2_m-2.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf2_m-3.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf2_mu-1.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf2_mu-2.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf2_mu-3.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf2_tu-1.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf2_tu-2.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf2_tu-3.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf2_tum-1.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf2_tum-2.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf2_tum-3.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf2_tumu-1.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf2_tumu-2.c: New test.
        * gcc.target/riscv/rvv/base/vzext_vf2_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vzext_vf2-1.c   | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vzext_vf2-2.c   | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vzext_vf2-3.c   | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vzext_vf2_m-1.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vzext_vf2_m-2.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vzext_vf2_m-3.c | 111 ++++++++++++++++++
 .../riscv/rvv/base/vzext_vf2_mu-1.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vzext_vf2_mu-2.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vzext_vf2_mu-3.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vzext_vf2_tu-1.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vzext_vf2_tu-2.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vzext_vf2_tu-3.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vzext_vf2_tum-1.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vzext_vf2_tum-2.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vzext_vf2_tum-3.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vzext_vf2_tumu-1.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vzext_vf2_tumu-2.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vzext_vf2_tumu-3.c         | 111 ++++++++++++++++++
 18 files changed, 1998 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tumu-3.c
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-1.c
new file mode 100644
index 00000000000..f5599339a36
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_u16mf4(vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf4(op1,vl);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_u16mf2(vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf2(op1,vl);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_u16m1(vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m1(op1,vl);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_u16m2(vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m2(op1,vl);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_u16m4(vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m4(op1,vl);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_u16m8(vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m8(op1,vl);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_u32mf2(vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32mf2(op1,vl);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_u32m1(vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m1(op1,vl);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_u32m2(vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m2(op1,vl);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_u32m4(vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m4(op1,vl);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_u32m8(vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m8(op1,vl);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_u64m1(vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m1(op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_u64m2(vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m2(op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_u64m4(vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m4(op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_u64m8(vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m8(op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-2.c
new file mode 100644
index 00000000000..553fff747ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_u16mf4(vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf4(op1,31);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_u16mf2(vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf2(op1,31);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_u16m1(vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m1(op1,31);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_u16m2(vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m2(op1,31);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_u16m4(vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m4(op1,31);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_u16m8(vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m8(op1,31);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_u32mf2(vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32mf2(op1,31);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_u32m1(vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m1(op1,31);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_u32m2(vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m2(op1,31);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_u32m4(vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m4(op1,31);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_u32m8(vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m8(op1,31);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_u64m1(vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m1(op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_u64m2(vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m2(op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_u64m4(vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m4(op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_u64m8(vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m8(op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-3.c
new file mode 100644
index 00000000000..b16a0993d4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_u16mf4(vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf4(op1,32);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_u16mf2(vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf2(op1,32);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_u16m1(vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m1(op1,32);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_u16m2(vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m2(op1,32);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_u16m4(vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m4(op1,32);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_u16m8(vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m8(op1,32);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_u32mf2(vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32mf2(op1,32);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_u32m1(vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m1(op1,32);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_u32m2(vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m2(op1,32);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_u32m4(vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m4(op1,32);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_u32m8(vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m8(op1,32);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_u64m1(vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m1(op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_u64m2(vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m2(op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_u64m4(vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m4(op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_u64m8(vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m8(op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_m-1.c
new file mode 100644
index 00000000000..c673e99b399
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_m-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_u16mf4_m(vbool64_t mask,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf4_m(mask,op1,vl);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_u16mf2_m(vbool32_t mask,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf2_m(mask,op1,vl);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_u16m1_m(vbool16_t mask,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m1_m(mask,op1,vl);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_u16m2_m(vbool8_t mask,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m2_m(mask,op1,vl);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_u16m4_m(vbool4_t mask,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m4_m(mask,op1,vl);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_u16m8_m(vbool2_t mask,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m8_m(mask,op1,vl);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_u32mf2_m(vbool64_t mask,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32mf2_m(mask,op1,vl);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_u32m1_m(vbool32_t mask,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m1_m(mask,op1,vl);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_u32m2_m(vbool16_t mask,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m2_m(mask,op1,vl);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_u32m4_m(vbool8_t mask,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m4_m(mask,op1,vl);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_u32m8_m(vbool4_t mask,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m8_m(mask,op1,vl);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_u64m1_m(vbool64_t mask,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m1_m(mask,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_u64m2_m(vbool32_t mask,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m2_m(mask,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_u64m4_m(vbool16_t mask,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m4_m(mask,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_u64m8_m(vbool8_t mask,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m8_m(mask,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_m-2.c
new file mode 100644
index 00000000000..61929878817
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_m-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_u16mf4_m(vbool64_t mask,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf4_m(mask,op1,31);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_u16mf2_m(vbool32_t mask,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf2_m(mask,op1,31);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_u16m1_m(vbool16_t mask,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m1_m(mask,op1,31);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_u16m2_m(vbool8_t mask,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m2_m(mask,op1,31);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_u16m4_m(vbool4_t mask,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m4_m(mask,op1,31);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_u16m8_m(vbool2_t mask,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m8_m(mask,op1,31);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_u32mf2_m(vbool64_t mask,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32mf2_m(mask,op1,31);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_u32m1_m(vbool32_t mask,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m1_m(mask,op1,31);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_u32m2_m(vbool16_t mask,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m2_m(mask,op1,31);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_u32m4_m(vbool8_t mask,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m4_m(mask,op1,31);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_u32m8_m(vbool4_t mask,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m8_m(mask,op1,31);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_u64m1_m(vbool64_t mask,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m1_m(mask,op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_u64m2_m(vbool32_t mask,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m2_m(mask,op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_u64m4_m(vbool16_t mask,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m4_m(mask,op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_u64m8_m(vbool8_t mask,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m8_m(mask,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_m-3.c
new file mode 100644
index 00000000000..894ae75cd37
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_m-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_u16mf4_m(vbool64_t mask,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf4_m(mask,op1,32);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_u16mf2_m(vbool32_t mask,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf2_m(mask,op1,32);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_u16m1_m(vbool16_t mask,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m1_m(mask,op1,32);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_u16m2_m(vbool8_t mask,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m2_m(mask,op1,32);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_u16m4_m(vbool4_t mask,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m4_m(mask,op1,32);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_u16m8_m(vbool2_t mask,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m8_m(mask,op1,32);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_u32mf2_m(vbool64_t mask,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32mf2_m(mask,op1,32);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_u32m1_m(vbool32_t mask,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m1_m(mask,op1,32);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_u32m2_m(vbool16_t mask,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m2_m(mask,op1,32);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_u32m4_m(vbool8_t mask,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m4_m(mask,op1,32);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_u32m8_m(vbool4_t mask,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m8_m(mask,op1,32);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_u64m1_m(vbool64_t mask,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m1_m(mask,op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_u64m2_m(vbool32_t mask,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m2_m(mask,op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_u64m4_m(vbool16_t mask,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m4_m(mask,op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_u64m8_m(vbool8_t mask,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m8_m(mask,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_mu-1.c
new file mode 100644
index 00000000000..08dba6aefb6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_mu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf4_mu(mask,merge,op1,vl);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf2_mu(mask,merge,op1,vl);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m1_mu(mask,merge,op1,vl);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m2_mu(mask,merge,op1,vl);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m4_mu(mask,merge,op1,vl);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m8_mu(mask,merge,op1,vl);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32mf2_mu(mask,merge,op1,vl);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m1_mu(mask,merge,op1,vl);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m2_mu(mask,merge,op1,vl);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m4_mu(mask,merge,op1,vl);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m8_mu(mask,merge,op1,vl);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m1_mu(mask,merge,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m2_mu(mask,merge,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m4_mu(mask,merge,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m8_mu(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_mu-2.c
new file mode 100644
index 00000000000..a82818857e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_mu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf4_mu(mask,merge,op1,31);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf2_mu(mask,merge,op1,31);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m1_mu(mask,merge,op1,31);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m2_mu(mask,merge,op1,31);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m4_mu(mask,merge,op1,31);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m8_mu(mask,merge,op1,31);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32mf2_mu(mask,merge,op1,31);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m1_mu(mask,merge,op1,31);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m2_mu(mask,merge,op1,31);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m4_mu(mask,merge,op1,31);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m8_mu(mask,merge,op1,31);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m1_mu(mask,merge,op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m2_mu(mask,merge,op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m4_mu(mask,merge,op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m8_mu(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_mu-3.c
new file mode 100644
index 00000000000..282d24db4c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_mu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf4_mu(mask,merge,op1,32);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf2_mu(mask,merge,op1,32);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m1_mu(mask,merge,op1,32);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m2_mu(mask,merge,op1,32);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m4_mu(mask,merge,op1,32);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m8_mu(mask,merge,op1,32);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32mf2_mu(mask,merge,op1,32);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m1_mu(mask,merge,op1,32);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m2_mu(mask,merge,op1,32);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m4_mu(mask,merge,op1,32);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m8_mu(mask,merge,op1,32);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m1_mu(mask,merge,op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m2_mu(mask,merge,op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m4_mu(mask,merge,op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m8_mu(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tu-1.c
new file mode 100644
index 00000000000..4f3110367d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf4_tu(merge,op1,vl);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf2_tu(merge,op1,vl);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_u16m1_tu(vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m1_tu(merge,op1,vl);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_u16m2_tu(vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m2_tu(merge,op1,vl);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_u16m4_tu(vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m4_tu(merge,op1,vl);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_u16m8_tu(vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m8_tu(merge,op1,vl);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32mf2_tu(merge,op1,vl);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_u32m1_tu(vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m1_tu(merge,op1,vl);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_u32m2_tu(vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m2_tu(merge,op1,vl);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_u32m4_tu(vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m4_tu(merge,op1,vl);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_u32m8_tu(vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m8_tu(merge,op1,vl);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_u64m1_tu(vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m1_tu(merge,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_u64m2_tu(vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m2_tu(merge,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_u64m4_tu(vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m4_tu(merge,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_u64m8_tu(vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m8_tu(merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tu-2.c
new file mode 100644
index 00000000000..c8df7e031f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf4_tu(merge,op1,31);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf2_tu(merge,op1,31);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_u16m1_tu(vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m1_tu(merge,op1,31);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_u16m2_tu(vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m2_tu(merge,op1,31);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_u16m4_tu(vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m4_tu(merge,op1,31);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_u16m8_tu(vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m8_tu(merge,op1,31);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32mf2_tu(merge,op1,31);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_u32m1_tu(vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m1_tu(merge,op1,31);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_u32m2_tu(vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m2_tu(merge,op1,31);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_u32m4_tu(vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m4_tu(merge,op1,31);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_u32m8_tu(vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m8_tu(merge,op1,31);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_u64m1_tu(vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m1_tu(merge,op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_u64m2_tu(vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m2_tu(merge,op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_u64m4_tu(vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m4_tu(merge,op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_u64m8_tu(vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m8_tu(merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tu-3.c
new file mode 100644
index 00000000000..da7fce19957
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf4_tu(merge,op1,32);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf2_tu(merge,op1,32);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_u16m1_tu(vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m1_tu(merge,op1,32);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_u16m2_tu(vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m2_tu(merge,op1,32);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_u16m4_tu(vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m4_tu(merge,op1,32);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_u16m8_tu(vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m8_tu(merge,op1,32);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32mf2_tu(merge,op1,32);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_u32m1_tu(vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m1_tu(merge,op1,32);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_u32m2_tu(vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m2_tu(merge,op1,32);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_u32m4_tu(vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m4_tu(merge,op1,32);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_u32m8_tu(vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m8_tu(merge,op1,32);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_u64m1_tu(vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m1_tu(merge,op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_u64m2_tu(vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m2_tu(merge,op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_u64m4_tu(vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m4_tu(merge,op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_u64m8_tu(vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m8_tu(merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tum-1.c
new file mode 100644
index 00000000000..f3016077596
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tum-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf4_tum(mask,merge,op1,vl);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf2_tum(mask,merge,op1,vl);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m1_tum(mask,merge,op1,vl);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m2_tum(mask,merge,op1,vl);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m4_tum(mask,merge,op1,vl);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m8_tum(mask,merge,op1,vl);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32mf2_tum(mask,merge,op1,vl);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m1_tum(mask,merge,op1,vl);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m2_tum(mask,merge,op1,vl);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m4_tum(mask,merge,op1,vl);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m8_tum(mask,merge,op1,vl);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m1_tum(mask,merge,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m2_tum(mask,merge,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m4_tum(mask,merge,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m8_tum(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tum-2.c
new file mode 100644
index 00000000000..879f9a63f72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tum-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf4_tum(mask,merge,op1,31);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf2_tum(mask,merge,op1,31);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m1_tum(mask,merge,op1,31);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m2_tum(mask,merge,op1,31);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m4_tum(mask,merge,op1,31);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m8_tum(mask,merge,op1,31);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32mf2_tum(mask,merge,op1,31);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m1_tum(mask,merge,op1,31);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m2_tum(mask,merge,op1,31);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m4_tum(mask,merge,op1,31);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m8_tum(mask,merge,op1,31);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m1_tum(mask,merge,op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m2_tum(mask,merge,op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m4_tum(mask,merge,op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m8_tum(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tum-3.c
new file mode 100644
index 00000000000..5e1de50787f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tum-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf4_tum(mask,merge,op1,32);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf2_tum(mask,merge,op1,32);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m1_tum(mask,merge,op1,32);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m2_tum(mask,merge,op1,32);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m4_tum(mask,merge,op1,32);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m8_tum(mask,merge,op1,32);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32mf2_tum(mask,merge,op1,32);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m1_tum(mask,merge,op1,32);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m2_tum(mask,merge,op1,32);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m4_tum(mask,merge,op1,32);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m8_tum(mask,merge,op1,32);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m1_tum(mask,merge,op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m2_tum(mask,merge,op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m4_tum(mask,merge,op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m8_tum(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tumu-1.c
new file mode 100644
index 00000000000..4c8c38e0d1d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tumu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf4_tumu(mask,merge,op1,vl);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf2_tumu(mask,merge,op1,vl);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m1_tumu(mask,merge,op1,vl);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m2_tumu(mask,merge,op1,vl);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m4_tumu(mask,merge,op1,vl);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m8_tumu(mask,merge,op1,vl);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32mf2_tumu(mask,merge,op1,vl);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m1_tumu(mask,merge,op1,vl);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m2_tumu(mask,merge,op1,vl);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m4_tumu(mask,merge,op1,vl);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m8_tumu(mask,merge,op1,vl);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m1_tumu(mask,merge,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m2_tumu(mask,merge,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m4_tumu(mask,merge,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m8_tumu(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tumu-2.c
new file mode 100644
index 00000000000..62b7d2b2b10
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tumu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf4_tumu(mask,merge,op1,31);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf2_tumu(mask,merge,op1,31);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m1_tumu(mask,merge,op1,31);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m2_tumu(mask,merge,op1,31);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m4_tumu(mask,merge,op1,31);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m8_tumu(mask,merge,op1,31);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32mf2_tumu(mask,merge,op1,31);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m1_tumu(mask,merge,op1,31);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m2_tumu(mask,merge,op1,31);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m4_tumu(mask,merge,op1,31);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m8_tumu(mask,merge,op1,31);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m1_tumu(mask,merge,op1,31);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m2_tumu(mask,merge,op1,31);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m4_tumu(mask,merge,op1,31);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m8_tumu(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tumu-3.c
new file mode 100644
index 00000000000..be0b074e2d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tumu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf4_tumu(mask,merge,op1,32);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16mf2_tumu(mask,merge,op1,32);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m1_tumu(mask,merge,op1,32);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m2_tumu(mask,merge,op1,32);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m4_tumu(mask,merge,op1,32);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u16m8_tumu(mask,merge,op1,32);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32mf2_tumu(mask,merge,op1,32);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m1_tumu(mask,merge,op1,32);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m2_tumu(mask,merge,op1,32);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m4_tumu(mask,merge,op1,32);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u32m8_tumu(mask,merge,op1,32);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m1_tumu(mask,merge,op1,32);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m2_tumu(mask,merge,op1,32);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf2_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m4_tumu(mask,merge,op1,32);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf2_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl)
+{
+    return __riscv_vzext_vf2_u64m8_tumu(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */