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From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vzext.vf4 C API tests Date: Mon, 6 Feb 2023 13:09:49 +0800 Message-Id: <20230206050949.215140-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757057101590158808?= X-GMAIL-MSGID: =?utf-8?q?1757057101590158808?= From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vzext_vf4-1.c: New test. * gcc.target/riscv/rvv/base/vzext_vf4-2.c: New test. * gcc.target/riscv/rvv/base/vzext_vf4-3.c: New test. * gcc.target/riscv/rvv/base/vzext_vf4_m-1.c: New test. * gcc.target/riscv/rvv/base/vzext_vf4_m-2.c: New test. * gcc.target/riscv/rvv/base/vzext_vf4_m-3.c: New test. * gcc.target/riscv/rvv/base/vzext_vf4_mu-1.c: New test. * gcc.target/riscv/rvv/base/vzext_vf4_mu-2.c: New test. * gcc.target/riscv/rvv/base/vzext_vf4_mu-3.c: New test. * gcc.target/riscv/rvv/base/vzext_vf4_tu-1.c: New test. * gcc.target/riscv/rvv/base/vzext_vf4_tu-2.c: New test. * gcc.target/riscv/rvv/base/vzext_vf4_tu-3.c: New test. * gcc.target/riscv/rvv/base/vzext_vf4_tum-1.c: New test. * gcc.target/riscv/rvv/base/vzext_vf4_tum-2.c: New test. * gcc.target/riscv/rvv/base/vzext_vf4_tum-3.c: New test. * gcc.target/riscv/rvv/base/vzext_vf4_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vzext_vf4_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vzext_vf4_tumu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vzext_vf4-1.c | 69 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf4-2.c | 69 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf4-3.c | 69 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf4_m-1.c | 69 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf4_m-2.c | 69 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf4_m-3.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf4_mu-1.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf4_mu-2.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf4_mu-3.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf4_tu-1.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf4_tu-2.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf4_tu-3.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf4_tum-1.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf4_tum-2.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf4_tum-3.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf4_tumu-1.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf4_tumu-2.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf4_tumu-3.c | 69 +++++++++++++++++++ 18 files changed, 1242 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tumu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-1.c new file mode 100644 index 00000000000..43df7caf4e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_u32mf2(vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32mf2(op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf4_u32m1(vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m1(op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf4_u32m2(vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m2(op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf4_u32m4(vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m4(op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf4_u32m8(vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m8(op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf4_u64m1(vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m1(op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf4_u64m2(vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m2(op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf4_u64m4(vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m4(op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf4_u64m8(vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m8(op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-2.c new file mode 100644 index 00000000000..d85f1f7edd0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-2.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_u32mf2(vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32mf2(op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf4_u32m1(vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m1(op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf4_u32m2(vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m2(op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf4_u32m4(vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m4(op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf4_u32m8(vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m8(op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf4_u64m1(vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m1(op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf4_u64m2(vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m2(op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf4_u64m4(vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m4(op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf4_u64m8(vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m8(op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-3.c new file mode 100644 index 00000000000..a3f625d36a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-3.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_u32mf2(vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32mf2(op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf4_u32m1(vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m1(op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf4_u32m2(vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m2(op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf4_u32m4(vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m4(op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf4_u32m8(vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m8(op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf4_u64m1(vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m1(op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf4_u64m2(vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m2(op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf4_u64m4(vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m4(op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf4_u64m8(vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m8(op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_m-1.c new file mode 100644 index 00000000000..fbcb776d705 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_m-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_u32mf2_m(vbool64_t mask,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32mf2_m(mask,op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf4_u32m1_m(vbool32_t mask,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m1_m(mask,op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf4_u32m2_m(vbool16_t mask,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m2_m(mask,op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf4_u32m4_m(vbool8_t mask,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m4_m(mask,op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf4_u32m8_m(vbool4_t mask,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m8_m(mask,op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf4_u64m1_m(vbool64_t mask,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m1_m(mask,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf4_u64m2_m(vbool32_t mask,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m2_m(mask,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf4_u64m4_m(vbool16_t mask,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m4_m(mask,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf4_u64m8_m(vbool8_t mask,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m8_m(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_m-2.c new file mode 100644 index 00000000000..cbe8d01ba9c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_m-2.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_u32mf2_m(vbool64_t mask,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32mf2_m(mask,op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf4_u32m1_m(vbool32_t mask,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m1_m(mask,op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf4_u32m2_m(vbool16_t mask,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m2_m(mask,op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf4_u32m4_m(vbool8_t mask,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m4_m(mask,op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf4_u32m8_m(vbool4_t mask,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m8_m(mask,op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf4_u64m1_m(vbool64_t mask,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m1_m(mask,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf4_u64m2_m(vbool32_t mask,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m2_m(mask,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf4_u64m4_m(vbool16_t mask,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m4_m(mask,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf4_u64m8_m(vbool8_t mask,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m8_m(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_m-3.c new file mode 100644 index 00000000000..47038d25bb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_m-3.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_u32mf2_m(vbool64_t mask,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32mf2_m(mask,op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf4_u32m1_m(vbool32_t mask,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m1_m(mask,op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf4_u32m2_m(vbool16_t mask,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m2_m(mask,op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf4_u32m4_m(vbool8_t mask,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m4_m(mask,op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf4_u32m8_m(vbool4_t mask,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m8_m(mask,op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf4_u64m1_m(vbool64_t mask,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m1_m(mask,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf4_u64m2_m(vbool32_t mask,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m2_m(mask,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf4_u64m4_m(vbool16_t mask,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m4_m(mask,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf4_u64m8_m(vbool8_t mask,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m8_m(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_mu-1.c new file mode 100644 index 00000000000..14b162f39bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_mu-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32mf2_mu(mask,merge,op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf4_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m1_mu(mask,merge,op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf4_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m2_mu(mask,merge,op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf4_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m4_mu(mask,merge,op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf4_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m8_mu(mask,merge,op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf4_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m1_mu(mask,merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf4_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m2_mu(mask,merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf4_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m4_mu(mask,merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf4_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m8_mu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_mu-2.c new file mode 100644 index 00000000000..b6437665cb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_mu-2.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32mf2_mu(mask,merge,op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf4_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m1_mu(mask,merge,op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf4_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m2_mu(mask,merge,op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf4_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m4_mu(mask,merge,op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf4_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m8_mu(mask,merge,op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf4_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m1_mu(mask,merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf4_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m2_mu(mask,merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf4_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m4_mu(mask,merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf4_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m8_mu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_mu-3.c new file mode 100644 index 00000000000..a83ab6f1af1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_mu-3.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32mf2_mu(mask,merge,op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf4_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m1_mu(mask,merge,op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf4_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m2_mu(mask,merge,op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf4_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m4_mu(mask,merge,op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf4_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m8_mu(mask,merge,op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf4_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m1_mu(mask,merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf4_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m2_mu(mask,merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf4_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m4_mu(mask,merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf4_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m8_mu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tu-1.c new file mode 100644 index 00000000000..ff76d422965 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tu-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_u32mf2_tu(vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32mf2_tu(merge,op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf4_u32m1_tu(vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m1_tu(merge,op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf4_u32m2_tu(vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m2_tu(merge,op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf4_u32m4_tu(vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m4_tu(merge,op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf4_u32m8_tu(vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m8_tu(merge,op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf4_u64m1_tu(vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m1_tu(merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf4_u64m2_tu(vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m2_tu(merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf4_u64m4_tu(vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m4_tu(merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf4_u64m8_tu(vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m8_tu(merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tu-2.c new file mode 100644 index 00000000000..553e3c7dfe7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tu-2.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_u32mf2_tu(vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32mf2_tu(merge,op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf4_u32m1_tu(vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m1_tu(merge,op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf4_u32m2_tu(vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m2_tu(merge,op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf4_u32m4_tu(vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m4_tu(merge,op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf4_u32m8_tu(vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m8_tu(merge,op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf4_u64m1_tu(vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m1_tu(merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf4_u64m2_tu(vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m2_tu(merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf4_u64m4_tu(vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m4_tu(merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf4_u64m8_tu(vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m8_tu(merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tu-3.c new file mode 100644 index 00000000000..276deda7d6a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tu-3.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_u32mf2_tu(vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32mf2_tu(merge,op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf4_u32m1_tu(vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m1_tu(merge,op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf4_u32m2_tu(vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m2_tu(merge,op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf4_u32m4_tu(vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m4_tu(merge,op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf4_u32m8_tu(vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m8_tu(merge,op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf4_u64m1_tu(vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m1_tu(merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf4_u64m2_tu(vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m2_tu(merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf4_u64m4_tu(vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m4_tu(merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf4_u64m8_tu(vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m8_tu(merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tum-1.c new file mode 100644 index 00000000000..9ab4183fe4e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tum-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32mf2_tum(mask,merge,op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf4_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m1_tum(mask,merge,op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf4_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m2_tum(mask,merge,op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf4_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m4_tum(mask,merge,op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf4_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m8_tum(mask,merge,op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf4_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m1_tum(mask,merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf4_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m2_tum(mask,merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf4_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m4_tum(mask,merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf4_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m8_tum(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tum-2.c new file mode 100644 index 00000000000..2e87d459d11 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tum-2.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32mf2_tum(mask,merge,op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf4_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m1_tum(mask,merge,op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf4_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m2_tum(mask,merge,op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf4_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m4_tum(mask,merge,op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf4_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m8_tum(mask,merge,op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf4_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m1_tum(mask,merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf4_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m2_tum(mask,merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf4_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m4_tum(mask,merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf4_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m8_tum(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tum-3.c new file mode 100644 index 00000000000..ba724b97e04 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tum-3.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32mf2_tum(mask,merge,op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf4_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m1_tum(mask,merge,op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf4_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m2_tum(mask,merge,op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf4_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m4_tum(mask,merge,op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf4_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m8_tum(mask,merge,op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf4_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m1_tum(mask,merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf4_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m2_tum(mask,merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf4_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m4_tum(mask,merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf4_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m8_tum(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tumu-1.c new file mode 100644 index 00000000000..656c63d72fa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tumu-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32mf2_tumu(mask,merge,op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf4_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m1_tumu(mask,merge,op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf4_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m2_tumu(mask,merge,op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf4_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m4_tumu(mask,merge,op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf4_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m8_tumu(mask,merge,op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf4_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m1_tumu(mask,merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf4_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m2_tumu(mask,merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf4_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m4_tumu(mask,merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf4_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m8_tumu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tumu-2.c new file mode 100644 index 00000000000..8fb7ed34ba1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tumu-2.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32mf2_tumu(mask,merge,op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf4_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m1_tumu(mask,merge,op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf4_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m2_tumu(mask,merge,op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf4_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m4_tumu(mask,merge,op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf4_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m8_tumu(mask,merge,op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf4_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m1_tumu(mask,merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf4_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m2_tumu(mask,merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf4_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m4_tumu(mask,merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf4_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m8_tumu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tumu-3.c new file mode 100644 index 00000000000..c5e8f721fee --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tumu-3.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32mf2_tumu(mask,merge,op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf4_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m1_tumu(mask,merge,op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf4_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m2_tumu(mask,merge,op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf4_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m4_tumu(mask,merge,op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf4_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u32m8_tumu(mask,merge,op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf4_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m1_tumu(mask,merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf4_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m2_tumu(mask,merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf4_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m4_tumu(mask,merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf4_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_u64m8_tumu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */