diff mbox series

RISC-V: Add vssubu.vx C++ API tests

Message ID 20230205082455.180453-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Add vssubu.vx C++ API tests |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai Feb. 5, 2023, 8:24 a.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-3.C: New test.

---
 .../riscv/rvv/base/vssubu_vx_mu_rv32-1.C      | 157 +++++++++
 .../riscv/rvv/base/vssubu_vx_mu_rv32-2.C      | 157 +++++++++
 .../riscv/rvv/base/vssubu_vx_mu_rv32-3.C      | 157 +++++++++
 .../riscv/rvv/base/vssubu_vx_mu_rv64-1.C      | 160 +++++++++
 .../riscv/rvv/base/vssubu_vx_mu_rv64-2.C      | 160 +++++++++
 .../riscv/rvv/base/vssubu_vx_mu_rv64-3.C      | 160 +++++++++
 .../riscv/rvv/base/vssubu_vx_rv32-1.C         | 308 +++++++++++++++++
 .../riscv/rvv/base/vssubu_vx_rv32-2.C         | 308 +++++++++++++++++
 .../riscv/rvv/base/vssubu_vx_rv32-3.C         | 308 +++++++++++++++++
 .../riscv/rvv/base/vssubu_vx_rv64-1.C         | 314 ++++++++++++++++++
 .../riscv/rvv/base/vssubu_vx_rv64-2.C         | 314 ++++++++++++++++++
 .../riscv/rvv/base/vssubu_vx_rv64-3.C         | 314 ++++++++++++++++++
 .../riscv/rvv/base/vssubu_vx_tu_rv32-1.C      | 157 +++++++++
 .../riscv/rvv/base/vssubu_vx_tu_rv32-2.C      | 157 +++++++++
 .../riscv/rvv/base/vssubu_vx_tu_rv32-3.C      | 157 +++++++++
 .../riscv/rvv/base/vssubu_vx_tu_rv64-1.C      | 160 +++++++++
 .../riscv/rvv/base/vssubu_vx_tu_rv64-2.C      | 160 +++++++++
 .../riscv/rvv/base/vssubu_vx_tu_rv64-3.C      | 160 +++++++++
 .../riscv/rvv/base/vssubu_vx_tum_rv32-1.C     | 157 +++++++++
 .../riscv/rvv/base/vssubu_vx_tum_rv32-2.C     | 157 +++++++++
 .../riscv/rvv/base/vssubu_vx_tum_rv32-3.C     | 157 +++++++++
 .../riscv/rvv/base/vssubu_vx_tum_rv64-1.C     | 160 +++++++++
 .../riscv/rvv/base/vssubu_vx_tum_rv64-2.C     | 160 +++++++++
 .../riscv/rvv/base/vssubu_vx_tum_rv64-3.C     | 160 +++++++++
 .../riscv/rvv/base/vssubu_vx_tumu_rv32-1.C    | 157 +++++++++
 .../riscv/rvv/base/vssubu_vx_tumu_rv32-2.C    | 157 +++++++++
 .../riscv/rvv/base/vssubu_vx_tumu_rv32-3.C    | 157 +++++++++
 .../riscv/rvv/base/vssubu_vx_tumu_rv64-1.C    | 160 +++++++++
 .../riscv/rvv/base/vssubu_vx_tumu_rv64-2.C    | 160 +++++++++
 .../riscv/rvv/base/vssubu_vx_tumu_rv64-3.C    | 160 +++++++++
 30 files changed, 5670 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-3.C
diff mbox series

Patch

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-1.C
new file mode 100644
index 00000000000..c1169bbda0f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-1.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vssubu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vssubu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vssubu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vssubu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vssubu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vssubu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vssubu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vssubu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vssubu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vssubu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vssubu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vssubu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vssubu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vssubu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vssubu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vssubu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-2.C
new file mode 100644
index 00000000000..aebe4f156ac
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-2.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vssubu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vssubu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vssubu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vssubu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vssubu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vssubu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vssubu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vssubu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vssubu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vssubu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vssubu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vssubu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vssubu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vssubu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vssubu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vssubu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-3.C
new file mode 100644
index 00000000000..b9c1851d66c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-3.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vssubu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vssubu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vssubu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vssubu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vssubu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vssubu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vssubu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vssubu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vssubu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vssubu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vssubu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vssubu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vssubu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vssubu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vssubu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vssubu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-1.C
new file mode 100644
index 00000000000..89300417f81
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vssubu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vssubu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vssubu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vssubu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vssubu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vssubu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vssubu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vssubu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vssubu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vssubu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vssubu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vssubu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vssubu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vssubu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vssubu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vssubu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-2.C
new file mode 100644
index 00000000000..e493696176e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vssubu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vssubu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vssubu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vssubu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vssubu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vssubu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vssubu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vssubu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vssubu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vssubu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vssubu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vssubu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vssubu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vssubu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vssubu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vssubu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-3.C
new file mode 100644
index 00000000000..4ddfc6aab2c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vssubu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vssubu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vssubu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vssubu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vssubu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vssubu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vssubu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vssubu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vssubu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vssubu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vssubu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vssubu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vssubu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vssubu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vssubu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vssubu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv32-1.C
new file mode 100644
index 00000000000..f7acaa01f4b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv32-1.C
@@ -0,0 +1,308 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vssubu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vssubu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vssubu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vssubu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vssubu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vssubu(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vssubu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vssubu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vssubu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vssubu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vssubu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vssubu(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vssubu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vssubu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vssubu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vssubu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vssubu(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vssubu(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vssubu(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vssubu(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vssubu(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vssubu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vssubu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vssubu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vssubu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vssubu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vssubu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vssubu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vssubu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vssubu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vssubu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vssubu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vssubu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vssubu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vssubu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vssubu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vssubu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vssubu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vssubu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vssubu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vssubu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vssubu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vssubu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv32-2.C
new file mode 100644
index 00000000000..96f4960bbb1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv32-2.C
@@ -0,0 +1,308 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vssubu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vssubu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vssubu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vssubu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vssubu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vssubu(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vssubu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vssubu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vssubu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vssubu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vssubu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vssubu(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vssubu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vssubu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vssubu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vssubu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vssubu(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vssubu(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vssubu(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vssubu(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vssubu(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vssubu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vssubu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vssubu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vssubu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vssubu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vssubu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vssubu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vssubu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vssubu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vssubu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vssubu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vssubu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vssubu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vssubu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vssubu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vssubu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vssubu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vssubu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vssubu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vssubu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vssubu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vssubu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv32-3.C
new file mode 100644
index 00000000000..3e251a90f04
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv32-3.C
@@ -0,0 +1,308 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vssubu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vssubu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vssubu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vssubu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vssubu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vssubu(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vssubu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vssubu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vssubu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vssubu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vssubu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vssubu(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vssubu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vssubu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vssubu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vssubu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vssubu(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vssubu(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vssubu(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vssubu(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vssubu(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vssubu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vssubu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vssubu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vssubu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vssubu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vssubu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vssubu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vssubu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vssubu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vssubu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vssubu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vssubu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vssubu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vssubu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vssubu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vssubu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vssubu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vssubu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vssubu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vssubu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vssubu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vssubu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv64-1.C
new file mode 100644
index 00000000000..a862c1fcd9b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv64-1.C
@@ -0,0 +1,314 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vssubu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vssubu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vssubu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vssubu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vssubu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vssubu(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vssubu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vssubu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vssubu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vssubu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vssubu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vssubu(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vssubu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vssubu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vssubu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vssubu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vssubu(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vssubu(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vssubu(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vssubu(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vssubu(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vssubu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vssubu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vssubu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vssubu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vssubu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vssubu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vssubu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vssubu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vssubu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vssubu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vssubu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vssubu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vssubu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vssubu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vssubu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vssubu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vssubu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vssubu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vssubu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vssubu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vssubu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vssubu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv64-2.C
new file mode 100644
index 00000000000..e05e30d0e92
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv64-2.C
@@ -0,0 +1,314 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vssubu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vssubu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vssubu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vssubu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vssubu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vssubu(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vssubu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vssubu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vssubu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vssubu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vssubu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vssubu(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vssubu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vssubu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vssubu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vssubu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vssubu(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vssubu(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vssubu(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vssubu(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vssubu(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vssubu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vssubu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vssubu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vssubu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vssubu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vssubu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vssubu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vssubu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vssubu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vssubu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vssubu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vssubu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vssubu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vssubu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vssubu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vssubu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vssubu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vssubu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vssubu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vssubu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vssubu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vssubu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv64-3.C
new file mode 100644
index 00000000000..75b9c407acc
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv64-3.C
@@ -0,0 +1,314 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vssubu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vssubu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vssubu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vssubu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vssubu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vssubu(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vssubu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vssubu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vssubu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vssubu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vssubu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vssubu(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vssubu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vssubu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vssubu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vssubu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vssubu(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vssubu(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vssubu(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vssubu(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vssubu(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vssubu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vssubu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vssubu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vssubu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vssubu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vssubu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vssubu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vssubu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vssubu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vssubu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vssubu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vssubu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vssubu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vssubu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vssubu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vssubu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vssubu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vssubu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vssubu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vssubu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vssubu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vssubu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-1.C
new file mode 100644
index 00000000000..4a33d9637c4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-1.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vssubu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vssubu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vssubu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vssubu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vssubu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vssubu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vssubu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vssubu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vssubu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vssubu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vssubu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vssubu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vssubu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vssubu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vssubu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vssubu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-2.C
new file mode 100644
index 00000000000..f97b5b11743
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-2.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vssubu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vssubu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vssubu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vssubu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vssubu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vssubu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vssubu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vssubu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vssubu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vssubu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vssubu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vssubu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vssubu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vssubu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vssubu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vssubu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-3.C
new file mode 100644
index 00000000000..b85250a9e79
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-3.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vssubu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vssubu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vssubu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vssubu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vssubu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vssubu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vssubu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vssubu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vssubu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vssubu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vssubu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vssubu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vssubu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vssubu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vssubu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vssubu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-1.C
new file mode 100644
index 00000000000..e29d3c050e6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vssubu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vssubu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vssubu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vssubu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vssubu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vssubu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vssubu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vssubu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vssubu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vssubu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vssubu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vssubu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vssubu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vssubu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vssubu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vssubu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-2.C
new file mode 100644
index 00000000000..db39e556188
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vssubu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vssubu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vssubu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vssubu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vssubu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vssubu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vssubu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vssubu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vssubu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vssubu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vssubu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vssubu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vssubu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vssubu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vssubu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vssubu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-3.C
new file mode 100644
index 00000000000..7db4cbaac28
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vssubu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vssubu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vssubu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vssubu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vssubu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vssubu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vssubu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vssubu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vssubu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vssubu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vssubu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vssubu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vssubu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vssubu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vssubu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vssubu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-1.C
new file mode 100644
index 00000000000..7e8f36b74fc
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-1.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vssubu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vssubu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vssubu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vssubu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vssubu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vssubu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vssubu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vssubu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vssubu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vssubu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vssubu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vssubu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vssubu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vssubu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vssubu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vssubu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-2.C
new file mode 100644
index 00000000000..5d035c2fb77
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-2.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vssubu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vssubu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vssubu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vssubu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vssubu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vssubu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vssubu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vssubu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vssubu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vssubu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vssubu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vssubu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vssubu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vssubu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vssubu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vssubu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-3.C
new file mode 100644
index 00000000000..1436549f4e0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-3.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vssubu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vssubu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vssubu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vssubu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vssubu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vssubu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vssubu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vssubu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vssubu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vssubu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vssubu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vssubu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vssubu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vssubu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vssubu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vssubu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-1.C
new file mode 100644
index 00000000000..5b8277715b1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vssubu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vssubu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vssubu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vssubu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vssubu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vssubu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vssubu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vssubu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vssubu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vssubu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vssubu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vssubu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vssubu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vssubu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vssubu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vssubu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-2.C
new file mode 100644
index 00000000000..6bb7ed47952
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vssubu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vssubu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vssubu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vssubu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vssubu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vssubu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vssubu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vssubu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vssubu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vssubu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vssubu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vssubu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vssubu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vssubu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vssubu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vssubu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-3.C
new file mode 100644
index 00000000000..4dae844ee19
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vssubu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vssubu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vssubu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vssubu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vssubu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vssubu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vssubu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vssubu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vssubu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vssubu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vssubu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vssubu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vssubu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vssubu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vssubu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vssubu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-1.C
new file mode 100644
index 00000000000..0da85c35b57
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-1.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vssubu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vssubu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vssubu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vssubu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vssubu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vssubu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vssubu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vssubu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vssubu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vssubu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vssubu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vssubu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vssubu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vssubu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vssubu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vssubu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-2.C
new file mode 100644
index 00000000000..a3800059e70
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-2.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vssubu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vssubu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vssubu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vssubu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vssubu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vssubu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vssubu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vssubu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vssubu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vssubu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vssubu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vssubu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vssubu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vssubu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vssubu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vssubu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-3.C
new file mode 100644
index 00000000000..dca6d9215c7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-3.C
@@ -0,0 +1,157 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vssubu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vssubu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vssubu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vssubu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vssubu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vssubu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vssubu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vssubu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vssubu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vssubu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vssubu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vssubu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vssubu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vssubu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vssubu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vssubu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-1.C
new file mode 100644
index 00000000000..acd11f6b9ce
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vssubu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vssubu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vssubu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vssubu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vssubu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vssubu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vssubu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vssubu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vssubu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vssubu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vssubu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vssubu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vssubu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vssubu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vssubu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vssubu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-2.C
new file mode 100644
index 00000000000..73223fb8e5e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vssubu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vssubu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vssubu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vssubu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vssubu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vssubu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vssubu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vssubu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vssubu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vssubu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vssubu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vssubu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vssubu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vssubu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vssubu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vssubu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-3.C
new file mode 100644
index 00000000000..500428f4559
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssubu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vssubu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vssubu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vssubu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vssubu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vssubu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vssubu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vssubu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vssubu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vssubu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vssubu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vssubu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vssubu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vssubu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vssubu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vssubu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vssubu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vssubu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vssubu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vssubu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vssubu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vssubu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vssubu_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */