diff mbox series

RISC-V: Fix VSETVL PASS bug in exception handling

Message ID 20230204010930.263271-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Fix VSETVL PASS bug in exception handling |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai Feb. 4, 2023, 1:09 a.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

        * config/riscv/riscv-vsetvl.cc (pass_vsetvl::compute_probabilities): Skip exit block.

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/exception-1.C: New test.

---
 gcc/config/riscv/riscv-vsetvl.cc              | 10 +++++--
 .../g++.target/riscv/rvv/base/exception-1.C   | 29 +++++++++++++++++++
 2 files changed, 36 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/exception-1.C
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index ef5b74c58d2..8e6063ae83b 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -3492,8 +3492,15 @@  pass_vsetvl::compute_probabilities (void)
       basic_block cfg_bb = bb->cfg_bb ();
       auto &curr_prob
 	= m_vector_manager->vector_block_infos[cfg_bb->index].probability;
+
+      /* GCC assume entry block (bb 0) are always so
+	 executed so set its probability as "always".  */
       if (ENTRY_BLOCK_PTR_FOR_FN (cfun) == cfg_bb)
 	curr_prob = profile_probability::always ();
+      /* Exit block (bb 1) is the block we don't need to process.  */
+      if (EXIT_BLOCK_PTR_FOR_FN (cfun) == cfg_bb)
+	continue;
+
       gcc_assert (curr_prob.initialized_p ());
       FOR_EACH_EDGE (e, ei, cfg_bb->succs)
 	{
@@ -3507,9 +3514,6 @@  pass_vsetvl::compute_probabilities (void)
 	    new_prob += curr_prob * e->probability;
 	}
     }
-  auto &exit_block
-    = m_vector_manager->vector_block_infos[EXIT_BLOCK_PTR_FOR_FN (cfun)->index];
-  exit_block.probability = profile_probability::always ();
 }
 
 /* Lazy vsetvl insertion for optimize > 0. */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/exception-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/exception-1.C
new file mode 100644
index 00000000000..5f5247bce46
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/exception-1.C
@@ -0,0 +1,29 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+
+#include <stdio.h>
+#include "riscv_vector.h"
+#include <stdexcept>
+void __attribute__((noinline)) foo(int arr[4]) {
+printf("%d %d %d %d\n", arr[0], arr[1], arr[2], arr[3]);
+}
+
+void __attribute__((noinline)) test() {
+// Intialization with 2 memsets leads to spilling of zero-splat value
+vint32m1_t a;
+int arr1[4] = {};
+foo(arr1);
+int arr2[4] = {};
+foo(arr2);
+asm volatile ("# %0" : "+vr" (a));
+throw int();
+}
+
+int main() {
+try {
+   test();
+} catch (...) {
+   printf("hello\n");
+};
+return 0;
+}