diff mbox series

RISC-V: Add vneg.v C++ API tests

Message ID	20230203232759.224994-1-juzhe.zhong@rivai.ai
State	Accepted
Headers	Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DCCE33858431 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong <juzhe.zhong@rivai.ai> Subject: [PATCH] RISC-V: Add vneg.v C++ API tests Date: Sat, 4 Feb 2023 07:27:59 +0800 Message-Id: <20230203232759.224994-1-juzhe.zhong@rivai.ai> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 Precedence: list Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org> X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?=
Series	RISC-V: Add vneg.v C++ API tests \| RISC-V: Add vneg.v C++ API tests

Checks

Context	Check	Description
snail/gcc-patch-check	success	Github commit url

Commit Message

juzhe.zhong@rivai.ai Feb. 3, 2023, 11:27 p.m. UTC

  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vneg_v-1.C: New test.
        * g++.target/riscv/rvv/base/vneg_v-2.C: New test.
        * g++.target/riscv/rvv/base/vneg_v-3.C: New test.
        * g++.target/riscv/rvv/base/vneg_v_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vneg_v_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vneg_v_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vneg_v_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vneg_v_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vneg_v_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vneg_v_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vneg_v_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vneg_v_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vneg_v_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vneg_v_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vneg_v_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vneg_v-1.C      | 314 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vneg_v-2.C      | 314 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vneg_v-3.C      | 314 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vneg_v_mu-1.C   | 160 +++++++++
 .../g++.target/riscv/rvv/base/vneg_v_mu-2.C   | 160 +++++++++
 .../g++.target/riscv/rvv/base/vneg_v_mu-3.C   | 160 +++++++++
 .../g++.target/riscv/rvv/base/vneg_v_tu-1.C   | 160 +++++++++
 .../g++.target/riscv/rvv/base/vneg_v_tu-2.C   | 160 +++++++++
 .../g++.target/riscv/rvv/base/vneg_v_tu-3.C   | 160 +++++++++
 .../g++.target/riscv/rvv/base/vneg_v_tum-1.C  | 160 +++++++++
 .../g++.target/riscv/rvv/base/vneg_v_tum-2.C  | 160 +++++++++
 .../g++.target/riscv/rvv/base/vneg_v_tum-3.C  | 160 +++++++++
 .../g++.target/riscv/rvv/base/vneg_v_tumu-1.C | 160 +++++++++
 .../g++.target/riscv/rvv/base/vneg_v_tumu-2.C | 160 +++++++++
 .../g++.target/riscv/rvv/base/vneg_v_tumu-3.C | 160 +++++++++
 15 files changed, 2862 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-3.C

diff mbox series

Patch

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-1.C
new file mode 100644
index 00000000000..2d135e0bc0d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-1.C
@@ -0,0 +1,314 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vneg(vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint8mf4_t test___riscv_vneg(vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint8mf2_t test___riscv_vneg(vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint8m1_t test___riscv_vneg(vint8m1_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint8m2_t test___riscv_vneg(vint8m2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint8m4_t test___riscv_vneg(vint8m4_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint8m8_t test___riscv_vneg(vint8m8_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint16mf4_t test___riscv_vneg(vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vneg(vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint16m1_t test___riscv_vneg(vint16m1_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint16m2_t test___riscv_vneg(vint16m2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint16m4_t test___riscv_vneg(vint16m4_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint16m8_t test___riscv_vneg(vint16m8_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vneg(vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint32m1_t test___riscv_vneg(vint32m1_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint32m2_t test___riscv_vneg(vint32m2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint32m4_t test___riscv_vneg(vint32m4_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint32m8_t test___riscv_vneg(vint32m8_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint64m1_t test___riscv_vneg(vint64m1_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint64m2_t test___riscv_vneg(vint64m2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint64m4_t test___riscv_vneg(vint64m4_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint64m8_t test___riscv_vneg(vint64m8_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,vl);
+}
+
+
+vint8mf8_t test___riscv_vneg(vbool64_t mask,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint8mf4_t test___riscv_vneg(vbool32_t mask,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint8mf2_t test___riscv_vneg(vbool16_t mask,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint8m1_t test___riscv_vneg(vbool8_t mask,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint8m2_t test___riscv_vneg(vbool4_t mask,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint8m4_t test___riscv_vneg(vbool2_t mask,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint8m8_t test___riscv_vneg(vbool1_t mask,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint16mf4_t test___riscv_vneg(vbool64_t mask,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vneg(vbool32_t mask,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint16m1_t test___riscv_vneg(vbool16_t mask,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint16m2_t test___riscv_vneg(vbool8_t mask,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint16m4_t test___riscv_vneg(vbool4_t mask,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint16m8_t test___riscv_vneg(vbool2_t mask,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vneg(vbool64_t mask,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint32m1_t test___riscv_vneg(vbool32_t mask,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint32m2_t test___riscv_vneg(vbool16_t mask,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint32m4_t test___riscv_vneg(vbool8_t mask,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint32m8_t test___riscv_vneg(vbool4_t mask,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint64m1_t test___riscv_vneg(vbool64_t mask,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint64m2_t test___riscv_vneg(vbool32_t mask,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint64m4_t test___riscv_vneg(vbool16_t mask,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+vint64m8_t test___riscv_vneg(vbool8_t mask,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-2.C
new file mode 100644
index 00000000000..97b9028a73d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-2.C
@@ -0,0 +1,314 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vneg(vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint8mf4_t test___riscv_vneg(vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint8mf2_t test___riscv_vneg(vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint8m1_t test___riscv_vneg(vint8m1_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint8m2_t test___riscv_vneg(vint8m2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint8m4_t test___riscv_vneg(vint8m4_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint8m8_t test___riscv_vneg(vint8m8_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint16mf4_t test___riscv_vneg(vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint16mf2_t test___riscv_vneg(vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint16m1_t test___riscv_vneg(vint16m1_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint16m2_t test___riscv_vneg(vint16m2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint16m4_t test___riscv_vneg(vint16m4_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint16m8_t test___riscv_vneg(vint16m8_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint32mf2_t test___riscv_vneg(vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint32m1_t test___riscv_vneg(vint32m1_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint32m2_t test___riscv_vneg(vint32m2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint32m4_t test___riscv_vneg(vint32m4_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint32m8_t test___riscv_vneg(vint32m8_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint64m1_t test___riscv_vneg(vint64m1_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint64m2_t test___riscv_vneg(vint64m2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint64m4_t test___riscv_vneg(vint64m4_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint64m8_t test___riscv_vneg(vint64m8_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,31);
+}
+
+
+vint8mf8_t test___riscv_vneg(vbool64_t mask,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint8mf4_t test___riscv_vneg(vbool32_t mask,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint8mf2_t test___riscv_vneg(vbool16_t mask,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint8m1_t test___riscv_vneg(vbool8_t mask,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint8m2_t test___riscv_vneg(vbool4_t mask,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint8m4_t test___riscv_vneg(vbool2_t mask,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint8m8_t test___riscv_vneg(vbool1_t mask,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint16mf4_t test___riscv_vneg(vbool64_t mask,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint16mf2_t test___riscv_vneg(vbool32_t mask,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint16m1_t test___riscv_vneg(vbool16_t mask,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint16m2_t test___riscv_vneg(vbool8_t mask,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint16m4_t test___riscv_vneg(vbool4_t mask,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint16m8_t test___riscv_vneg(vbool2_t mask,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint32mf2_t test___riscv_vneg(vbool64_t mask,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint32m1_t test___riscv_vneg(vbool32_t mask,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint32m2_t test___riscv_vneg(vbool16_t mask,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint32m4_t test___riscv_vneg(vbool8_t mask,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint32m8_t test___riscv_vneg(vbool4_t mask,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint64m1_t test___riscv_vneg(vbool64_t mask,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint64m2_t test___riscv_vneg(vbool32_t mask,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint64m4_t test___riscv_vneg(vbool16_t mask,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+vint64m8_t test___riscv_vneg(vbool8_t mask,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-3.C
new file mode 100644
index 00000000000..430792260a4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-3.C
@@ -0,0 +1,314 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vneg(vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint8mf4_t test___riscv_vneg(vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint8mf2_t test___riscv_vneg(vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint8m1_t test___riscv_vneg(vint8m1_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint8m2_t test___riscv_vneg(vint8m2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint8m4_t test___riscv_vneg(vint8m4_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint8m8_t test___riscv_vneg(vint8m8_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint16mf4_t test___riscv_vneg(vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint16mf2_t test___riscv_vneg(vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint16m1_t test___riscv_vneg(vint16m1_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint16m2_t test___riscv_vneg(vint16m2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint16m4_t test___riscv_vneg(vint16m4_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint16m8_t test___riscv_vneg(vint16m8_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint32mf2_t test___riscv_vneg(vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint32m1_t test___riscv_vneg(vint32m1_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint32m2_t test___riscv_vneg(vint32m2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint32m4_t test___riscv_vneg(vint32m4_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint32m8_t test___riscv_vneg(vint32m8_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint64m1_t test___riscv_vneg(vint64m1_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint64m2_t test___riscv_vneg(vint64m2_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint64m4_t test___riscv_vneg(vint64m4_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint64m8_t test___riscv_vneg(vint64m8_t op1,size_t vl)
+{
+    return __riscv_vneg(op1,32);
+}
+
+
+vint8mf8_t test___riscv_vneg(vbool64_t mask,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint8mf4_t test___riscv_vneg(vbool32_t mask,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint8mf2_t test___riscv_vneg(vbool16_t mask,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint8m1_t test___riscv_vneg(vbool8_t mask,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint8m2_t test___riscv_vneg(vbool4_t mask,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint8m4_t test___riscv_vneg(vbool2_t mask,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint8m8_t test___riscv_vneg(vbool1_t mask,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint16mf4_t test___riscv_vneg(vbool64_t mask,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint16mf2_t test___riscv_vneg(vbool32_t mask,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint16m1_t test___riscv_vneg(vbool16_t mask,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint16m2_t test___riscv_vneg(vbool8_t mask,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint16m4_t test___riscv_vneg(vbool4_t mask,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint16m8_t test___riscv_vneg(vbool2_t mask,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint32mf2_t test___riscv_vneg(vbool64_t mask,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint32m1_t test___riscv_vneg(vbool32_t mask,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint32m2_t test___riscv_vneg(vbool16_t mask,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint32m4_t test___riscv_vneg(vbool8_t mask,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint32m8_t test___riscv_vneg(vbool4_t mask,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint64m1_t test___riscv_vneg(vbool64_t mask,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint64m2_t test___riscv_vneg(vbool32_t mask,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint64m4_t test___riscv_vneg(vbool16_t mask,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+vint64m8_t test___riscv_vneg(vbool8_t mask,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vneg(mask,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-1.C
new file mode 100644
index 00000000000..aa56e052450
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vneg_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint8mf4_t test___riscv_vneg_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint8mf2_t test___riscv_vneg_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint8m1_t test___riscv_vneg_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint8m2_t test___riscv_vneg_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint8m4_t test___riscv_vneg_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint8m8_t test___riscv_vneg_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint16mf4_t test___riscv_vneg_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vneg_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint16m1_t test___riscv_vneg_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint16m2_t test___riscv_vneg_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint16m4_t test___riscv_vneg_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint16m8_t test___riscv_vneg_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vneg_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint32m1_t test___riscv_vneg_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint32m2_t test___riscv_vneg_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint32m4_t test___riscv_vneg_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint32m8_t test___riscv_vneg_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint64m1_t test___riscv_vneg_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint64m2_t test___riscv_vneg_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint64m4_t test___riscv_vneg_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+vint64m8_t test___riscv_vneg_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-2.C
new file mode 100644
index 00000000000..1161eb88503
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vneg_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint8mf4_t test___riscv_vneg_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint8mf2_t test___riscv_vneg_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint8m1_t test___riscv_vneg_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint8m2_t test___riscv_vneg_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint8m4_t test___riscv_vneg_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint8m8_t test___riscv_vneg_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint16mf4_t test___riscv_vneg_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint16mf2_t test___riscv_vneg_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint16m1_t test___riscv_vneg_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint16m2_t test___riscv_vneg_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint16m4_t test___riscv_vneg_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint16m8_t test___riscv_vneg_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint32mf2_t test___riscv_vneg_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint32m1_t test___riscv_vneg_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint32m2_t test___riscv_vneg_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint32m4_t test___riscv_vneg_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint32m8_t test___riscv_vneg_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint64m1_t test___riscv_vneg_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint64m2_t test___riscv_vneg_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint64m4_t test___riscv_vneg_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+vint64m8_t test___riscv_vneg_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-3.C
new file mode 100644
index 00000000000..f742d5c6592
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vneg_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint8mf4_t test___riscv_vneg_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint8mf2_t test___riscv_vneg_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint8m1_t test___riscv_vneg_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint8m2_t test___riscv_vneg_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint8m4_t test___riscv_vneg_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint8m8_t test___riscv_vneg_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint16mf4_t test___riscv_vneg_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint16mf2_t test___riscv_vneg_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint16m1_t test___riscv_vneg_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint16m2_t test___riscv_vneg_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint16m4_t test___riscv_vneg_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint16m8_t test___riscv_vneg_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint32mf2_t test___riscv_vneg_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint32m1_t test___riscv_vneg_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint32m2_t test___riscv_vneg_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint32m4_t test___riscv_vneg_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint32m8_t test___riscv_vneg_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint64m1_t test___riscv_vneg_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint64m2_t test___riscv_vneg_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint64m4_t test___riscv_vneg_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+vint64m8_t test___riscv_vneg_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vneg_mu(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-1.C
new file mode 100644
index 00000000000..46c50ea898f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vneg_tu(vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint8mf4_t test___riscv_vneg_tu(vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint8mf2_t test___riscv_vneg_tu(vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint8m1_t test___riscv_vneg_tu(vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint8m2_t test___riscv_vneg_tu(vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint8m4_t test___riscv_vneg_tu(vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint8m8_t test___riscv_vneg_tu(vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint16mf4_t test___riscv_vneg_tu(vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vneg_tu(vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint16m1_t test___riscv_vneg_tu(vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint16m2_t test___riscv_vneg_tu(vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint16m4_t test___riscv_vneg_tu(vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint16m8_t test___riscv_vneg_tu(vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vneg_tu(vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint32m1_t test___riscv_vneg_tu(vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint32m2_t test___riscv_vneg_tu(vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint32m4_t test___riscv_vneg_tu(vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint32m8_t test___riscv_vneg_tu(vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint64m1_t test___riscv_vneg_tu(vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint64m2_t test___riscv_vneg_tu(vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint64m4_t test___riscv_vneg_tu(vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+vint64m8_t test___riscv_vneg_tu(vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-2.C
new file mode 100644
index 00000000000..1b1181b131c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vneg_tu(vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint8mf4_t test___riscv_vneg_tu(vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint8mf2_t test___riscv_vneg_tu(vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint8m1_t test___riscv_vneg_tu(vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint8m2_t test___riscv_vneg_tu(vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint8m4_t test___riscv_vneg_tu(vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint8m8_t test___riscv_vneg_tu(vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint16mf4_t test___riscv_vneg_tu(vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint16mf2_t test___riscv_vneg_tu(vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint16m1_t test___riscv_vneg_tu(vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint16m2_t test___riscv_vneg_tu(vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint16m4_t test___riscv_vneg_tu(vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint16m8_t test___riscv_vneg_tu(vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint32mf2_t test___riscv_vneg_tu(vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint32m1_t test___riscv_vneg_tu(vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint32m2_t test___riscv_vneg_tu(vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint32m4_t test___riscv_vneg_tu(vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint32m8_t test___riscv_vneg_tu(vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint64m1_t test___riscv_vneg_tu(vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint64m2_t test___riscv_vneg_tu(vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint64m4_t test___riscv_vneg_tu(vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+vint64m8_t test___riscv_vneg_tu(vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-3.C
new file mode 100644
index 00000000000..bf392306725
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vneg_tu(vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint8mf4_t test___riscv_vneg_tu(vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint8mf2_t test___riscv_vneg_tu(vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint8m1_t test___riscv_vneg_tu(vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint8m2_t test___riscv_vneg_tu(vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint8m4_t test___riscv_vneg_tu(vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint8m8_t test___riscv_vneg_tu(vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint16mf4_t test___riscv_vneg_tu(vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint16mf2_t test___riscv_vneg_tu(vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint16m1_t test___riscv_vneg_tu(vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint16m2_t test___riscv_vneg_tu(vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint16m4_t test___riscv_vneg_tu(vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint16m8_t test___riscv_vneg_tu(vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint32mf2_t test___riscv_vneg_tu(vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint32m1_t test___riscv_vneg_tu(vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint32m2_t test___riscv_vneg_tu(vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint32m4_t test___riscv_vneg_tu(vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint32m8_t test___riscv_vneg_tu(vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint64m1_t test___riscv_vneg_tu(vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint64m2_t test___riscv_vneg_tu(vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint64m4_t test___riscv_vneg_tu(vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+vint64m8_t test___riscv_vneg_tu(vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tu(merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-1.C
new file mode 100644
index 00000000000..d1b55a56933
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vneg_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint8mf4_t test___riscv_vneg_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint8mf2_t test___riscv_vneg_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint8m1_t test___riscv_vneg_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint8m2_t test___riscv_vneg_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint8m4_t test___riscv_vneg_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint8m8_t test___riscv_vneg_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint16mf4_t test___riscv_vneg_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vneg_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint16m1_t test___riscv_vneg_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint16m2_t test___riscv_vneg_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint16m4_t test___riscv_vneg_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint16m8_t test___riscv_vneg_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vneg_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint32m1_t test___riscv_vneg_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint32m2_t test___riscv_vneg_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint32m4_t test___riscv_vneg_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint32m8_t test___riscv_vneg_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint64m1_t test___riscv_vneg_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint64m2_t test___riscv_vneg_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint64m4_t test___riscv_vneg_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+vint64m8_t test___riscv_vneg_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-2.C
new file mode 100644
index 00000000000..a7f6cd3a6b7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vneg_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint8mf4_t test___riscv_vneg_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint8mf2_t test___riscv_vneg_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint8m1_t test___riscv_vneg_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint8m2_t test___riscv_vneg_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint8m4_t test___riscv_vneg_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint8m8_t test___riscv_vneg_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint16mf4_t test___riscv_vneg_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint16mf2_t test___riscv_vneg_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint16m1_t test___riscv_vneg_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint16m2_t test___riscv_vneg_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint16m4_t test___riscv_vneg_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint16m8_t test___riscv_vneg_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint32mf2_t test___riscv_vneg_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint32m1_t test___riscv_vneg_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint32m2_t test___riscv_vneg_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint32m4_t test___riscv_vneg_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint32m8_t test___riscv_vneg_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint64m1_t test___riscv_vneg_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint64m2_t test___riscv_vneg_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint64m4_t test___riscv_vneg_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+vint64m8_t test___riscv_vneg_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-3.C
new file mode 100644
index 00000000000..985a3b0eeea
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vneg_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint8mf4_t test___riscv_vneg_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint8mf2_t test___riscv_vneg_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint8m1_t test___riscv_vneg_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint8m2_t test___riscv_vneg_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint8m4_t test___riscv_vneg_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint8m8_t test___riscv_vneg_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint16mf4_t test___riscv_vneg_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint16mf2_t test___riscv_vneg_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint16m1_t test___riscv_vneg_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint16m2_t test___riscv_vneg_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint16m4_t test___riscv_vneg_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint16m8_t test___riscv_vneg_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint32mf2_t test___riscv_vneg_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint32m1_t test___riscv_vneg_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint32m2_t test___riscv_vneg_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint32m4_t test___riscv_vneg_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint32m8_t test___riscv_vneg_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint64m1_t test___riscv_vneg_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint64m2_t test___riscv_vneg_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint64m4_t test___riscv_vneg_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+vint64m8_t test___riscv_vneg_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tum(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-1.C
new file mode 100644
index 00000000000..272fd203b35
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-1.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vneg_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint8mf4_t test___riscv_vneg_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint8mf2_t test___riscv_vneg_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint8m1_t test___riscv_vneg_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint8m2_t test___riscv_vneg_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint8m4_t test___riscv_vneg_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint8m8_t test___riscv_vneg_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint16mf4_t test___riscv_vneg_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vneg_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint16m1_t test___riscv_vneg_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint16m2_t test___riscv_vneg_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint16m4_t test___riscv_vneg_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint16m8_t test___riscv_vneg_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vneg_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint32m1_t test___riscv_vneg_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint32m2_t test___riscv_vneg_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint32m4_t test___riscv_vneg_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint32m8_t test___riscv_vneg_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint64m1_t test___riscv_vneg_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint64m2_t test___riscv_vneg_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint64m4_t test___riscv_vneg_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+vint64m8_t test___riscv_vneg_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-2.C
new file mode 100644
index 00000000000..2fc7c839d88
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-2.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vneg_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint8mf4_t test___riscv_vneg_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint8mf2_t test___riscv_vneg_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint8m1_t test___riscv_vneg_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint8m2_t test___riscv_vneg_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint8m4_t test___riscv_vneg_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint8m8_t test___riscv_vneg_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint16mf4_t test___riscv_vneg_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint16mf2_t test___riscv_vneg_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint16m1_t test___riscv_vneg_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint16m2_t test___riscv_vneg_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint16m4_t test___riscv_vneg_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint16m8_t test___riscv_vneg_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint32mf2_t test___riscv_vneg_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint32m1_t test___riscv_vneg_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint32m2_t test___riscv_vneg_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint32m4_t test___riscv_vneg_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint32m8_t test___riscv_vneg_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint64m1_t test___riscv_vneg_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint64m2_t test___riscv_vneg_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint64m4_t test___riscv_vneg_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+vint64m8_t test___riscv_vneg_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-3.C
new file mode 100644
index 00000000000..dd50d5d5890
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-3.C
@@ -0,0 +1,160 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vneg_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint8mf4_t test___riscv_vneg_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint8mf2_t test___riscv_vneg_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint8m1_t test___riscv_vneg_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint8m2_t test___riscv_vneg_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint8m4_t test___riscv_vneg_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint8m8_t test___riscv_vneg_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint16mf4_t test___riscv_vneg_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint16mf2_t test___riscv_vneg_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint16m1_t test___riscv_vneg_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint16m2_t test___riscv_vneg_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint16m4_t test___riscv_vneg_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint16m8_t test___riscv_vneg_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint32mf2_t test___riscv_vneg_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint32m1_t test___riscv_vneg_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint32m2_t test___riscv_vneg_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint32m4_t test___riscv_vneg_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint32m8_t test___riscv_vneg_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint64m1_t test___riscv_vneg_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint64m2_t test___riscv_vneg_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint64m4_t test___riscv_vneg_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+vint64m8_t test___riscv_vneg_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vneg_tumu(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */