diff mbox series

RISC-V: Add unary C/C++ API support

Message ID 20230203232115.223866-1-juzhe.zhong@rivai.ai
State Unresolved
Headers
Series RISC-V: Add unary C/C++ API support |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

juzhe.zhong@rivai.ai Feb. 3, 2023, 11:21 p.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

        * config/riscv/iterators.md: Add neg and not.
        * config/riscv/riscv-vector-builtins-bases.cc (class unop): New class.
        (BASE): Ditto.
        * config/riscv/riscv-vector-builtins-bases.h: Ditto.
        * config/riscv/riscv-vector-builtins-functions.def (vadd): Rename binop into alu.
        (vsub): Ditto.
        (vand): Ditto.
        (vor): Ditto.
        (vxor): Ditto.
        (vsll): Ditto.
        (vsra): Ditto.
        (vsrl): Ditto.
        (vmin): Ditto.
        (vmax): Ditto.
        (vminu): Ditto.
        (vmaxu): Ditto.
        (vmul): Ditto.
        (vdiv): Ditto.
        (vrem): Ditto.
        (vdivu): Ditto.
        (vremu): Ditto.
        (vrsub): Ditto.
        (vneg): Ditto.
        (vnot): Ditto.
        * config/riscv/riscv-vector-builtins-shapes.cc (struct binop_def): Ditto.
        (struct alu_def): Ditto.
        (SHAPE): Ditto.
        * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
        * config/riscv/riscv-vector-builtins.cc: Support unary C/C/++.
        * config/riscv/vector-iterators.md: New iterator.
        * config/riscv/vector.md (@pred_<optab><mode>): New pattern

---
 gcc/config/riscv/iterators.md                 |  8 ++-
 .../riscv/riscv-vector-builtins-bases.cc      | 15 ++++
 .../riscv/riscv-vector-builtins-bases.h       |  2 +
 .../riscv/riscv-vector-builtins-functions.def | 72 ++++++++++---------
 .../riscv/riscv-vector-builtins-shapes.cc     |  6 +-
 .../riscv/riscv-vector-builtins-shapes.h      |  2 +-
 gcc/config/riscv/riscv-vector-builtins.cc     | 12 ++++
 gcc/config/riscv/vector-iterators.md          |  2 +
 gcc/config/riscv/vector.md                    | 30 ++++++++
 9 files changed, 108 insertions(+), 41 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 9561403419b..6013f58db6e 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -201,7 +201,9 @@ 
 			 (smax "smax")
 			 (umin "umin")
 			 (umax "umax")
-			 (mult "mul")])
+			 (mult "mul")
+			 (not "one_cmpl")
+			 (neg "neg")])
 
 ;; <or_optab> code attributes
 (define_code_attr or_optab [(ior "ior")
@@ -224,7 +226,9 @@ 
 			(smax "max")
 			(umin "minu")
 			(umax "maxu")
-			(mult "mul")])
+			(mult "mul")
+			(not "not")
+			(neg "neg")])
 
 ; atomics code attribute
 (define_code_attr atomic_optab
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 0d54694398d..0d86bbcd6b1 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -186,6 +186,17 @@  public:
   }
 };
 
+/* Implements vneg/vnot.  */
+template<rtx_code CODE>
+class unop : public function_base
+{
+public:
+  rtx expand (function_expander &e) const override
+  {
+    return e.use_exact_insn (code_for_pred (CODE, e.vector_mode ()));
+  }
+};
+
 static CONSTEXPR const vsetvl<false> vsetvl_obj;
 static CONSTEXPR const vsetvl<true> vsetvlmax_obj;
 static CONSTEXPR const loadstore<false, LST_UNIT_STRIDE, false> vle_obj;
@@ -228,6 +239,8 @@  static CONSTEXPR const binop<DIV> vdiv_obj;
 static CONSTEXPR const binop<MOD> vrem_obj;
 static CONSTEXPR const binop<UDIV> vdivu_obj;
 static CONSTEXPR const binop<UMOD> vremu_obj;
+static CONSTEXPR const unop<NEG> vneg_obj;
+static CONSTEXPR const unop<NOT> vnot_obj;
 
 /* Declare the function base NAME, pointing it to an instance
    of class <NAME>_obj.  */
@@ -276,5 +289,7 @@  BASE (vdiv)
 BASE (vrem)
 BASE (vdivu)
 BASE (vremu)
+BASE (vneg)
+BASE (vnot)
 
 } // end namespace riscv_vector
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h
index a8b65dee6fc..72ee25655b2 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -66,6 +66,8 @@  extern const function_base *const vdiv;
 extern const function_base *const vrem;
 extern const function_base *const vdivu;
 extern const function_base *const vremu;
+extern const function_base *const vneg;
+extern const function_base *const vnot;
 }
 
 } // end namespace riscv_vector
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index d5df5c3d433..b94e780e916 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -63,40 +63,42 @@  DEF_RVV_FUNCTION (vsoxei16, indexed_loadstore, none_m_preds, all_v_scalar_ptr_ui
 DEF_RVV_FUNCTION (vsoxei32, indexed_loadstore, none_m_preds, all_v_scalar_ptr_uint32_index_ops)
 DEF_RVV_FUNCTION (vsoxei64, indexed_loadstore, none_m_preds, all_v_scalar_ptr_uint64_index_ops)
 /* 11. Vector Integer Arithmetic Instructions.  */
-DEF_RVV_FUNCTION (vadd, binop, full_preds, iu_vvv_ops)
-DEF_RVV_FUNCTION (vsub, binop, full_preds, iu_vvv_ops)
-DEF_RVV_FUNCTION (vand, binop, full_preds, iu_vvv_ops)
-DEF_RVV_FUNCTION (vor, binop, full_preds, iu_vvv_ops)
-DEF_RVV_FUNCTION (vxor, binop, full_preds, iu_vvv_ops)
-DEF_RVV_FUNCTION (vsll, binop, full_preds, iu_shift_vvv_ops)
-DEF_RVV_FUNCTION (vsra, binop, full_preds, iu_shift_vvv_ops)
-DEF_RVV_FUNCTION (vsrl, binop, full_preds, iu_shift_vvv_ops)
-DEF_RVV_FUNCTION (vmin, binop, full_preds, i_vvv_ops)
-DEF_RVV_FUNCTION (vmax, binop, full_preds, i_vvv_ops)
-DEF_RVV_FUNCTION (vminu, binop, full_preds, u_vvv_ops)
-DEF_RVV_FUNCTION (vmaxu, binop, full_preds, u_vvv_ops)
-DEF_RVV_FUNCTION (vmul, binop, full_preds, iu_vvv_ops)
-DEF_RVV_FUNCTION (vdiv, binop, full_preds, i_vvv_ops)
-DEF_RVV_FUNCTION (vrem, binop, full_preds, i_vvv_ops)
-DEF_RVV_FUNCTION (vdivu, binop, full_preds, u_vvv_ops)
-DEF_RVV_FUNCTION (vremu, binop, full_preds, u_vvv_ops)
-DEF_RVV_FUNCTION (vadd, binop, full_preds, iu_vvx_ops)
-DEF_RVV_FUNCTION (vsub, binop, full_preds, iu_vvx_ops)
-DEF_RVV_FUNCTION (vrsub, binop, full_preds, iu_vvx_ops)
-DEF_RVV_FUNCTION (vand, binop, full_preds, iu_vvx_ops)
-DEF_RVV_FUNCTION (vor, binop, full_preds, iu_vvx_ops)
-DEF_RVV_FUNCTION (vxor, binop, full_preds, iu_vvx_ops)
-DEF_RVV_FUNCTION (vsll, binop, full_preds, iu_shift_vvx_ops)
-DEF_RVV_FUNCTION (vsra, binop, full_preds, iu_shift_vvx_ops)
-DEF_RVV_FUNCTION (vsrl, binop, full_preds, iu_shift_vvx_ops)
-DEF_RVV_FUNCTION (vmin, binop, full_preds, i_vvx_ops)
-DEF_RVV_FUNCTION (vmax, binop, full_preds, i_vvx_ops)
-DEF_RVV_FUNCTION (vminu, binop, full_preds, u_vvx_ops)
-DEF_RVV_FUNCTION (vmaxu, binop, full_preds, u_vvx_ops)
-DEF_RVV_FUNCTION (vmul, binop, full_preds, iu_vvx_ops)
-DEF_RVV_FUNCTION (vdiv, binop, full_preds, i_vvx_ops)
-DEF_RVV_FUNCTION (vrem, binop, full_preds, i_vvx_ops)
-DEF_RVV_FUNCTION (vdivu, binop, full_preds, u_vvx_ops)
-DEF_RVV_FUNCTION (vremu, binop, full_preds, u_vvx_ops)
+DEF_RVV_FUNCTION (vadd, alu, full_preds, iu_vvv_ops)
+DEF_RVV_FUNCTION (vsub, alu, full_preds, iu_vvv_ops)
+DEF_RVV_FUNCTION (vand, alu, full_preds, iu_vvv_ops)
+DEF_RVV_FUNCTION (vor, alu, full_preds, iu_vvv_ops)
+DEF_RVV_FUNCTION (vxor, alu, full_preds, iu_vvv_ops)
+DEF_RVV_FUNCTION (vsll, alu, full_preds, iu_shift_vvv_ops)
+DEF_RVV_FUNCTION (vsra, alu, full_preds, iu_shift_vvv_ops)
+DEF_RVV_FUNCTION (vsrl, alu, full_preds, iu_shift_vvv_ops)
+DEF_RVV_FUNCTION (vmin, alu, full_preds, i_vvv_ops)
+DEF_RVV_FUNCTION (vmax, alu, full_preds, i_vvv_ops)
+DEF_RVV_FUNCTION (vminu, alu, full_preds, u_vvv_ops)
+DEF_RVV_FUNCTION (vmaxu, alu, full_preds, u_vvv_ops)
+DEF_RVV_FUNCTION (vmul, alu, full_preds, iu_vvv_ops)
+DEF_RVV_FUNCTION (vdiv, alu, full_preds, i_vvv_ops)
+DEF_RVV_FUNCTION (vrem, alu, full_preds, i_vvv_ops)
+DEF_RVV_FUNCTION (vdivu, alu, full_preds, u_vvv_ops)
+DEF_RVV_FUNCTION (vremu, alu, full_preds, u_vvv_ops)
+DEF_RVV_FUNCTION (vadd, alu, full_preds, iu_vvx_ops)
+DEF_RVV_FUNCTION (vsub, alu, full_preds, iu_vvx_ops)
+DEF_RVV_FUNCTION (vrsub, alu, full_preds, iu_vvx_ops)
+DEF_RVV_FUNCTION (vand, alu, full_preds, iu_vvx_ops)
+DEF_RVV_FUNCTION (vor, alu, full_preds, iu_vvx_ops)
+DEF_RVV_FUNCTION (vxor, alu, full_preds, iu_vvx_ops)
+DEF_RVV_FUNCTION (vsll, alu, full_preds, iu_shift_vvx_ops)
+DEF_RVV_FUNCTION (vsra, alu, full_preds, iu_shift_vvx_ops)
+DEF_RVV_FUNCTION (vsrl, alu, full_preds, iu_shift_vvx_ops)
+DEF_RVV_FUNCTION (vmin, alu, full_preds, i_vvx_ops)
+DEF_RVV_FUNCTION (vmax, alu, full_preds, i_vvx_ops)
+DEF_RVV_FUNCTION (vminu, alu, full_preds, u_vvx_ops)
+DEF_RVV_FUNCTION (vmaxu, alu, full_preds, u_vvx_ops)
+DEF_RVV_FUNCTION (vmul, alu, full_preds, iu_vvx_ops)
+DEF_RVV_FUNCTION (vdiv, alu, full_preds, i_vvx_ops)
+DEF_RVV_FUNCTION (vrem, alu, full_preds, i_vvx_ops)
+DEF_RVV_FUNCTION (vdivu, alu, full_preds, u_vvx_ops)
+DEF_RVV_FUNCTION (vremu, alu, full_preds, u_vvx_ops)
+DEF_RVV_FUNCTION (vneg, alu, full_preds, iu_v_ops)
+DEF_RVV_FUNCTION (vnot, alu, full_preds, iu_v_ops)
 
 #undef DEF_RVV_FUNCTION
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
index c8bca3598ac..d6dc4c7049e 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
@@ -185,8 +185,8 @@  struct indexed_loadstore_def : public function_shape
   }
 };
 
-/* binop_def class.  */
-struct binop_def : public build_base
+/* alu_def class.  */
+struct alu_def : public build_base
 {
   char *get_name (function_builder &b, const function_instance &instance,
 		  bool overloaded_p) const override
@@ -213,6 +213,6 @@  SHAPE(vsetvl, vsetvl)
 SHAPE(vsetvl, vsetvlmax)
 SHAPE(loadstore, loadstore)
 SHAPE(indexed_loadstore, indexed_loadstore)
-SHAPE(binop, binop)
+SHAPE(alu, alu)
 
 } // end namespace riscv_vector
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.h b/gcc/config/riscv/riscv-vector-builtins-shapes.h
index 2903c2dfead..b4f6eaa0bba 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.h
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.h
@@ -28,7 +28,7 @@  extern const function_shape *const vsetvl;
 extern const function_shape *const vsetvlmax;
 extern const function_shape *const loadstore;
 extern const function_shape *const indexed_loadstore;
-extern const function_shape *const binop;
+extern const function_shape *const alu;
 }
 
 } // end namespace riscv_vector
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 70df5d1ce87..95a949aab7c 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -260,6 +260,10 @@  static CONSTEXPR const rvv_arg_type_info shift_vv_args[]
   = {rvv_arg_type_info (RVV_BASE_vector),
      rvv_arg_type_info (RVV_BASE_shift_vector), rvv_arg_type_info_end};
 
+/* A list of args for vector_type func (vector_type) function.  */
+static CONSTEXPR const rvv_arg_type_info v_args[]
+  = {rvv_arg_type_info (RVV_BASE_vector), rvv_arg_type_info_end};
+
 /* A list of args for vector_type func (vector_type, size) function.  */
 static CONSTEXPR const rvv_arg_type_info vector_size_args[]
   = {rvv_arg_type_info (RVV_BASE_vector), rvv_arg_type_info (RVV_BASE_size),
@@ -469,6 +473,14 @@  static CONSTEXPR const rvv_op_info iu_shift_vvx_ops
      rvv_arg_type_info (RVV_BASE_vector), /* Return type */
      vector_size_args /* Args */};
 
+/* A static operand information for vector_type func (vector_type)
+ * function registration. */
+static CONSTEXPR const rvv_op_info iu_v_ops
+  = {iu_ops,			/* Types */
+     OP_TYPE_v,			/* Suffix */
+     rvv_arg_type_info (RVV_BASE_vector), /* Return type */
+     v_args /* Args */};
+
 /* A list of all RVV intrinsic functions.  */
 static function_group_info function_groups[] = {
 #define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO)                         \
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index ed9da0c35a6..9cc60da91f4 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -209,6 +209,8 @@ 
   smax umax smin umin mult div udiv mod umod
 ])
 
+(define_code_iterator any_int_unop [neg not])
+
 (define_code_iterator any_commutative_binop [plus and ior xor
   smax umax smin umin mult
 ])
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 02ded957f99..73c839f45c3 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1531,3 +1531,33 @@ 
   "vrsub.vx\t%0,%3,%4%p1"
   [(set_attr "type" "vialu")
    (set_attr "mode" "<MODE>")])
+
+;; -------------------------------------------------------------------------------
+;; ---- Predicated integer unary operations
+;; -------------------------------------------------------------------------------
+;; Includes:
+;; - vneg.v/vnot.v
+;; -------------------------------------------------------------------------------
+
+(define_insn "@pred_<optab><mode>"
+  [(set (match_operand:VI 0 "register_operand"           "=vd, vr")
+	(if_then_else:VI
+	  (unspec:<VM>
+	    [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
+	     (match_operand 4 "vector_length_operand"    " rK, rK")
+	     (match_operand 5 "const_int_operand"        "  i,  i")
+	     (match_operand 6 "const_int_operand"        "  i,  i")
+	     (match_operand 7 "const_int_operand"        "  i,  i")
+	     (reg:SI VL_REGNUM)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	  (any_int_unop:VI
+	    (match_operand:VI 3 "register_operand"       " vr, vr"))
+	  (match_operand:VI 2 "vector_merge_operand"     "0vu,0vu")))]
+  "TARGET_VECTOR"
+  "v<insn>.v\t%0,%3%p1"
+  [(set_attr "type" "vialu")
+   (set_attr "mode" "<MODE>")
+   (set_attr "vl_op_idx" "4")
+   (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
+   (set (attr "ma") (symbol_ref "riscv_vector::get_ta(operands[6])"))
+   (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])