diff mbox series

RISC-V: Add vrsub.vx C++ API tests

Message ID 20230203074318.199552-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Add vrsub.vx C++ API tests |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai Feb. 3, 2023, 7:43 a.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-3.C: New test.

---
 .../riscv/rvv/base/vrsub_vx_mu_rv32-1.C       | 289 +++++++++
 .../riscv/rvv/base/vrsub_vx_mu_rv32-2.C       | 289 +++++++++
 .../riscv/rvv/base/vrsub_vx_mu_rv32-3.C       | 289 +++++++++
 .../riscv/rvv/base/vrsub_vx_mu_rv64-1.C       | 292 +++++++++
 .../riscv/rvv/base/vrsub_vx_mu_rv64-2.C       | 292 +++++++++
 .../riscv/rvv/base/vrsub_vx_mu_rv64-3.C       | 292 +++++++++
 .../riscv/rvv/base/vrsub_vx_rv32-1.C          | 572 +++++++++++++++++
 .../riscv/rvv/base/vrsub_vx_rv32-2.C          | 572 +++++++++++++++++
 .../riscv/rvv/base/vrsub_vx_rv32-3.C          | 572 +++++++++++++++++
 .../riscv/rvv/base/vrsub_vx_rv64-1.C          | 578 ++++++++++++++++++
 .../riscv/rvv/base/vrsub_vx_rv64-2.C          | 578 ++++++++++++++++++
 .../riscv/rvv/base/vrsub_vx_rv64-3.C          | 578 ++++++++++++++++++
 .../riscv/rvv/base/vrsub_vx_tu_rv32-1.C       | 289 +++++++++
 .../riscv/rvv/base/vrsub_vx_tu_rv32-2.C       | 289 +++++++++
 .../riscv/rvv/base/vrsub_vx_tu_rv32-3.C       | 289 +++++++++
 .../riscv/rvv/base/vrsub_vx_tu_rv64-1.C       | 292 +++++++++
 .../riscv/rvv/base/vrsub_vx_tu_rv64-2.C       | 292 +++++++++
 .../riscv/rvv/base/vrsub_vx_tu_rv64-3.C       | 292 +++++++++
 .../riscv/rvv/base/vrsub_vx_tum_rv32-1.C      | 289 +++++++++
 .../riscv/rvv/base/vrsub_vx_tum_rv32-2.C      | 289 +++++++++
 .../riscv/rvv/base/vrsub_vx_tum_rv32-3.C      | 289 +++++++++
 .../riscv/rvv/base/vrsub_vx_tum_rv64-1.C      | 292 +++++++++
 .../riscv/rvv/base/vrsub_vx_tum_rv64-2.C      | 292 +++++++++
 .../riscv/rvv/base/vrsub_vx_tum_rv64-3.C      | 292 +++++++++
 .../riscv/rvv/base/vrsub_vx_tumu_rv32-1.C     | 289 +++++++++
 .../riscv/rvv/base/vrsub_vx_tumu_rv32-2.C     | 289 +++++++++
 .../riscv/rvv/base/vrsub_vx_tumu_rv32-3.C     | 289 +++++++++
 .../riscv/rvv/base/vrsub_vx_tumu_rv64-1.C     | 292 +++++++++
 .../riscv/rvv/base/vrsub_vx_tumu_rv64-2.C     | 292 +++++++++
 .../riscv/rvv/base/vrsub_vx_tumu_rv64-3.C     | 292 +++++++++
 30 files changed, 10422 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-3.C
diff mbox series

Patch

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-1.C
new file mode 100644
index 00000000000..e65a91ed38a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-1.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vrsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vrsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vrsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vrsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vrsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vrsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vrsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vrsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vrsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vrsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vrsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vrsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vrsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vrsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vrsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vrsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-2.C
new file mode 100644
index 00000000000..e96c71b6658
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-2.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vrsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vrsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vrsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vrsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vrsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vrsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vrsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vrsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vrsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vrsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vrsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vrsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vrsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vrsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vrsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vrsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-3.C
new file mode 100644
index 00000000000..219495f9c10
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-3.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vrsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vrsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vrsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vrsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vrsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vrsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vrsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vrsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vrsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vrsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vrsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vrsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vrsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vrsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vrsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vrsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-1.C
new file mode 100644
index 00000000000..3b85308e40a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-1.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vrsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vrsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vrsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vrsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vrsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vrsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vrsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vrsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vrsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vrsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vrsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vrsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vrsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vrsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vrsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vrsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-2.C
new file mode 100644
index 00000000000..27dadd553cf
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-2.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vrsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vrsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vrsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vrsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vrsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vrsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vrsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vrsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vrsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vrsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vrsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vrsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vrsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vrsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vrsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vrsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-3.C
new file mode 100644
index 00000000000..58a4c40ba1c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-3.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vrsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vrsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vrsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vrsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vrsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vrsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vrsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vrsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vrsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vrsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vrsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vrsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vrsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vrsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vrsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vrsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-1.C
new file mode 100644
index 00000000000..09a3170f174
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-1.C
@@ -0,0 +1,572 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrsub(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrsub(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrsub(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrsub(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrsub(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrsub(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrsub(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrsub(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrsub(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrsub(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrsub(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrsub(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrsub(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrsub(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrsub(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrsub(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrsub(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrsub(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrsub(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrsub(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrsub(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vrsub(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vrsub(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vrsub(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vrsub(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vrsub(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vrsub(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vrsub(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vrsub(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vrsub(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vrsub(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vrsub(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vrsub(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vrsub(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vrsub(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vrsub(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vrsub(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vrsub(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vrsub(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vrsub(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vrsub(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vrsub(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vrsub(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint8mf8_t test___riscv_vrsub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrsub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrsub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrsub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrsub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrsub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrsub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrsub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrsub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrsub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrsub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrsub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrsub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrsub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrsub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrsub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrsub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrsub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrsub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrsub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrsub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrsub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vrsub(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vrsub(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vrsub(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vrsub(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vrsub(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vrsub(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vrsub(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vrsub(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vrsub(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vrsub(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vrsub(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vrsub(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vrsub(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vrsub(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vrsub(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vrsub(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vrsub(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vrsub(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vrsub(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vrsub(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vrsub(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vrsub(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-2.C
new file mode 100644
index 00000000000..c66350632cd
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-2.C
@@ -0,0 +1,572 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrsub(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrsub(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrsub(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrsub(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrsub(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrsub(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrsub(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrsub(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrsub(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrsub(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrsub(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrsub(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrsub(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrsub(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrsub(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrsub(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrsub(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrsub(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrsub(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrsub(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrsub(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vrsub(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vrsub(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vrsub(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vrsub(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vrsub(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vrsub(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vrsub(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vrsub(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vrsub(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vrsub(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vrsub(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vrsub(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vrsub(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vrsub(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vrsub(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vrsub(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vrsub(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vrsub(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vrsub(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vrsub(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vrsub(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vrsub(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint8mf8_t test___riscv_vrsub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrsub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrsub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrsub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrsub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrsub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrsub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrsub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrsub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrsub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrsub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrsub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrsub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrsub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrsub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrsub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrsub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrsub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrsub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrsub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrsub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrsub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vrsub(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vrsub(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vrsub(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vrsub(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vrsub(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vrsub(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vrsub(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vrsub(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vrsub(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vrsub(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vrsub(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vrsub(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vrsub(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vrsub(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vrsub(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vrsub(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vrsub(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vrsub(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vrsub(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vrsub(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vrsub(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vrsub(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-3.C
new file mode 100644
index 00000000000..0e23ae70f45
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-3.C
@@ -0,0 +1,572 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrsub(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrsub(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrsub(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrsub(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrsub(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrsub(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrsub(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrsub(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrsub(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrsub(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrsub(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrsub(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrsub(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrsub(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrsub(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrsub(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrsub(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrsub(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrsub(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrsub(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrsub(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vrsub(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vrsub(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vrsub(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vrsub(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vrsub(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vrsub(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vrsub(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vrsub(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vrsub(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vrsub(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vrsub(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vrsub(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vrsub(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vrsub(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vrsub(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vrsub(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vrsub(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vrsub(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vrsub(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vrsub(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vrsub(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vrsub(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint8mf8_t test___riscv_vrsub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrsub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrsub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrsub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrsub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrsub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrsub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrsub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrsub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrsub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrsub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrsub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrsub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrsub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrsub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrsub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrsub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrsub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrsub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrsub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrsub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrsub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vrsub(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vrsub(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vrsub(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vrsub(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vrsub(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vrsub(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vrsub(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vrsub(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vrsub(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vrsub(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vrsub(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vrsub(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vrsub(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vrsub(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vrsub(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vrsub(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vrsub(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vrsub(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vrsub(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vrsub(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vrsub(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vrsub(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-1.C
new file mode 100644
index 00000000000..7d0e91a5ce0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-1.C
@@ -0,0 +1,578 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrsub(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrsub(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrsub(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrsub(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrsub(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrsub(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrsub(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrsub(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrsub(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrsub(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrsub(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrsub(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrsub(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrsub(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrsub(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrsub(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrsub(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrsub(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrsub(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrsub(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrsub(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vrsub(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vrsub(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vrsub(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vrsub(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vrsub(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vrsub(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vrsub(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vrsub(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vrsub(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vrsub(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vrsub(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vrsub(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vrsub(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vrsub(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vrsub(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vrsub(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vrsub(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vrsub(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vrsub(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vrsub(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vrsub(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vrsub(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,vl);
+}
+
+
+vint8mf8_t test___riscv_vrsub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrsub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrsub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrsub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrsub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrsub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrsub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrsub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrsub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrsub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrsub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrsub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrsub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrsub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrsub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrsub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrsub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrsub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrsub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrsub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrsub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrsub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vrsub(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vrsub(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vrsub(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vrsub(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vrsub(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vrsub(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vrsub(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vrsub(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vrsub(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vrsub(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vrsub(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vrsub(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vrsub(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vrsub(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vrsub(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vrsub(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vrsub(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vrsub(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vrsub(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vrsub(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vrsub(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vrsub(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-2.C
new file mode 100644
index 00000000000..69eaa5e640a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-2.C
@@ -0,0 +1,578 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrsub(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrsub(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrsub(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrsub(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrsub(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrsub(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrsub(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrsub(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrsub(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrsub(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrsub(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrsub(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrsub(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrsub(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrsub(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrsub(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrsub(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrsub(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrsub(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrsub(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrsub(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vrsub(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vrsub(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vrsub(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vrsub(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vrsub(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vrsub(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vrsub(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vrsub(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vrsub(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vrsub(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vrsub(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vrsub(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vrsub(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vrsub(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vrsub(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vrsub(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vrsub(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vrsub(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vrsub(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vrsub(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vrsub(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vrsub(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,31);
+}
+
+
+vint8mf8_t test___riscv_vrsub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrsub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrsub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrsub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrsub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrsub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrsub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrsub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrsub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrsub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrsub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrsub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrsub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrsub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrsub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrsub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrsub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrsub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrsub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrsub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrsub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrsub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vrsub(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vrsub(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vrsub(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vrsub(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vrsub(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vrsub(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vrsub(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vrsub(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vrsub(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vrsub(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vrsub(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vrsub(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vrsub(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vrsub(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vrsub(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vrsub(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vrsub(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vrsub(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vrsub(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vrsub(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vrsub(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vrsub(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-3.C
new file mode 100644
index 00000000000..f23a0147773
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-3.C
@@ -0,0 +1,578 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrsub(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrsub(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrsub(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrsub(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrsub(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrsub(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrsub(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrsub(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrsub(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrsub(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrsub(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrsub(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrsub(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrsub(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrsub(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrsub(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrsub(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrsub(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrsub(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrsub(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrsub(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vrsub(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vrsub(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vrsub(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vrsub(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vrsub(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vrsub(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vrsub(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vrsub(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vrsub(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vrsub(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vrsub(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vrsub(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vrsub(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vrsub(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vrsub(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vrsub(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vrsub(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vrsub(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vrsub(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vrsub(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vrsub(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vrsub(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(op1,op2,32);
+}
+
+
+vint8mf8_t test___riscv_vrsub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrsub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrsub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrsub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrsub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrsub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrsub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrsub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrsub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrsub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrsub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrsub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrsub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrsub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrsub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrsub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrsub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrsub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrsub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrsub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrsub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrsub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vrsub(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vrsub(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vrsub(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vrsub(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vrsub(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vrsub(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vrsub(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vrsub(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vrsub(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vrsub(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vrsub(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vrsub(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vrsub(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vrsub(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vrsub(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vrsub(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vrsub(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vrsub(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vrsub(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vrsub(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vrsub(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vrsub(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-1.C
new file mode 100644
index 00000000000..2b499cec9a5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-1.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrsub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrsub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrsub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrsub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrsub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrsub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrsub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrsub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrsub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrsub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrsub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrsub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrsub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrsub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrsub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrsub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrsub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrsub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrsub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrsub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrsub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vrsub_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vrsub_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vrsub_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vrsub_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vrsub_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vrsub_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vrsub_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vrsub_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vrsub_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vrsub_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vrsub_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vrsub_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vrsub_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vrsub_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vrsub_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vrsub_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-2.C
new file mode 100644
index 00000000000..2abe8f86f40
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-2.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrsub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrsub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrsub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrsub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrsub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrsub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrsub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrsub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrsub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrsub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrsub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrsub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrsub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrsub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrsub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrsub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrsub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrsub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrsub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrsub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrsub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vrsub_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vrsub_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vrsub_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vrsub_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vrsub_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vrsub_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vrsub_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vrsub_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vrsub_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vrsub_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vrsub_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vrsub_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vrsub_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vrsub_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vrsub_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vrsub_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-3.C
new file mode 100644
index 00000000000..be25c484ec9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-3.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrsub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrsub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrsub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrsub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrsub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrsub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrsub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrsub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrsub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrsub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrsub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrsub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrsub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrsub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrsub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrsub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrsub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrsub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrsub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrsub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrsub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vrsub_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vrsub_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vrsub_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vrsub_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vrsub_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vrsub_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vrsub_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vrsub_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vrsub_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vrsub_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vrsub_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vrsub_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vrsub_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vrsub_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vrsub_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vrsub_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-1.C
new file mode 100644
index 00000000000..4a90dc25754
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-1.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrsub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrsub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrsub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrsub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrsub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrsub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrsub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrsub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrsub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrsub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrsub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrsub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrsub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrsub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrsub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrsub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrsub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrsub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrsub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrsub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrsub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vrsub_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vrsub_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vrsub_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vrsub_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vrsub_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vrsub_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vrsub_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vrsub_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vrsub_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vrsub_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vrsub_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vrsub_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vrsub_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vrsub_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vrsub_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vrsub_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-2.C
new file mode 100644
index 00000000000..8f94f352e39
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-2.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrsub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrsub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrsub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrsub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrsub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrsub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrsub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrsub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrsub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrsub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrsub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrsub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrsub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrsub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrsub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrsub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrsub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrsub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrsub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrsub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrsub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vrsub_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vrsub_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vrsub_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vrsub_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vrsub_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vrsub_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vrsub_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vrsub_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vrsub_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vrsub_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vrsub_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vrsub_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vrsub_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vrsub_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vrsub_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vrsub_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-3.C
new file mode 100644
index 00000000000..a3bd9f15f35
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-3.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrsub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrsub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrsub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrsub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrsub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrsub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrsub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrsub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrsub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrsub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrsub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrsub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrsub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrsub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrsub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrsub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrsub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrsub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrsub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrsub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrsub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vrsub_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vrsub_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vrsub_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vrsub_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vrsub_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vrsub_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vrsub_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vrsub_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vrsub_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vrsub_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vrsub_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vrsub_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vrsub_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vrsub_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vrsub_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vrsub_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-1.C
new file mode 100644
index 00000000000..b2313baeb6d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-1.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vrsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vrsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vrsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vrsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vrsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vrsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vrsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vrsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vrsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vrsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vrsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vrsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vrsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vrsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vrsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vrsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-2.C
new file mode 100644
index 00000000000..150b58f8e65
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-2.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vrsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vrsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vrsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vrsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vrsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vrsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vrsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vrsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vrsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vrsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vrsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vrsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vrsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vrsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vrsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vrsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-3.C
new file mode 100644
index 00000000000..94a3735c002
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-3.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vrsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vrsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vrsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vrsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vrsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vrsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vrsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vrsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vrsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vrsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vrsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vrsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vrsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vrsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vrsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vrsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-1.C
new file mode 100644
index 00000000000..3d4d0350b23
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-1.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vrsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vrsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vrsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vrsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vrsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vrsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vrsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vrsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vrsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vrsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vrsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vrsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vrsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vrsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vrsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vrsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-2.C
new file mode 100644
index 00000000000..fbe75f6743f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-2.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vrsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vrsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vrsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vrsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vrsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vrsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vrsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vrsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vrsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vrsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vrsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vrsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vrsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vrsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vrsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vrsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-3.C
new file mode 100644
index 00000000000..46782113641
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-3.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vrsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vrsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vrsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vrsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vrsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vrsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vrsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vrsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vrsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vrsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vrsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vrsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vrsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vrsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vrsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vrsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-1.C
new file mode 100644
index 00000000000..daccc41fb3b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-1.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vrsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vrsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vrsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vrsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vrsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vrsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vrsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vrsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vrsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vrsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vrsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vrsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vrsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vrsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vrsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vrsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-2.C
new file mode 100644
index 00000000000..e1c63907d27
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-2.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vrsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vrsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vrsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vrsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vrsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vrsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vrsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vrsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vrsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vrsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vrsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vrsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vrsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vrsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vrsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vrsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-3.C
new file mode 100644
index 00000000000..13a915b292d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-3.C
@@ -0,0 +1,289 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vrsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vrsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vrsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vrsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vrsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vrsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vrsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vrsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vrsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vrsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vrsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vrsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vrsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vrsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vrsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vrsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-1.C
new file mode 100644
index 00000000000..1c6f3bca3e6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-1.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vrsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vrsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vrsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vrsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vrsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vrsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vrsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vrsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vrsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vrsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vrsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vrsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vrsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vrsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vrsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vrsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vrsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vrsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vrsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vrsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vrsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vrsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vrsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vrsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vrsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vrsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vrsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vrsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vrsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vrsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vrsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vrsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vrsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vrsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vrsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vrsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vrsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-2.C
new file mode 100644
index 00000000000..3c74b30ea3b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-2.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vrsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vrsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vrsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vrsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vrsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vrsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vrsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vrsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vrsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vrsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vrsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vrsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vrsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vrsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vrsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vrsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vrsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vrsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vrsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vrsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vrsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vrsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vrsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vrsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vrsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vrsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vrsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vrsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vrsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vrsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vrsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vrsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vrsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vrsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vrsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vrsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vrsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-3.C
new file mode 100644
index 00000000000..583ea1c104c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-3.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vrsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vrsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vrsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vrsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vrsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vrsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vrsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vrsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vrsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vrsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vrsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vrsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vrsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vrsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vrsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vrsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vrsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vrsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vrsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vrsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vrsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vrsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vrsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vrsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vrsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vrsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vrsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vrsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vrsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vrsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vrsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vrsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vrsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vrsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vrsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vrsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vrsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vrsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vrsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vrsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vrsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vrsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vrsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vrsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+    return __riscv_vrsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vrsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */