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Subject: [PATCH] RISC-V: Add vsub.vx C++ API tests Date: Fri, 3 Feb 2023 15:42:07 +0800 Message-Id: <20230203074207.197673-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756794942897889135?= X-GMAIL-MSGID: =?utf-8?q?1756794942897889135?= From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vsub_vx_mu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vsub_vx_mu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vsub_vx_mu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vsub_vx_mu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vsub_vx_mu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vsub_vx_mu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vsub_vx_rv32-1.C: New test. * g++.target/riscv/rvv/base/vsub_vx_rv32-2.C: New test. * g++.target/riscv/rvv/base/vsub_vx_rv32-3.C: New test. * g++.target/riscv/rvv/base/vsub_vx_rv64-1.C: New test. * g++.target/riscv/rvv/base/vsub_vx_rv64-2.C: New test. * g++.target/riscv/rvv/base/vsub_vx_rv64-3.C: New test. * g++.target/riscv/rvv/base/vsub_vx_tu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vsub_vx_tu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vsub_vx_tu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vsub_vx_tu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vsub_vx_tu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vsub_vx_tu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vsub_vx_tum_rv32-1.C: New test. * g++.target/riscv/rvv/base/vsub_vx_tum_rv32-2.C: New test. * g++.target/riscv/rvv/base/vsub_vx_tum_rv32-3.C: New test. * g++.target/riscv/rvv/base/vsub_vx_tum_rv64-1.C: New test. * g++.target/riscv/rvv/base/vsub_vx_tum_rv64-2.C: New test. * g++.target/riscv/rvv/base/vsub_vx_tum_rv64-3.C: New test. * g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-3.C: New test. --- .../riscv/rvv/base/vsub_vx_mu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vsub_vx_mu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vsub_vx_mu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vsub_vx_mu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vsub_vx_mu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vsub_vx_mu_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vsub_vx_rv32-1.C | 572 +++++++++++++++++ .../riscv/rvv/base/vsub_vx_rv32-2.C | 572 +++++++++++++++++ .../riscv/rvv/base/vsub_vx_rv32-3.C | 572 +++++++++++++++++ .../riscv/rvv/base/vsub_vx_rv64-1.C | 578 ++++++++++++++++++ .../riscv/rvv/base/vsub_vx_rv64-2.C | 578 ++++++++++++++++++ .../riscv/rvv/base/vsub_vx_rv64-3.C | 578 ++++++++++++++++++ .../riscv/rvv/base/vsub_vx_tu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vsub_vx_tu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vsub_vx_tu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vsub_vx_tu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vsub_vx_tu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vsub_vx_tu_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vsub_vx_tum_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vsub_vx_tum_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vsub_vx_tum_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vsub_vx_tum_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vsub_vx_tum_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vsub_vx_tum_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vsub_vx_tumu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vsub_vx_tumu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vsub_vx_tumu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vsub_vx_tumu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vsub_vx_tumu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vsub_vx_tumu_rv64-3.C | 292 +++++++++ 30 files changed, 10422 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-1.C new file mode 100644 index 00000000000..6e8f536247b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-2.C new file mode 100644 index 00000000000..ba395cacce4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-3.C new file mode 100644 index 00000000000..7afe9ded282 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-1.C new file mode 100644 index 00000000000..562d9d70832 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-2.C new file mode 100644 index 00000000000..dc6b08caad6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-3.C new file mode 100644 index 00000000000..6d90eafcf8c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-1.C new file mode 100644 index 00000000000..71c4f43a981 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-1.C @@ -0,0 +1,572 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vsub(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vsub(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8m1_t test___riscv_vsub(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8m2_t test___riscv_vsub(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8m4_t test___riscv_vsub(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8m8_t test___riscv_vsub(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vsub(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vsub(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint16m1_t test___riscv_vsub(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint16m2_t test___riscv_vsub(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint16m4_t test___riscv_vsub(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint16m8_t test___riscv_vsub(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vsub(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint32m1_t test___riscv_vsub(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint32m2_t test___riscv_vsub(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint32m4_t test___riscv_vsub(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint32m8_t test___riscv_vsub(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint64m1_t test___riscv_vsub(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint64m2_t test___riscv_vsub(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint64m4_t test___riscv_vsub(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint64m8_t test___riscv_vsub(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vsub(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vsub(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vsub(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8m1_t test___riscv_vsub(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8m2_t test___riscv_vsub(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8m4_t test___riscv_vsub(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8m8_t test___riscv_vsub(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vsub(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vsub(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vsub(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vsub(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vsub(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vsub(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vsub(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vsub(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vsub(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vsub(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vsub(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vsub(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vsub(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vsub(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vsub(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8mf8_t test___riscv_vsub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vsub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vsub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vsub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vsub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vsub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vsub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vsub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vsub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vsub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vsub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vsub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vsub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vsub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vsub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vsub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vsub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vsub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vsub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vsub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vsub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vsub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vsub(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vsub(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vsub(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vsub(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vsub(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vsub(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vsub(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vsub(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vsub(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vsub(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vsub(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vsub(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vsub(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vsub(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vsub(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vsub(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vsub(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vsub(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vsub(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vsub(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vsub(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vsub(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-2.C new file mode 100644 index 00000000000..dd7074590d2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-2.C @@ -0,0 +1,572 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8mf4_t test___riscv_vsub(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8mf2_t test___riscv_vsub(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8m1_t test___riscv_vsub(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8m2_t test___riscv_vsub(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8m4_t test___riscv_vsub(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8m8_t test___riscv_vsub(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint16mf4_t test___riscv_vsub(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint16mf2_t test___riscv_vsub(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint16m1_t test___riscv_vsub(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint16m2_t test___riscv_vsub(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint16m4_t test___riscv_vsub(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint16m8_t test___riscv_vsub(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint32mf2_t test___riscv_vsub(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint32m1_t test___riscv_vsub(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint32m2_t test___riscv_vsub(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint32m4_t test___riscv_vsub(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint32m8_t test___riscv_vsub(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint64m1_t test___riscv_vsub(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint64m2_t test___riscv_vsub(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint64m4_t test___riscv_vsub(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint64m8_t test___riscv_vsub(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8mf8_t test___riscv_vsub(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8mf4_t test___riscv_vsub(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8mf2_t test___riscv_vsub(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8m1_t test___riscv_vsub(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8m2_t test___riscv_vsub(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8m4_t test___riscv_vsub(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8m8_t test___riscv_vsub(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vsub(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vsub(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint16m1_t test___riscv_vsub(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint16m2_t test___riscv_vsub(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint16m4_t test___riscv_vsub(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint16m8_t test___riscv_vsub(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vsub(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint32m1_t test___riscv_vsub(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint32m2_t test___riscv_vsub(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint32m4_t test___riscv_vsub(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint32m8_t test___riscv_vsub(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint64m1_t test___riscv_vsub(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint64m2_t test___riscv_vsub(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint64m4_t test___riscv_vsub(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint64m8_t test___riscv_vsub(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8mf8_t test___riscv_vsub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vsub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vsub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vsub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vsub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vsub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vsub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vsub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vsub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vsub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vsub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vsub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vsub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vsub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vsub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vsub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vsub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vsub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vsub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vsub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vsub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vsub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vsub(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vsub(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vsub(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8m1_t test___riscv_vsub(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8m2_t test___riscv_vsub(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8m4_t test___riscv_vsub(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8m8_t test___riscv_vsub(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vsub(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vsub(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vsub(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vsub(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vsub(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vsub(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vsub(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vsub(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vsub(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vsub(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vsub(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vsub(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vsub(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vsub(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vsub(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-3.C new file mode 100644 index 00000000000..e5e0982c4a7 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-3.C @@ -0,0 +1,572 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8mf4_t test___riscv_vsub(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8mf2_t test___riscv_vsub(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8m1_t test___riscv_vsub(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8m2_t test___riscv_vsub(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8m4_t test___riscv_vsub(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8m8_t test___riscv_vsub(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint16mf4_t test___riscv_vsub(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint16mf2_t test___riscv_vsub(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint16m1_t test___riscv_vsub(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint16m2_t test___riscv_vsub(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint16m4_t test___riscv_vsub(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint16m8_t test___riscv_vsub(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint32mf2_t test___riscv_vsub(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint32m1_t test___riscv_vsub(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint32m2_t test___riscv_vsub(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint32m4_t test___riscv_vsub(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint32m8_t test___riscv_vsub(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint64m1_t test___riscv_vsub(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint64m2_t test___riscv_vsub(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint64m4_t test___riscv_vsub(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint64m8_t test___riscv_vsub(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8mf8_t test___riscv_vsub(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8mf4_t test___riscv_vsub(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8mf2_t test___riscv_vsub(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8m1_t test___riscv_vsub(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8m2_t test___riscv_vsub(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8m4_t test___riscv_vsub(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8m8_t test___riscv_vsub(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vsub(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vsub(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint16m1_t test___riscv_vsub(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint16m2_t test___riscv_vsub(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint16m4_t test___riscv_vsub(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint16m8_t test___riscv_vsub(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vsub(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint32m1_t test___riscv_vsub(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint32m2_t test___riscv_vsub(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint32m4_t test___riscv_vsub(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint32m8_t test___riscv_vsub(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint64m1_t test___riscv_vsub(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint64m2_t test___riscv_vsub(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint64m4_t test___riscv_vsub(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint64m8_t test___riscv_vsub(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8mf8_t test___riscv_vsub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vsub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vsub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vsub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vsub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vsub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vsub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vsub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vsub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vsub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vsub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vsub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vsub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vsub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vsub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vsub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vsub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vsub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vsub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vsub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vsub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vsub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vsub(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vsub(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vsub(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8m1_t test___riscv_vsub(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8m2_t test___riscv_vsub(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8m4_t test___riscv_vsub(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8m8_t test___riscv_vsub(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vsub(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vsub(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vsub(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vsub(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vsub(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vsub(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vsub(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vsub(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vsub(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vsub(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vsub(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vsub(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vsub(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vsub(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vsub(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-1.C new file mode 100644 index 00000000000..f602a79ed44 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-1.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vsub(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vsub(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8m1_t test___riscv_vsub(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8m2_t test___riscv_vsub(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8m4_t test___riscv_vsub(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8m8_t test___riscv_vsub(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vsub(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vsub(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint16m1_t test___riscv_vsub(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint16m2_t test___riscv_vsub(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint16m4_t test___riscv_vsub(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint16m8_t test___riscv_vsub(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vsub(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint32m1_t test___riscv_vsub(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint32m2_t test___riscv_vsub(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint32m4_t test___riscv_vsub(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint32m8_t test___riscv_vsub(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint64m1_t test___riscv_vsub(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint64m2_t test___riscv_vsub(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint64m4_t test___riscv_vsub(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint64m8_t test___riscv_vsub(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vsub(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vsub(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vsub(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8m1_t test___riscv_vsub(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8m2_t test___riscv_vsub(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8m4_t test___riscv_vsub(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint8m8_t test___riscv_vsub(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vsub(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vsub(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vsub(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vsub(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vsub(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vsub(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vsub(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vsub(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vsub(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vsub(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vsub(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vsub(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vsub(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vsub(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vsub(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,vl); +} + + +vint8mf8_t test___riscv_vsub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vsub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vsub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vsub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vsub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vsub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vsub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vsub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vsub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vsub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vsub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vsub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vsub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vsub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vsub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vsub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vsub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vsub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vsub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vsub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vsub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vsub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vsub(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vsub(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vsub(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vsub(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vsub(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vsub(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vsub(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vsub(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vsub(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vsub(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vsub(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vsub(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vsub(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vsub(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vsub(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vsub(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vsub(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vsub(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vsub(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vsub(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vsub(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vsub(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-2.C new file mode 100644 index 00000000000..bfd2d6924a7 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-2.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8mf4_t test___riscv_vsub(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8mf2_t test___riscv_vsub(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8m1_t test___riscv_vsub(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8m2_t test___riscv_vsub(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8m4_t test___riscv_vsub(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8m8_t test___riscv_vsub(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint16mf4_t test___riscv_vsub(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint16mf2_t test___riscv_vsub(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint16m1_t test___riscv_vsub(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint16m2_t test___riscv_vsub(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint16m4_t test___riscv_vsub(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint16m8_t test___riscv_vsub(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint32mf2_t test___riscv_vsub(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint32m1_t test___riscv_vsub(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint32m2_t test___riscv_vsub(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint32m4_t test___riscv_vsub(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint32m8_t test___riscv_vsub(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint64m1_t test___riscv_vsub(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint64m2_t test___riscv_vsub(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint64m4_t test___riscv_vsub(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint64m8_t test___riscv_vsub(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8mf8_t test___riscv_vsub(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8mf4_t test___riscv_vsub(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8mf2_t test___riscv_vsub(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8m1_t test___riscv_vsub(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8m2_t test___riscv_vsub(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8m4_t test___riscv_vsub(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint8m8_t test___riscv_vsub(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vsub(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vsub(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint16m1_t test___riscv_vsub(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint16m2_t test___riscv_vsub(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint16m4_t test___riscv_vsub(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint16m8_t test___riscv_vsub(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vsub(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint32m1_t test___riscv_vsub(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint32m2_t test___riscv_vsub(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint32m4_t test___riscv_vsub(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint32m8_t test___riscv_vsub(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint64m1_t test___riscv_vsub(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint64m2_t test___riscv_vsub(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint64m4_t test___riscv_vsub(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vuint64m8_t test___riscv_vsub(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,31); +} + + +vint8mf8_t test___riscv_vsub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vsub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vsub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vsub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vsub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vsub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vsub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vsub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vsub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vsub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vsub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vsub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vsub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vsub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vsub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vsub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vsub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vsub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vsub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vsub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vsub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vsub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vsub(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vsub(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vsub(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8m1_t test___riscv_vsub(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8m2_t test___riscv_vsub(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8m4_t test___riscv_vsub(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint8m8_t test___riscv_vsub(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vsub(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vsub(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vsub(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vsub(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vsub(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vsub(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vsub(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vsub(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vsub(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vsub(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vsub(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vsub(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vsub(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vsub(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vsub(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-3.C new file mode 100644 index 00000000000..391c1eae3d5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-3.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8mf4_t test___riscv_vsub(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8mf2_t test___riscv_vsub(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8m1_t test___riscv_vsub(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8m2_t test___riscv_vsub(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8m4_t test___riscv_vsub(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8m8_t test___riscv_vsub(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint16mf4_t test___riscv_vsub(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint16mf2_t test___riscv_vsub(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint16m1_t test___riscv_vsub(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint16m2_t test___riscv_vsub(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint16m4_t test___riscv_vsub(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint16m8_t test___riscv_vsub(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint32mf2_t test___riscv_vsub(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint32m1_t test___riscv_vsub(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint32m2_t test___riscv_vsub(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint32m4_t test___riscv_vsub(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint32m8_t test___riscv_vsub(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint64m1_t test___riscv_vsub(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint64m2_t test___riscv_vsub(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint64m4_t test___riscv_vsub(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint64m8_t test___riscv_vsub(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8mf8_t test___riscv_vsub(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8mf4_t test___riscv_vsub(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8mf2_t test___riscv_vsub(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8m1_t test___riscv_vsub(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8m2_t test___riscv_vsub(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8m4_t test___riscv_vsub(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint8m8_t test___riscv_vsub(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vsub(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vsub(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint16m1_t test___riscv_vsub(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint16m2_t test___riscv_vsub(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint16m4_t test___riscv_vsub(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint16m8_t test___riscv_vsub(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vsub(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint32m1_t test___riscv_vsub(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint32m2_t test___riscv_vsub(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint32m4_t test___riscv_vsub(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint32m8_t test___riscv_vsub(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint64m1_t test___riscv_vsub(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint64m2_t test___riscv_vsub(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint64m4_t test___riscv_vsub(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vuint64m8_t test___riscv_vsub(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(op1,op2,32); +} + + +vint8mf8_t test___riscv_vsub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vsub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vsub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vsub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vsub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vsub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vsub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vsub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vsub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vsub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vsub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vsub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vsub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vsub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vsub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vsub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vsub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vsub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vsub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vsub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vsub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vsub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vsub(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vsub(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vsub(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8m1_t test___riscv_vsub(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8m2_t test___riscv_vsub(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8m4_t test___riscv_vsub(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint8m8_t test___riscv_vsub(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vsub(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vsub(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vsub(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vsub(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vsub(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vsub(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vsub(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vsub(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vsub(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vsub(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vsub(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vsub(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vsub(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vsub(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vsub(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-1.C new file mode 100644 index 00000000000..be890dfe844 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vsub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vsub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vsub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vsub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vsub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vsub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vsub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vsub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vsub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vsub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vsub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vsub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vsub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vsub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vsub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vsub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vsub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vsub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vsub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vsub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vsub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vsub_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vsub_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vsub_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vsub_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vsub_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vsub_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vsub_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vsub_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vsub_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vsub_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vsub_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vsub_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vsub_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vsub_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vsub_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vsub_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-2.C new file mode 100644 index 00000000000..590e02e326c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vsub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vsub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vsub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vsub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vsub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vsub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vsub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vsub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vsub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vsub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vsub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vsub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vsub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vsub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vsub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vsub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vsub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vsub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vsub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vsub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vsub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vsub_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vsub_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vsub_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vsub_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vsub_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vsub_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vsub_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vsub_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vsub_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vsub_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vsub_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vsub_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vsub_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vsub_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vsub_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vsub_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-3.C new file mode 100644 index 00000000000..ef82b81ba0f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vsub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vsub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vsub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vsub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vsub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vsub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vsub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vsub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vsub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vsub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vsub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vsub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vsub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vsub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vsub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vsub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vsub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vsub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vsub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vsub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vsub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vsub_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vsub_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vsub_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vsub_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vsub_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vsub_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vsub_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vsub_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vsub_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vsub_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vsub_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vsub_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vsub_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vsub_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vsub_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vsub_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-1.C new file mode 100644 index 00000000000..c6105afc9d6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vsub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vsub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vsub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vsub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vsub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vsub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vsub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vsub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vsub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vsub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vsub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vsub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vsub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vsub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vsub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vsub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vsub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vsub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vsub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vsub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vsub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vsub_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vsub_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vsub_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vsub_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vsub_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vsub_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vsub_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vsub_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vsub_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vsub_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vsub_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vsub_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vsub_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vsub_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vsub_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vsub_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-2.C new file mode 100644 index 00000000000..cb37b528de9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vsub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vsub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vsub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vsub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vsub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vsub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vsub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vsub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vsub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vsub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vsub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vsub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vsub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vsub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vsub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vsub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vsub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vsub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vsub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vsub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vsub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vsub_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vsub_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vsub_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vsub_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vsub_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vsub_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vsub_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vsub_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vsub_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vsub_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vsub_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vsub_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vsub_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vsub_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vsub_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vsub_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-3.C new file mode 100644 index 00000000000..23927091edb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vsub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vsub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vsub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vsub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vsub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vsub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vsub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vsub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vsub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vsub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vsub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vsub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vsub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vsub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vsub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vsub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vsub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vsub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vsub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vsub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vsub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vsub_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vsub_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vsub_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vsub_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vsub_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vsub_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vsub_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vsub_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vsub_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vsub_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vsub_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vsub_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vsub_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vsub_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vsub_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vsub_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-1.C new file mode 100644 index 00000000000..9863520e23c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-2.C new file mode 100644 index 00000000000..45797e4e46f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-3.C new file mode 100644 index 00000000000..873d672b213 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-1.C new file mode 100644 index 00000000000..1f736a0515c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-2.C new file mode 100644 index 00000000000..965a40b659d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-3.C new file mode 100644 index 00000000000..53e99f5e766 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-1.C new file mode 100644 index 00000000000..44c1d048c33 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-2.C new file mode 100644 index 00000000000..fa4a97f70ec --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-3.C new file mode 100644 index 00000000000..e23fb659827 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-1.C new file mode 100644 index 00000000000..6f90d3595b2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-2.C new file mode 100644 index 00000000000..cc5b52b32db --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-3.C new file mode 100644 index 00000000000..899316f4ef8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vsub_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */