diff mbox series

RISC-V: Add shift constraint tests

Message ID 20230131221513.22652-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Add shift constraint tests |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai Jan. 31, 2023, 10:15 p.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: New test.

---
 .../riscv/rvv/base/shift_vx_constraint-1.c    | 133 ++++++++++++++++++
 1 file changed, 133 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c

Comments

Kito Cheng Feb. 3, 2023, 7:16 a.m. UTC | #1 
committed, thanks!

On Wed, Feb 1, 2023 at 6:15 AM <juzhe.zhong@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: New test.
>
> ---
>  .../riscv/rvv/base/shift_vx_constraint-1.c    | 133 ++++++++++++++++++
>  1 file changed, 133 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
> new file mode 100644
> index 00000000000..ae3883c5af9
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
> @@ -0,0 +1,133 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +#include "riscv_vector.h"
> +
> +/*
> +** f1:
> +**     vsetivli\tzero,4,e32,m1,tu,ma
> +**     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
> +**     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
> +**     vsll\.vi\tv[0-9]+,\s*v[0-9]+,31
> +**     vsll\.vi\tv[0-9]+,\s*v[0-9]+,31
> +**     vse32\.v\tv[0-9]+,0\([a-x0-9]+\)
> +**     ret
> +*/
> +void f1 (void * in, void *out)
> +{
> +    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
> +    vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
> +    vint32m1_t v3 = __riscv_vsll_vx_i32m1 (v2, 31, 4);
> +    vint32m1_t v4 = __riscv_vsll_vx_i32m1_tu (v3, v2, 31, 4);
> +    __riscv_vse32_v_i32m1 (out, v4, 4);
> +}
> +
> +/*
> +** f2:
> +**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
> +**     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
> +**     ...
> +**     vsetivli\tzero,4,e32,m1,ta,ma
> +**     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
> +**     vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
> +**     vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
> +**     vse32.v\tv[0-9]+,0\([a-x0-9]+\)
> +**     ret
> +*/
> +void f2 (void * in, void *out)
> +{
> +    vbool32_t mask = *(vbool32_t*)in;
> +    asm volatile ("":::"memory");
> +    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
> +    vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
> +    vint32m1_t v3 = __riscv_vsll_vx_i32m1 (v2, 32, 4);
> +    vint32m1_t v4 = __riscv_vsll_vx_i32m1_m (mask, v3, 32, 4);
> +    __riscv_vse32_v_i32m1 (out, v4, 4);
> +}
> +
> +/*
> +** f3:
> +**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
> +**     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
> +**     vsetivli\tzero,4,e32,m1,tu,mu
> +**     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
> +**     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
> +**     vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*17
> +**     vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*17,\s*v0.t
> +**     vse32.v\tv[0-9]+,0\([a-x0-9]+\)
> +**     ret
> +*/
> +void f3 (void * in, void *out)
> +{
> +    vbool32_t mask = *(vbool32_t*)in;
> +    asm volatile ("":::"memory");
> +    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
> +    vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
> +    vint32m1_t v3 = __riscv_vsll_vx_i32m1 (v2, 17, 4);
> +    vint32m1_t v4 = __riscv_vsll_vx_i32m1_tumu (mask, v3, v2, 17, 4);
> +    __riscv_vse32_v_i32m1 (out, v4, 4);
> +}
> +
> +/*
> +** f4:
> +**     vsetivli\tzero,4,e8,mf8,tu,ma
> +**     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
> +**     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
> +**     vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
> +**     vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
> +**     vse8\.v\tv[0-9]+,0\([a-x0-9]+\)
> +**     ret
> +*/
> +void f4 (void * in, void *out, size_t x)
> +{
> +    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4);
> +    vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in, 4);
> +    vint8mf8_t v3 = __riscv_vsll_vx_i8mf8 (v2, x, 4);
> +    vint8mf8_t v4 = __riscv_vsll_vx_i8mf8_tu (v3, v2, x, 4);
> +    __riscv_vse8_v_i8mf8 (out, v4, 4);
> +}
> +
> +/*
> +** f5:
> +**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
> +**     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
> +**     vsetivli\tzero,4,e8,mf8,ta,ma
> +**     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
> +**     vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*5
> +**     vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*5,\s*v0.t
> +**     vse8.v\tv[0-9]+,0\([a-x0-9]+\)
> +**     ret
> +*/
> +void f5 (void * in, void *out)
> +{
> +    vbool64_t mask = *(vbool64_t*)in;
> +    asm volatile ("":::"memory");
> +    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4);
> +    vint8mf8_t v2 = __riscv_vle8_v_i8mf8_m (mask, in, 4);
> +    vint8mf8_t v3 = __riscv_vsll_vx_i8mf8 (v2, 5, 4);
> +    vint8mf8_t v4 = __riscv_vsll_vx_i8mf8_m (mask, v3, 5, 4);
> +    __riscv_vse8_v_i8mf8 (out, v4, 4);
> +}
> +
> +/*
> +** f6:
> +**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
> +**     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
> +**     vsetivli\tzero,4,e8,mf8,tu,mu
> +**     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
> +**     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
> +**     vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
> +**     vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
> +**     vse8.v\tv[0-9]+,0\([a-x0-9]+\)
> +**     ret
> +*/
> +void f6 (void * in, void *out, size_t x)
> +{
> +    vbool64_t mask = *(vbool64_t*)in;
> +    asm volatile ("":::"memory");
> +    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4);
> +    vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tumu (mask, v, in, 4);
> +    vint8mf8_t v3 = __riscv_vsll_vx_i8mf8 (v2, x, 4);
> +    vint8mf8_t v4 = __riscv_vsll_vx_i8mf8_tumu (mask, v3, v2, x, 4);
> +    __riscv_vse8_v_i8mf8 (out, v4, 4);
> +}
> --
> 2.36.3
>
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
new file mode 100644
index 00000000000..ae3883c5af9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
@@ -0,0 +1,133 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_vector.h"
+
+/*
+** f1:
+**	vsetivli\tzero,4,e32,m1,tu,ma
+**	vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	vsll\.vi\tv[0-9]+,\s*v[0-9]+,31
+**	vsll\.vi\tv[0-9]+,\s*v[0-9]+,31
+**	vse32\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f1 (void * in, void *out)
+{
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+    vint32m1_t v3 = __riscv_vsll_vx_i32m1 (v2, 31, 4);
+    vint32m1_t v4 = __riscv_vsll_vx_i32m1_tu (v3, v2, 31, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+**	vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**	vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**	...
+**	vsetivli\tzero,4,e32,m1,ta,ma
+**	vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	vse32.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f2 (void * in, void *out)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+    vint32m1_t v3 = __riscv_vsll_vx_i32m1 (v2, 32, 4);
+    vint32m1_t v4 = __riscv_vsll_vx_i32m1_m (mask, v3, 32, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+**	vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**	vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**	vsetivli\tzero,4,e32,m1,tu,mu
+**	vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*17
+**	vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*17,\s*v0.t
+**	vse32.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f3 (void * in, void *out)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+    vint32m1_t v3 = __riscv_vsll_vx_i32m1 (v2, 17, 4);
+    vint32m1_t v4 = __riscv_vsll_vx_i32m1_tumu (mask, v3, v2, 17, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f4:
+**	vsetivli\tzero,4,e8,mf8,tu,ma
+**	vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vse8\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f4 (void * in, void *out, size_t x)
+{
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4);
+    vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in, 4);
+    vint8mf8_t v3 = __riscv_vsll_vx_i8mf8 (v2, x, 4);
+    vint8mf8_t v4 = __riscv_vsll_vx_i8mf8_tu (v3, v2, x, 4);
+    __riscv_vse8_v_i8mf8 (out, v4, 4);
+}
+
+/*
+** f5:
+**	vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**	vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**	vsetivli\tzero,4,e8,mf8,ta,ma
+**	vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*5
+**	vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*5,\s*v0.t
+**	vse8.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f5 (void * in, void *out)
+{
+    vbool64_t mask = *(vbool64_t*)in;
+    asm volatile ("":::"memory");
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4);
+    vint8mf8_t v2 = __riscv_vle8_v_i8mf8_m (mask, in, 4);
+    vint8mf8_t v3 = __riscv_vsll_vx_i8mf8 (v2, 5, 4);
+    vint8mf8_t v4 = __riscv_vsll_vx_i8mf8_m (mask, v3, 5, 4);
+    __riscv_vse8_v_i8mf8 (out, v4, 4);
+}
+
+/*
+** f6:
+**	vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**	vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**	vsetivli\tzero,4,e8,mf8,tu,mu
+**	vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	vse8.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f6 (void * in, void *out, size_t x)
+{
+    vbool64_t mask = *(vbool64_t*)in;
+    asm volatile ("":::"memory");
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4);
+    vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tumu (mask, v, in, 4);
+    vint8mf8_t v3 = __riscv_vsll_vx_i8mf8 (v2, x, 4);
+    vint8mf8_t v4 = __riscv_vsll_vx_i8mf8_tumu (mask, v3, v2, x, 4);
+    __riscv_vse8_v_i8mf8 (out, v4, 4);
+}