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[8.43.85.97]) by mx.google.com with ESMTPS id f7-20020a1709063f4700b0087943d5ca70si287446ejj.89.2023.01.26.10.39.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 10:39:33 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=fail header.i=@dinux.eu header.s=default header.b=aaeQYmyl; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9A5C23858023 for ; Thu, 26 Jan 2023 18:39:19 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server28.superhosting.bg (server28.superhosting.bg [217.174.156.11]) by sourceware.org (Postfix) with ESMTPS id B9DAA3858D28 for ; Thu, 26 Jan 2023 18:38:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B9DAA3858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dinux.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dinux.eu DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=dinux.eu; s=default; h=Content-Transfer-Encoding:MIME-Version:Message-Id:Date:Subject: Cc:To:From:Sender:Reply-To:Content-Type:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: In-Reply-To:References:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=zmRnSrBc9hdD7X41RjeEJbRsMZn4vnBtFBknq7aG24s=; b=aaeQYmylDd7ulHJyNhjHa1Pd7o T/nv1r/2KjsjueckhacWDcrHb2f6TSoswwWj1/Jm/c1iinVwjReEiOKp5k//Bl9tfRX5ZXO38gRMS V18hTbwxGqyjyYo/r2jb4IKtZTNF2QrYhd83SrcaSoETrPr9HhYIUQ6i0BtQR3ykhSoufcV55CbI2 zuZML9EtwlOpWcqMCplsVQLGo3S8JWTLaOLEMHFjt9+0+1ZFHSsT9F0wcNzBX2535OgYa35V3RYhf PSPdmU2oZPv2HrD0+M7LbuQYmkL+Mi95VXNLF7Zoc5LeQXoEJPxmgtCSGBCaXIU0LjOCbrt2r/e2/ DNg/xp3w==; Received: from [95.42.20.142] (port=57406 helo=kendros.lan) by server28.superhosting.bg with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pL793-0009ZU-88; Thu, 26 Jan 2023 20:38:47 +0200 From: Dimitar Dimitrov To: gcc-patches@gcc.gnu.org Cc: Dimitar Dimitrov Subject: [GCC-12][committed] pru: Fix CLZ expansion for QI and HI modes Date: Thu, 26 Jan 2023 20:38:24 +0200 Message-Id: <20230126183824.285183-1-dimitar@dinux.eu> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server28.superhosting.bg X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - dinux.eu X-Get-Message-Sender-Via: server28.superhosting.bg: authenticated_id: dimitar@dinux.eu X-Authenticated-Sender: server28.superhosting.bg: dimitar@dinux.eu X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756111436887311702?= X-GMAIL-MSGID: =?utf-8?q?1756111436887311702?= The recent gcc.dg/tree-ssa/clz-char.c test case failed for PRU target, exposing a wrong code generation bug in the PRU backend. The "clz" pattern did not produce correct output for QI and HI input operand modes. SI mode is ok. The "clz" pattern is expanded to an LMBD instruction to get the left-most bit position having value "1". In turn, to get the correct "clz" value, that bit position must be subtracted from the MSB bit position of the input operand. The old behaviour of hard-coding 31 for MSB bit position is wrong. The LMBD instruction returns 32 if input operand is zero, irrespective of its register mode. This maps nicely for SI mode, where the "clz" pattern outputs -1. It also leads to peculiar (but valid!) output values from the "clz" pattern for QI and HI zero-valued inputs. The corresponding commit in trunk contains two new test cases, which have been removed here because they depend on r13-5195-g4798080d4a3530. Regtested for pru-unknown-elf. gcc/ChangeLog: * config/pru/pru.h (CLZ_DEFINED_VALUE_AT_ZERO): Fix value for QI and HI input modes. * config/pru/pru.md (clz): Fix generated code for QI and HI input modes. Signed-off-by: Dimitar Dimitrov (cherry picked from commit c517295940a23db8ca165dfd5d0edea4457eda49) --- gcc/config/pru/pru.h | 5 +++-- gcc/config/pru/pru.md | 15 ++++++++++++--- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/gcc/config/pru/pru.h b/gcc/config/pru/pru.h index 4c35a7d7ee3..41260b9450d 100644 --- a/gcc/config/pru/pru.h +++ b/gcc/config/pru/pru.h @@ -562,8 +562,9 @@ do { \ #define CASE_VECTOR_MODE Pmode -/* See definition of clz pattern for rationale of value -1. */ -#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 2) +/* See definition of clz pattern for rationale of the value. */ +#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ + ((VALUE) = GET_MODE_BITSIZE (MODE) - 1 - 32, 2) /* Jumps are cheap on PRU. */ #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md index e6cfa8ec3bf..c5661adb6c4 100644 --- a/gcc/config/pru/pru.md +++ b/gcc/config/pru/pru.md @@ -1035,8 +1035,16 @@ (define_insn "pru_halt" [(set_attr "type" "control")]) ;; Count Leading Zeros implemented using LMBD. -;; LMBD returns 32 if bit value is not present, and we subtract 31 to get CLZ. -;; Hence we get a defined value -1 for CLZ_DEFINED_VALUE_AT_ZERO. +;; +;; LMBD returns 32 if bit value is not present, for any kind of input MODE. +;; The LMBD's search result for a "1" bit is subtracted from the +;; mode bit size minus one, in order to get CLZ. +;; +;; Hence for SImode we get a defined value -1 for CLZ_DEFINED_VALUE_AT_ZERO. +;; +;; The QImode and HImode defined values for zero inputs end up to be +;; non-standard (-25 and -17). But this is considered acceptable in +;; order to keep the CLZ expansion to only two instructions. (define_expand "clz2" [(set (match_operand:QISI 0 "register_operand") (clz:QISI (match_operand:QISI 1 "register_operand")))] @@ -1047,7 +1055,8 @@ (define_expand "clz2" rtx tmpval = gen_reg_rtx (mode); emit_insn (gen_pru_lmbd (mode, tmpval, src, const1_rtx)); - emit_insn (gen_sub3_insn (dst, GEN_INT (31), tmpval)); + int msb_bitn = GET_MODE_BITSIZE (mode) - 1; + emit_insn (gen_sub3_insn (dst, GEN_INT (msb_bitn), tmpval)); DONE; })