diff mbox series

RISC-V: Finalize testcases for final version VSETVL PASS.

Message ID 20230118032915.71849-1-juzhe.zhong@rivai.ai
State Unresolved
Headers
Series RISC-V: Finalize testcases for final version VSETVL PASS. |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

juzhe.zhong@rivai.ai Jan. 18, 2023, 3:29 a.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/vsetvl/avl_single-14.c: Adjust for final implementation.
        * gcc.target/riscv/rvv/vsetvl/avl_single-23.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/avl_single-30.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/avl_single-44.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/avl_single-47.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/avl_single-50.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/avl_single-51.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/avl_single-6.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/avl_single-65.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/avl_single-66.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/avl_single-67.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/avl_single-68.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/avl_single-71.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/avl_single-72.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/avl_single-9.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-73.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-74.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-75.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvl-10.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvl-11.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvl-12.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvl-13.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvl-14.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvl-15.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvl-16.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvl-18.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvl-19.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvl-2.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvl-20.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvl-3.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvl-4.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvl-5.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvl-6.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvl-7.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvl-8.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvl-9.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c: New test.
        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c: New test.

---
 .../riscv/rvv/vsetvl/avl_multiple-1.c         | 35 +++++++++
 .../riscv/rvv/vsetvl/avl_multiple-10.c        | 73 ++++++++++++++++++
 .../riscv/rvv/vsetvl/avl_multiple-11.c        | 40 ++++++++++
 .../riscv/rvv/vsetvl/avl_multiple-12.c        | 39 ++++++++++
 .../riscv/rvv/vsetvl/avl_multiple-13.c        | 46 ++++++++++++
 .../riscv/rvv/vsetvl/avl_multiple-14.c        | 66 +++++++++++++++++
 .../riscv/rvv/vsetvl/avl_multiple-15.c        | 67 +++++++++++++++++
 .../riscv/rvv/vsetvl/avl_multiple-16.c        | 67 +++++++++++++++++
 .../riscv/rvv/vsetvl/avl_multiple-2.c         | 35 +++++++++
 .../riscv/rvv/vsetvl/avl_multiple-3.c         | 39 ++++++++++
 .../riscv/rvv/vsetvl/avl_multiple-4.c         | 38 ++++++++++
 .../riscv/rvv/vsetvl/avl_multiple-5.c         | 40 ++++++++++
 .../riscv/rvv/vsetvl/avl_multiple-6.c         | 40 ++++++++++
 .../riscv/rvv/vsetvl/avl_multiple-7.c         | 40 ++++++++++
 .../riscv/rvv/vsetvl/avl_multiple-8.c         | 39 ++++++++++
 .../riscv/rvv/vsetvl/avl_multiple-9.c         | 74 +++++++++++++++++++
 .../riscv/rvv/vsetvl/avl_single-14.c          |  4 +-
 .../riscv/rvv/vsetvl/avl_single-23.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-30.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-44.c          |  3 +-
 .../riscv/rvv/vsetvl/avl_single-47.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-50.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-51.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-6.c           |  4 +-
 .../riscv/rvv/vsetvl/avl_single-65.c          |  4 +-
 .../riscv/rvv/vsetvl/avl_single-66.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-67.c          |  5 +-
 .../riscv/rvv/vsetvl/avl_single-68.c          |  5 +-
 .../riscv/rvv/vsetvl/avl_single-71.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-72.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-73.c          | 25 +++++++
 .../riscv/rvv/vsetvl/avl_single-74.c          | 27 +++++++
 .../riscv/rvv/vsetvl/avl_single-75.c          | 27 +++++++
 .../riscv/rvv/vsetvl/avl_single-9.c           |  1 +
 .../riscv/rvv/vsetvl/imm_bb_prop-2.c          |  2 +-
 .../riscv/rvv/vsetvl/imm_bb_prop-3.c          |  2 +-
 .../riscv/rvv/vsetvl/imm_bb_prop-4.c          |  2 +-
 .../riscv/rvv/vsetvl/imm_conflict-4.c         | 10 +--
 .../riscv/rvv/vsetvl/imm_conflict-5.c         | 10 +--
 .../riscv/rvv/vsetvl/vlmax_back_prop-13.c     |  6 +-
 .../riscv/rvv/vsetvl/vlmax_bb_prop-13.c       |  6 --
 .../riscv/rvv/vsetvl/vlmax_bb_prop-14.c       |  6 --
 .../riscv/rvv/vsetvl/vlmax_bb_prop-15.c       |  1 -
 .../riscv/rvv/vsetvl/vlmax_bb_prop-16.c       |  7 --
 .../riscv/rvv/vsetvl/vlmax_bb_prop-21.c       | 12 +--
 .../riscv/rvv/vsetvl/vlmax_bb_prop-22.c       | 12 +--
 .../riscv/rvv/vsetvl/vlmax_bb_prop-23.c       |  2 +-
 .../riscv/rvv/vsetvl/vlmax_bb_prop-24.c       | 14 ++--
 .../riscv/rvv/vsetvl/vlmax_bb_prop-5.c        | 12 +--
 .../riscv/rvv/vsetvl/vlmax_bb_prop-6.c        | 12 +--
 .../riscv/rvv/vsetvl/vlmax_bb_prop-7.c        |  2 +-
 .../riscv/rvv/vsetvl/vlmax_bb_prop-8.c        | 14 ++--
 .../riscv/rvv/vsetvl/vlmax_conflict-1.c       |  4 +-
 .../riscv/rvv/vsetvl/vlmax_conflict-6.c       |  1 -
 .../riscv/rvv/vsetvl/vlmax_miss_default-1.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_miss_default-10.c  |  1 -
 .../riscv/rvv/vsetvl/vlmax_miss_default-11.c  |  2 +-
 .../riscv/rvv/vsetvl/vlmax_miss_default-12.c  |  2 +-
 .../riscv/rvv/vsetvl/vlmax_miss_default-13.c  |  2 +-
 .../riscv/rvv/vsetvl/vlmax_miss_default-14.c  |  8 +-
 .../riscv/rvv/vsetvl/vlmax_miss_default-2.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_miss_default-3.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_miss_default-4.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_miss_default-5.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_miss_default-6.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_miss_default-7.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_miss_default-8.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_miss_default-9.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-10.c  |  1 -
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c    | 16 ++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-10.c   | 20 +++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-11.c   | 21 ++++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-12.c   | 21 ++++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c   | 22 ++++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-14.c   | 24 ++++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-15.c   | 22 ++++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-16.c   | 20 +++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-17.c   | 14 ++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c   | 19 +++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-19.c   | 22 ++++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-2.c    | 20 +++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-20.c   | 23 ++++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-3.c    | 21 ++++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-4.c    | 21 ++++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-5.c    | 17 +++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-6.c    | 22 ++++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-7.c    | 17 +++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-8.c    | 22 ++++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-9.c    | 20 +++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c | 17 +++++
 .../riscv/rvv/vsetvl/vsetvlmax-10.c           | 23 ++++++
 .../riscv/rvv/vsetvl/vsetvlmax-11.c           | 23 ++++++
 .../riscv/rvv/vsetvl/vsetvlmax-12.c           | 26 +++++++
 .../riscv/rvv/vsetvl/vsetvlmax-13.c           | 27 +++++++
 .../riscv/rvv/vsetvl/vsetvlmax-14.c           | 18 +++++
 .../riscv/rvv/vsetvl/vsetvlmax-15.c           | 23 ++++++
 .../riscv/rvv/vsetvl/vsetvlmax-16.c           | 14 ++++
 .../riscv/rvv/vsetvl/vsetvlmax-17.c           | 16 ++++
 .../riscv/rvv/vsetvl/vsetvlmax-18.c           | 19 +++++
 .../riscv/rvv/vsetvl/vsetvlmax-19.c           | 22 ++++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c | 21 ++++++
 .../riscv/rvv/vsetvl/vsetvlmax-20.c           | 19 +++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c | 16 ++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c | 21 ++++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c | 21 ++++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c | 22 ++++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c | 24 ++++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c | 22 ++++++
 .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c | 23 ++++++
 109 files changed, 1769 insertions(+), 122 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c
new file mode 100644
index 00000000000..ea0faf66818
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c
@@ -0,0 +1,35 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  size_t vl;
+  switch (cond)
+  {
+  case 1:
+    vl = 100;
+    break;
+  case 2:
+    vl = *(size_t*)(in + 100);
+    break;
+  case 3:
+    {
+      size_t new_vl = *(size_t*)(in + 500);
+      size_t new_vl2 = *(size_t*)(in + 600);
+      vl = new_vl + new_vl2 + 777;
+      break;
+    }
+  default:
+    vl = vl + 4000;
+    break;
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+      __riscv_vse8_v_i8mf8 (out + i, v, vl);
+    }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c
new file mode 100644
index 00000000000..664f3479f04
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c
@@ -0,0 +1,73 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int l, int n, int m, int cond)
+{
+  size_t vl;
+  switch (cond)
+  {
+  case 1:
+    vl = 100;
+    break;
+  case 2:
+    vl = *(size_t*)(in + 100);
+    break;
+  case 3:
+    {
+      size_t new_vl = *(size_t*)(in + 500);
+      size_t new_vl2 = *(size_t*)(in + 600);
+      vl = new_vl + new_vl2 + 777;
+      break;
+    }
+  default:
+    break;
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v1 = __riscv_vle8_v_i8mf8 (in + i + 1, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 1, v1, vl);
+
+      vint8mf8_t v2 = __riscv_vle8_v_i8mf8 (in + i + 2, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 2, v2, vl);
+
+      vint8mf8_t v3 = __riscv_vle8_v_i8mf8 (in + i + 3, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 3, v3, vl);
+
+      vint8mf8_t v4 = __riscv_vle8_v_i8mf8 (in + i + 4, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 4, v4, vl);
+
+      vint8mf8_t v5 = __riscv_vle8_v_i8mf8 (in + i + 5, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 5, v5, vl);
+
+      vint8mf8_t v6 = __riscv_vle8_v_i8mf8 (in + i + 6, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 6, v6, vl);
+
+      vint8mf8_t v7 = __riscv_vle8_v_i8mf8 (in + i + 7, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 7, v7, vl);
+
+      vint8mf8_t v8 = __riscv_vle8_v_i8mf8 (in + i + 8, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 8, v8, vl);
+
+      vint8mf8_t v9 = __riscv_vle8_v_i8mf8 (in + i + 9, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 9, v9, vl);
+
+      vint8mf8_t v10 = __riscv_vle8_v_i8mf8 (in + i + 10, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 10, v10, vl);
+
+      vint8mf8_t v11 = __riscv_vle8_v_i8mf8 (in + i + 11, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 11, v11, vl);
+
+      vint8mf8_t v12 = __riscv_vle8_v_i8mf8 (in + i + 12, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 12, v12, vl);
+
+      vint8mf8_t v13 = __riscv_vle8_v_i8mf8 (in + i + 13, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 13, v13, vl);
+
+      vint8mf8_t v14 = __riscv_vle8_v_i8mf8 (in + i + 14, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 14, v14, vl);
+    }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c
new file mode 100644
index 00000000000..91812c90d7b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c
@@ -0,0 +1,40 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  size_t vl;
+  switch (cond)
+  {
+  case 1:
+    vl = 100;
+    break;
+  case 2:
+    vl = *(size_t*)(in + 100);
+    break;
+  case 3:
+    {
+      size_t new_vl = *(size_t*)(in + 500);
+      size_t new_vl2 = *(size_t*)(in + 600);
+      vl = new_vl + new_vl2 + 777;
+      break;
+    }
+  default:
+    vl = vl + 4000;
+    break;
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+      __riscv_vse8_v_i8mf8 (out + i, v, vl);
+      
+      vint8mf2_t v2 = __riscv_vle8_v_i8mf2 (in + i + 100, vl);
+      __riscv_vse8_v_i8mf2 (out + i + 100, v2, vl);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c
new file mode 100644
index 00000000000..a7a62bd2a3f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c
@@ -0,0 +1,39 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  size_t vl;
+  switch (cond)
+  {
+  case 1:
+    vl = 100;
+    break;
+  case 2:
+    vl = *(size_t*)(in + 100);
+    break;
+  case 3:
+    {
+      size_t new_vl = *(size_t*)(in + 500);
+      size_t new_vl2 = *(size_t*)(in + 600);
+      vl = new_vl + new_vl2 + 777;
+      break;
+    }
+  default:
+    vl = vl + 4000;
+    break;
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+      __riscv_vse8_v_i8mf8 (out + i, v, vl);
+      
+      vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl);
+    }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c
new file mode 100644
index 00000000000..fb1cbc5e176
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c
@@ -0,0 +1,46 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  size_t vl;
+  switch (cond)
+  {
+  case 1:
+    vl = 100;
+    break;
+  case 2:
+    vl = *(size_t*)(in + 100);
+    break;
+  case 3:
+    {
+      size_t new_vl = *(size_t*)(in + 500);
+      size_t new_vl2 = *(size_t*)(in + 600);
+      vl = new_vl + new_vl2 + 777;
+      break;
+    }
+  default:
+    vl = vl + 4000;
+    break;
+  }
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+      __riscv_vse8_v_i8mf8 (out + i, v, vl);
+      
+      vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl);
+    }
+  
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 300, v, vl);
+      vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 200, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 200, v2, vl);
+    }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c
new file mode 100644
index 00000000000..5ede182c36d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c
@@ -0,0 +1,66 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n, int m, int cond, int cond2)
+{
+  size_t vl;
+  switch (cond)
+  {
+  case 1:
+    vl = 100;
+    break;
+  case 2:
+    vl = *(size_t*)(in + 100);
+    break;
+  case 3:
+    {
+      size_t new_vl = *(size_t*)(in + 500);
+      size_t new_vl2 = *(size_t*)(in + 600);
+      vl = new_vl + new_vl2 + 777;
+      break;
+    }
+  default:
+    vl = 4000;
+    break;
+  }
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+      __riscv_vse8_v_i8mf8 (out + i, v, vl);
+      
+      vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl);
+    }
+  
+  size_t vl2;
+  switch (cond)
+  {
+  case 1:
+    vl2 = 100;
+    break;
+  case 2:
+    vl2 = *(size_t*)(in + 100);
+    break;
+  case 3:
+    {
+      size_t new_vl = *(size_t*)(in + 500);
+      size_t new_vl2 = *(size_t*)(in + 600);
+      vl2 = new_vl + new_vl2 + 777;
+      break;
+    }
+  default:
+  vl2 = 4000;
+    break;
+  }
+
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl2);
+      __riscv_vse8_v_i8mf8 (out + i + 300, v, vl2);
+      vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 200, vl2);
+      __riscv_vse8_v_i8mf8 (out + i + 200, v2, vl2);
+    }
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c
new file mode 100644
index 00000000000..884d69ccde3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c
@@ -0,0 +1,67 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n, int m, int cond, int cond2)
+{
+  size_t vl;
+  switch (cond)
+  {
+  case 1:
+    vl = 100;
+    break;
+  case 2:
+    vl = *(size_t*)(in + 100);
+    break;
+  case 3:
+    {
+      size_t new_vl = *(size_t*)(in + 500);
+      size_t new_vl2 = *(size_t*)(in + 600);
+      vl = new_vl + new_vl2 + 777;
+      break;
+    }
+  default:
+    vl = 4000;
+    break;
+  }
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+      __riscv_vse8_v_i8mf8 (out + i, v, vl);
+      
+      vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl);
+    }
+  
+  size_t vl2;
+  switch (cond2)
+  {
+  case 1:
+    vl2 = 100;
+    break;
+  case 2:
+    vl2 = *(size_t*)(in + 100);
+    break;
+  case 3:
+    {
+      size_t new_vl = *(size_t*)(in + 500);
+      size_t new_vl2 = *(size_t*)(in + 600);
+      vl2 = new_vl + new_vl2 + 777;
+      break;
+    }
+  default:
+    vl2 = 4000;
+    break;
+  }
+
+  for (size_t i = 0; i < m; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl2);
+      __riscv_vse8_v_i8mf8 (out + i + 300, v, vl2);
+      vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 200, vl2);
+      __riscv_vse8_v_i8mf8 (out + i + 200, v2, vl2);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c
new file mode 100644
index 00000000000..c8352bb9223
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c
@@ -0,0 +1,67 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n, int m, int cond, int cond2)
+{
+  size_t vl;
+  switch (cond)
+  {
+  case 1:
+    vl = 100;
+    break;
+  case 2:
+    vl = *(size_t*)(in + 100);
+    break;
+  case 3:
+    {
+      size_t new_vl = *(size_t*)(in + 500);
+      size_t new_vl2 = *(size_t*)(in + 600);
+      vl = new_vl + new_vl2 + 777;
+      break;
+    }
+  default:
+    vl = 4000;
+    break;
+  }
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+      __riscv_vse8_v_i8mf8 (out + i, v, vl);
+      
+      vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl);
+    }
+  
+  size_t vl2;
+  switch (cond)
+  {
+  case 1:
+    vl2 = 100;
+    break;
+  case 2:
+    vl2 = *(size_t*)(in + 100);
+    break;
+  case 3:
+    {
+      size_t new_vl = *(size_t*)(in + 500);
+      size_t new_vl2 = *(size_t*)(in + 600);
+      vl2 = new_vl + new_vl2 + 777;
+      break;
+    }
+  default:
+  vl = 3000;
+    break;
+  }
+
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl2);
+      __riscv_vse8_v_i8mf8 (out + i + 300, v, vl2);
+      vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 200, vl2);
+      __riscv_vse8_v_i8mf8 (out + i + 200, v2, vl2);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c
new file mode 100644
index 00000000000..9c0af9a34f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c
@@ -0,0 +1,35 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  size_t vl;
+  switch (cond)
+  {
+  case 1:
+    vl = 100;
+    break;
+  case 2:
+    vl = *(size_t*)(in + 100);
+    break;
+  case 3:
+    {
+      size_t new_vl = *(size_t*)(in + 500);
+      size_t new_vl2 = *(size_t*)(in + 600);
+      vl = new_vl + new_vl2 + 777;
+      break;
+    }
+  default:
+    break;
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+      __riscv_vse8_v_i8mf8 (out + i, v, vl);
+    }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c
new file mode 100644
index 00000000000..a39638879a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c
@@ -0,0 +1,39 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int l, int n, int m, int cond)
+{
+  size_t vl;
+  switch (cond)
+  {
+  case 1:
+    vl = 100;
+    break;
+  case 2:
+    vl = *(size_t*)(in + 100);
+    break;
+  case 3:
+    {
+      size_t new_vl = *(size_t*)(in + 500);
+      size_t new_vl2 = *(size_t*)(in + 600);
+      vl = new_vl + new_vl2 + 777;
+      break;
+    }
+  default:
+    vl = vl + 4000;
+    break;
+  }
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl);
+          __riscv_vse8_v_i8mf8 (out + i + j, v, vl);
+        }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c
new file mode 100644
index 00000000000..f41ddb75001
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c
@@ -0,0 +1,38 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int l, int n, int m, int cond)
+{
+  size_t vl;
+  switch (cond)
+  {
+  case 1:
+    vl = 100;
+    break;
+  case 2:
+    vl = *(size_t*)(in + 100);
+    break;
+  case 3:
+    {
+      size_t new_vl = *(size_t*)(in + 500);
+      size_t new_vl2 = *(size_t*)(in + 600);
+      vl = new_vl + new_vl2 + 777;
+      break;
+    }
+  default:
+    break;
+  }
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl);
+          __riscv_vse8_v_i8mf8 (out + i + j, v, vl);
+        }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c
new file mode 100644
index 00000000000..374b7af1073
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c
@@ -0,0 +1,40 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int l, int n, int m, int cond)
+{
+  size_t vl;
+  switch (cond)
+  {
+  case 1:
+    vl = 100;
+    break;
+  case 2:
+    vl = *(size_t*)(in + 100);
+    break;
+  case 3:
+    {
+      size_t new_vl = *(size_t*)(in + 500);
+      size_t new_vl2 = *(size_t*)(in + 600);
+      vl = new_vl + new_vl2 + 777;
+      break;
+    }
+  default:
+    vl = vl + 4000;
+    break;
+  }
+  for (int i = 0; i < l; i++){
+    vl++;
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl);
+          __riscv_vse8_v_i8mf8 (out + i + j, v, vl);
+        }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c
new file mode 100644
index 00000000000..efd1e4efdaa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c
@@ -0,0 +1,40 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int l, int n, int m, int cond)
+{
+  size_t vl;
+  switch (cond)
+  {
+  case 1:
+    vl = 100;
+    break;
+  case 2:
+    vl = *(size_t*)(in + 100);
+    break;
+  case 3:
+    {
+      size_t new_vl = *(size_t*)(in + 500);
+      size_t new_vl2 = *(size_t*)(in + 600);
+      vl = new_vl + new_vl2 + 777;
+      break;
+    }
+  default:
+    break;
+  }
+  for (int i = 0; i < l; i++){
+    vl++;
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl);
+          __riscv_vse8_v_i8mf8 (out + i + j, v, vl);
+        }
+    }
+  }
+}
+
+
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c
new file mode 100644
index 00000000000..e855f86b9a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c
@@ -0,0 +1,40 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int l, int n, int m, int cond)
+{
+  size_t vl;
+  switch (cond)
+  {
+  case 1:
+    vl = 100;
+    break;
+  case 2:
+    vl = *(size_t*)(in + 100);
+    break;
+  case 3:
+    {
+      size_t new_vl = *(size_t*)(in + 500);
+      size_t new_vl2 = *(size_t*)(in + 600);
+      vl = new_vl + new_vl2 + 777;
+      break;
+    }
+  default:
+    vl = vl + 4000;
+    break;
+  }
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl);
+          __riscv_vse8_v_i8mf8 (out + i + j, v, vl);
+        }
+    }
+    vl++;
+  }
+}
+
+/* { dg-final { scan-assembler-times {add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c
new file mode 100644
index 00000000000..316a4ce6193
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c
@@ -0,0 +1,39 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int l, int n, int m, int cond)
+{
+  size_t vl;
+  switch (cond)
+  {
+  case 1:
+    vl = 100;
+    break;
+  case 2:
+    vl = *(size_t*)(in + 100);
+    break;
+  case 3:
+    {
+      size_t new_vl = *(size_t*)(in + 500);
+      size_t new_vl2 = *(size_t*)(in + 600);
+      vl = new_vl + new_vl2 + 777;
+      break;
+    }
+  default:
+    break;
+  }
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl);
+          __riscv_vse8_v_i8mf8 (out + i + j, v, vl);
+        }
+    }
+    vl++;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c
new file mode 100644
index 00000000000..60d3f0906c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c
@@ -0,0 +1,74 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int l, int n, int m, int cond)
+{
+  size_t vl;
+  switch (cond)
+  {
+  case 1:
+    vl = 100;
+    break;
+  case 2:
+    vl = *(size_t*)(in + 100);
+    break;
+  case 3:
+    {
+      size_t new_vl = *(size_t*)(in + 500);
+      size_t new_vl2 = *(size_t*)(in + 600);
+      vl = new_vl + new_vl2 + 777;
+      break;
+    }
+  default:
+    vl = vl + 4000;
+    break;
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v1 = __riscv_vle8_v_i8mf8 (in + i + 1, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 1, v1, vl);
+
+      vint8mf8_t v2 = __riscv_vle8_v_i8mf8 (in + i + 2, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 2, v2, vl);
+
+      vint8mf8_t v3 = __riscv_vle8_v_i8mf8 (in + i + 3, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 3, v3, vl);
+
+      vint8mf8_t v4 = __riscv_vle8_v_i8mf8 (in + i + 4, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 4, v4, vl);
+
+      vint8mf8_t v5 = __riscv_vle8_v_i8mf8 (in + i + 5, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 5, v5, vl);
+
+      vint8mf8_t v6 = __riscv_vle8_v_i8mf8 (in + i + 6, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 6, v6, vl);
+
+      vint8mf8_t v7 = __riscv_vle8_v_i8mf8 (in + i + 7, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 7, v7, vl);
+
+      vint8mf8_t v8 = __riscv_vle8_v_i8mf8 (in + i + 8, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 8, v8, vl);
+
+      vint8mf8_t v9 = __riscv_vle8_v_i8mf8 (in + i + 9, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 9, v9, vl);
+
+      vint8mf8_t v10 = __riscv_vle8_v_i8mf8 (in + i + 10, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 10, v10, vl);
+
+      vint8mf8_t v11 = __riscv_vle8_v_i8mf8 (in + i + 11, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 11, v11, vl);
+
+      vint8mf8_t v12 = __riscv_vle8_v_i8mf8 (in + i + 12, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 12, v12, vl);
+
+      vint8mf8_t v13 = __riscv_vle8_v_i8mf8 (in + i + 13, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 13, v13, vl);
+
+      vint8mf8_t v14 = __riscv_vle8_v_i8mf8 (in + i + 14, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 14, v14, vl);
+    }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c
index 501d14c6e2d..426754309e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c
@@ -23,5 +23,5 @@  void f (int8_t * restrict in, int8_t * restrict out, int n, int cond)
     }
 }
 
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c
index aa10b7724fe..6c2584c6ba2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c
@@ -29,6 +29,6 @@  void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int cond)
 
 /* { dg-final { scan-assembler {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
 /* { dg-final { scan-assembler {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
 /* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,101} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
 /* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,102} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c
index be5986e00a1..b5267b748e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c
@@ -25,5 +25,5 @@  void f (int8_t * restrict in, int8_t * restrict out, int n, int m, unsigned cond
     }
 }
 
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c
index 0f4d60e9adf..470c99e4ec4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c
@@ -15,5 +15,4 @@  void f(int8_t *base, int8_t *out, size_t vl, size_t m) {
   }
 }
 
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+j\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c
index 15ecb5d171a..935e1b10630 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c
@@ -31,5 +31,5 @@  void f (int8_t * restrict in, int8_t * restrict out, int n, int cond)
   }
 }
 
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c
index d91d2e0005c..0c8764334b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c
@@ -18,6 +18,6 @@  void f(void *base, void *out, void *mask_in, size_t m) {
     }
   }
 }
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c
index 0cb55ba28c6..d2ceab4c1c8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c
@@ -21,5 +21,5 @@  void f(void *base, void *out, void *mask_in, size_t m, size_t n) {
   }
 }
 
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c
index 02f62b46b20..db2f7500885 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c
@@ -17,6 +17,6 @@  void f (void * restrict in, void * restrict out, int l, int n, int m, size_t vl)
   }
 }
 
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+ble\s+[a-x0-9]+,\s*zero,\.L[0-9]+\s+\.L[0-9]+\:\s+add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
-
+/* { dg-final { scan-assembler-times {add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+li\s+[a-x0-9]+,0\s+vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-O2" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c
index 24d3300ccbf..c440b9b176b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c
@@ -29,5 +29,5 @@  void f (int8_t * restrict in, int8_t * restrict out, int n, int n2)
   }
 }
 
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
index f9073e65ff5..dfbb744d166 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
@@ -17,5 +17,5 @@  void f2 (void * restrict in, void * restrict out, int l, int n, int m, size_t vl
   }
 }
 
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+ble\s+[a-x0-9]+,\s*zero,\.L[0-9]+\s+\.L[0-9]+\:\s+add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c
index 3828afa9de8..b9f49b90de1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c
@@ -21,6 +21,7 @@  void f2 (void * restrict in, void * restrict out, int l, int n, int m)
   }
 }
 
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {addi\s+[a-x0-9]+,\s*[a-x0-9]+,\s*44} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c
index 71071729048..da6e5a8cc72 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c
@@ -21,5 +21,6 @@  void f2 (void * restrict in, void * restrict out, int l, int n, int m)
   }
 }
 
-/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {addi\s+[a-x0-9]+,\s*[a-x0-9]+,\s*44} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c
index 0f780a7cb55..06706d6bac3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c
@@ -50,5 +50,5 @@  void f (int8_t * restrict in, int8_t * restrict out, int l, int n, int m, size_t
   }
 }
 
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
index 866370f0618..d9c35cbb65d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
@@ -42,5 +42,5 @@  void f (int8_t * restrict in, int8_t * restrict out, int l, int n, int m, size_t
   }
 }
 
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c
new file mode 100644
index 00000000000..cd9bb802922
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c
@@ -0,0 +1,25 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int cond, size_t vl, size_t vl2)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 300, v, vl);
+    }
+  
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl2);
+      __riscv_vse8_v_i8mf8 (out + i, v, vl2);
+      
+      vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl2);
+      __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl2);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c
new file mode 100644
index 00000000000..568615aa7f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c
@@ -0,0 +1,27 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int cond, size_t vl, size_t vl2)
+{
+  if (cond)
+    vl = 101;
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 300, v, vl);
+    }
+  
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+      __riscv_vse8_v_i8mf8 (out + i, v, vl);
+      
+      vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c
new file mode 100644
index 00000000000..b7680ec98fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c
@@ -0,0 +1,27 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int cond, size_t vl, size_t vl2)
+{
+  if (cond)
+    vl = 101;
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 300, v, vl);
+    }
+  
+  vl = 101;
+  for (size_t i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+      __riscv_vse8_v_i8mf8 (out + i, v, vl);
+      
+      vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl);
+      __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl);
+    }
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c
index 0ecfb969685..8f47258d80b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c
@@ -54,3 +54,4 @@  void f (void * restrict in, void * restrict out, int l, int n, int m)
 
 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,32} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c
index 76ec7ae14ec..61bf57b5d42 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c
@@ -26,4 +26,4 @@  void f (int8_t * restrict in, int8_t * restrict out, int n, int n2)
 }
 
 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*9,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c
index 20a1cd27c43..3da7b8722c2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c
@@ -19,4 +19,4 @@  void f(void *base, void *out, void *mask_in, size_t vl, size_t m) {
   }
 }
 
-/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e16,\s*mf4,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e8,\s*mf8,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c
index 58aecb0a219..2a9616eb7ea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c
@@ -21,5 +21,5 @@  void f(void *base, void *out, void *mask_in, size_t vl, size_t m, size_t n) {
   }
 }
 
-/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e16,\s*mf4,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e8,\s*mf8,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c
index fdfcb07a63d..1671bb573f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c
@@ -30,9 +30,7 @@  void f (void * restrict in, void * restrict out, int n, int cond)
   }
 }
 
-/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*19,\s*e32,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*8,\s*e32,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os"  no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetivli} 5 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os"  no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*tu,\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler {vsetivli\s+zero,\s*19,\s*e32,\s*m1,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler {vsetivli\s+zero,\s*8,\s*e32,\s*m1,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os"  no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c
index 3e109c0c86a..c4e25f4600a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c
@@ -37,9 +37,7 @@  void f (void * restrict in, void * restrict out, int n, int cond)
   }
 }
 
-/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*19,\s*e32,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*8,\s*e32,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os"  no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetivli} 5 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os"  no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*tu,\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler {vsetivli\s+zero,\s*19,\s*e32,\s*m1,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler {vsetivli\s+zero,\s*8,\s*e32,\s*m1,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os"  no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c
index 31034bcfa25..b819029603c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c
@@ -22,8 +22,8 @@  void f (int32_t * restrict in, int32_t * restrict out, int n, int cond, int cond
     *(vfloat32mf2_t*)(out + i + 500) = v;
   }
   for (int i = 0; i < n; i++) {
-    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500 + i);
-    *(vfloat64m1_t*)(out + i + 600) = v;
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 500 + i);
+    *(vuint32mf2_t*)(out + i + 600) = v;
   }
 
   if (cond == 0)
@@ -58,7 +58,7 @@  void f (int32_t * restrict in, int32_t * restrict out, int n, int cond, int cond
   }
 }
 
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c
index bcf8e1c59bb..d7c74fe8137 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c
@@ -210,12 +210,6 @@  void f6 (int8_t * restrict in, int8_t * restrict out, int n)
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c
index c2a8c3bd3b0..9ea35cf7e32 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c
@@ -210,12 +210,6 @@  void f6 (int8_t * restrict in, int8_t * restrict out, int n)
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c
index e449078c79e..5c4a03108fb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c
@@ -38,4 +38,3 @@  void f (int8_t * restrict in, int8_t * restrict out, int n)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c
index 224fc2e5f86..fe7870e40ed 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c
@@ -248,10 +248,3 @@  void f7 (int8_t * restrict in, int8_t * restrict out, int n)
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c
index 198b72fd8ca..d564b065daa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c
@@ -147,9 +147,9 @@  void f6 (int * restrict in, int * restrict out, int n, int cond)
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c
index ca20f2f6aa8..fe32d83eb81 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c
@@ -147,9 +147,9 @@  void f6 (int * restrict in, int * restrict out, int n, int cond)
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c
index ecd8a202440..3271557f589 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c
@@ -27,4 +27,4 @@  void f (int * restrict in, int * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c
index a9ed21167a8..233bb0bff54 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c
@@ -171,10 +171,10 @@  void f7 (int * restrict in, int * restrict out, int n, int cond)
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c
index 2cf28d7cd36..83b7aafebb3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c
@@ -156,12 +156,12 @@  void f6 (int8_t * restrict in, int8_t * restrict out, int n)
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c
index d52c1bbecd3..d3be7011881 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c
@@ -156,12 +156,12 @@  void f6 (int8_t * restrict in, int8_t * restrict out, int n)
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c
index bd6d68bf780..c3f8684c3ac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c
@@ -29,4 +29,4 @@  void f (int8_t * restrict in, int8_t * restrict out, int n)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c
index d3b3fa3390e..24875936d26 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c
@@ -185,10 +185,10 @@  void f7 (int8_t * restrict in, int8_t * restrict out, int n)
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c
index 34ac4a54164..7a8bb8e93ed 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
@@ -18,6 +18,6 @@  void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t cond, si
 }
 
 /* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {\.L[0-9]+:\s+vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+j\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c
index 217ce11f5a9..d365e4ac3c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c
@@ -19,7 +19,6 @@  void f (int32_t * in, int32_t * out, int n, int cond)
   }
 }
 
-/* { dg-final { scan-assembler-times {\.L[0-9]+:\s+vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+:} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {\.L[0-9]+:\s+vle8\.v} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c
index db5f64ffad2..aaafa02b508 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c
@@ -29,4 +29,4 @@  void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c
index d5c108c0872..200bec7935a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c
@@ -29,4 +29,3 @@  void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c
index 2c8e0ba490b..f8bf5ebbd0f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c
@@ -29,4 +29,4 @@  void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c
index 50807adc3cd..691ff249b2e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c
@@ -29,4 +29,4 @@  void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c
index b9e0d207b84..b922c43bcab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c
@@ -29,4 +29,4 @@  void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c
index efe51b2e0f9..d1be90a7c66 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c
@@ -180,10 +180,4 @@  void f7 (void * restrict in, void * restrict out, int n, int cond)
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c
index ab6c1b13aa2..4acf12c1276 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c
@@ -29,4 +29,4 @@  void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c
index eb1afa55aab..2dda69041f5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c
@@ -29,4 +29,4 @@  void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c
index 535f3261204..9e57b0d1357 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c
@@ -29,4 +29,4 @@  void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c
index ea7f4e3d2de..ae342cff8a7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c
@@ -29,4 +29,4 @@  void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c
index f340b44db31..6a5a9cc80fb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c
@@ -29,4 +29,4 @@  void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c
index 70aea4e7ea6..76cbfec151a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c
@@ -29,4 +29,4 @@  void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c
index 697d5faff22..0f48bdba040 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c
@@ -29,4 +29,4 @@  void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c
index f1edf8f68ec..712a3ee2552 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c
@@ -29,4 +29,4 @@  void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"    no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
index b68932a6802..cdbe856ae84 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
@@ -42,6 +42,5 @@  void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times {\s*\.L[0-9]+:\s*vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
new file mode 100644
index 00000000000..b82e2490815
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
@@ -0,0 +1,16 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(int8_t *base, int8_t *out, size_t vl, size_t m, vbool64_t mask) {
+  size_t avl = __riscv_vsetvl_e8mf8(vl);
+
+  for (size_t i = 0; i < m; i++) {
+    vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, avl);
+    __riscv_vse8_v_i8mf8(out + i, v0, avl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c
new file mode 100644
index 00000000000..3c7e0ec27b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c
@@ -0,0 +1,20 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(void *in1, void *in2, void *in3, void *out, size_t n, size_t vl) {
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, __riscv_vsetvl_e16m1(vl));
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, __riscv_vsetvl_e16m1(vl));
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, __riscv_vsetvl_e16m1(vl));
+    __riscv_vse32_v_i32m1(out, c, __riscv_vsetvl_e16m1(vl));
+    
+    vint8mf2_t a2 = __riscv_vle8_v_i8mf2(in1 + 100, __riscv_vsetvl_e8m1(vl));
+    vint8mf2_t b2 = __riscv_vle8_v_i8mf2_tu(a2, in2 + 100, __riscv_vsetvl_e8m1(vl));
+    vint8mf2_t c2 = __riscv_vle8_v_i8mf2_tu(b2, in3 + 100, __riscv_vsetvl_e8m1(vl));
+    __riscv_vse8_v_i8mf2(out + 100, c2, __riscv_vsetvl_e8m1(vl));
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c
new file mode 100644
index 00000000000..fa825f031f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c
@@ -0,0 +1,21 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int cond, int avl) {
+  
+  size_t vl;
+  if (cond)
+    vl = __riscv_vsetvl_e32m1(avl);
+  else
+    vl = __riscv_vsetvl_e16mf2(avl);
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl);
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+    __riscv_vse32_v_i32m1(out, c, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c
new file mode 100644
index 00000000000..fc7e1cb249e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c
@@ -0,0 +1,21 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int cond, int avl) {
+  
+  size_t vl;
+  if (cond)
+    vl = __riscv_vsetvl_e32m1(avl);
+  else
+    vl = 3;
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl);
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+    __riscv_vse32_v_i32m1(out, c, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c
new file mode 100644
index 00000000000..6157a2c7f12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int cond, int avl) {
+  
+  size_t vl;
+  if (cond)
+    vl = __riscv_vsetvl_e32m1(avl);
+  else
+    vl = 55;
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl);
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+    __riscv_vse32_v_i32m1(out, c, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c
new file mode 100644
index 00000000000..40d4af00419
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c
@@ -0,0 +1,24 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int cond, int avl) {
+  
+  size_t vl;
+  if (cond){
+    vl = __riscv_vsetvl_e32m1(avl);
+    vint16mf2_t v = *(vint16mf2_t*)(in1 + 1000);
+    *(vint16mf2_t*)(out + 1000) = v;
+  }
+  else
+    vl = 55;
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl);
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+    __riscv_vse32_v_i32m1(out, c, vl);
+  }
+}
+
+/* { dg-final { scan-assembler {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c
new file mode 100644
index 00000000000..c677a81d706
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int cond, int avl) {
+  
+  size_t vl;
+  if (cond)
+    vl = __riscv_vsetvl_e32m1(avl);
+  else
+    vl = __riscv_vsetvl_e16mf2(avl) >> 4;
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl);
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+    __riscv_vse32_v_i32m1(out, c, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {srli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*4} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c
new file mode 100644
index 00000000000..37a9039af85
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c
@@ -0,0 +1,20 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(int8_t *base, int8_t *out, size_t vl, size_t m) {
+  size_t avl;
+  if (m > 100)
+    avl = __riscv_vsetvl_e8mf8(vl << 10);
+  else
+    avl = __riscv_vsetvl_e8mf8(vl);
+
+  for (size_t i = 0; i < m; i++) {
+    vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, avl);
+    __riscv_vse8_v_i8mf8(out + i, v0, avl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*10} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c
new file mode 100644
index 00000000000..ee58f9bbdfc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int cond, int vl) {
+  
+  vint32m1_t a = __riscv_vle32_v_i32m1(in1, __riscv_vsetvl_e8mf8 (vl));
+  vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, __riscv_vsetvl_e8mf4 (vl));
+  vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, __riscv_vsetvl_e8m1 (vl));
+  __riscv_vse32_v_i32m1(out, c, __riscv_vsetvl_e8mf2 (vl));
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 8 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c
new file mode 100644
index 00000000000..df4fdf24a4a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c
@@ -0,0 +1,19 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(int8_t *base, int8_t *out, size_t vl, size_t m, size_t n) {
+  vint8mf4_t v1 = *(vint8mf4_t*) (base + 100000);
+  size_t avl = __riscv_vsetvl_e8mf8(vl);
+  for (size_t i = 0; i < m; i++) {
+    vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, avl);
+    if (n > 100) {
+      __riscv_vse8_v_i8mf4(out + i, v1, avl);
+    } else {
+      __riscv_vse8_v_i8mf8(out + i, v0, avl);
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c
new file mode 100644
index 00000000000..87ef3acc24d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int cond, int avl) {
+  
+  size_t vl;
+  if (cond)
+    vl = __riscv_vsetvl_e32m1(avl);
+  else
+    vl = __riscv_vsetvl_e32m1(avl) << 5;
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl);
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+    __riscv_vse32_v_i32m1(out, c, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*5} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c
new file mode 100644
index 00000000000..fb8f14ec4f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c
@@ -0,0 +1,20 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(int8_t *base, int8_t *out, size_t vl, size_t m) {
+  size_t avl;
+  if (m > 100)
+    avl = __riscv_vsetvl_e8mf8(vl << 10);
+  else
+    avl = __riscv_vsetvl_e8mf8(vl);
+
+  for (size_t i = 0; i < m; i++) {
+    vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, avl);
+    __riscv_vse8_v_i8mf8(out + i, v0, avl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*10} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c
new file mode 100644
index 00000000000..d3f4a271ccf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c
@@ -0,0 +1,23 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int cond, int avl) {
+  
+  size_t vl;
+  if (cond)
+    vl = __riscv_vsetvl_e32m1(avl);
+  else
+    vl = (__riscv_vsetvl_e32m1(avl) << 5) + 100;
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl);
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+    __riscv_vse32_v_i32m1(out, c, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*5} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {addi\s+[a-x0-9]+,\s*[a-x0-9]+,\s*100} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c
new file mode 100644
index 00000000000..98306cc5dfa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c
@@ -0,0 +1,21 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(int8_t *base, int8_t *out, size_t vl, size_t m) {
+  size_t avl;
+  if (m > 100)
+    avl = __riscv_vsetvl_e8mf8(vl << 10);
+  else
+    avl = __riscv_vsetvl_e8mf8(vl);
+
+  for (size_t i = 0; i < m; i++) {
+    vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, avl);
+    v0 = __riscv_vle8_v_i8mf8_tu(v0,base + i, avl);
+    __riscv_vse8_v_i8mf8(out + i, v0, avl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*10} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c
new file mode 100644
index 00000000000..548958cf764
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c
@@ -0,0 +1,21 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(int8_t *base, int8_t *out, size_t vl, size_t m) {
+  size_t avl;
+  if (m > 100)
+    avl = __riscv_vsetvl_e8mf8(vl << 10);
+  else
+    avl = vl;
+
+  for (size_t i = 0; i < m; i++) {
+    vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, avl);
+    v0 = __riscv_vle8_v_i8mf8_tu(v0,base + i, avl);
+    __riscv_vse8_v_i8mf8(out + i, v0, avl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*10} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c
new file mode 100644
index 00000000000..35ffe7e410f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, size_t vl) {
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, __riscv_vsetvl_e32m1(vl));
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, __riscv_vsetvl_e32m1(vl));
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, __riscv_vsetvl_e32m1(vl));
+    __riscv_vse32_v_i32m1(out, c, __riscv_vsetvl_e32m1(vl));
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle32\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c
new file mode 100644
index 00000000000..180ef07e578
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, size_t vl) {
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, __riscv_vsetvl_e32m1(vl));
+    __riscv_vse32_v_i32m1(out, a, __riscv_vsetvl_e32m1(vl));
+  }
+  
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1 + 100, __riscv_vsetvl_e32m1(vl));
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2 + 100, __riscv_vsetvl_e32m1(vl));
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3 + 100, __riscv_vsetvl_e32m1(vl));
+    __riscv_vse32_v_i32m1(out + 100, c, __riscv_vsetvl_e32m1(vl));
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle32\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c
new file mode 100644
index 00000000000..84d948b28dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, size_t vl) {
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, __riscv_vsetvl_e16mf2(vl));
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, __riscv_vsetvl_e16mf2(vl));
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, __riscv_vsetvl_e16mf2(vl));
+    __riscv_vse32_v_i32m1(out, c, __riscv_vsetvl_e16mf2(vl));
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle32\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c
new file mode 100644
index 00000000000..6f4c792c645
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, size_t vl) {
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, __riscv_vsetvl_e16mf2(vl));
+    __riscv_vse32_v_i32m1(out, a, __riscv_vsetvl_e16mf2(vl));
+  }
+  
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1 + 100, __riscv_vsetvl_e16mf2(vl));
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2 + 100, __riscv_vsetvl_e16mf2(vl));
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3 + 100, __riscv_vsetvl_e16mf2(vl));
+    __riscv_vse32_v_i32m1(out + 100, c, __riscv_vsetvl_e16mf2(vl));
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle32\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c
new file mode 100644
index 00000000000..d07152ce781
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c
@@ -0,0 +1,20 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(void *in1, void *in2, void *in3, void *out, size_t n, size_t vl) {
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, __riscv_vsetvl_e16mf2(vl));
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, __riscv_vsetvl_e16mf2(vl));
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, __riscv_vsetvl_e16mf2(vl));
+    __riscv_vse32_v_i32m1(out, c, __riscv_vsetvl_e16mf2(vl));
+    
+    vint8mf4_t a2 = __riscv_vle8_v_i8mf4(in1 + 100, __riscv_vsetvl_e32m1(vl));
+    vint8mf4_t b2 = __riscv_vle8_v_i8mf4_tu(a2, in2 + 100, __riscv_vsetvl_e32m1(vl));
+    vint8mf4_t c2 = __riscv_vle8_v_i8mf4_tu(b2, in3 + 100, __riscv_vsetvl_e32m1(vl));
+    __riscv_vse8_v_i8mf4(out + 100, c2, __riscv_vsetvl_e32m1(vl));
+  }
+}
+
+/* { dg-final { scan-assembler {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c
new file mode 100644
index 00000000000..49e0a53f14a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n) {
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, __riscv_vsetvlmax_e32m1());
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, __riscv_vsetvlmax_e32m1());
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, __riscv_vsetvlmax_e32m1());
+    __riscv_vse32_v_i32m1(out, c, __riscv_vsetvlmax_e32m1());
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle32\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c
new file mode 100644
index 00000000000..5b5a31b0eb6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c
@@ -0,0 +1,23 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int cond) {
+  
+  size_t vl;
+  if (cond)
+    vl = __riscv_vsetvlmax_e32m1();
+  else
+    vl = 3;
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl);
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+    __riscv_vse32_v_i32m1(out, c, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c
new file mode 100644
index 00000000000..e880c2ccdc2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c
@@ -0,0 +1,23 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int cond) {
+  
+  size_t vl;
+  if (cond)
+    vl = __riscv_vsetvlmax_e32m1();
+  else
+    vl = 55;
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl);
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+    __riscv_vse32_v_i32m1(out, c, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c
new file mode 100644
index 00000000000..c141f8bede2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c
@@ -0,0 +1,26 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int cond) {
+  
+  size_t vl;
+  if (cond) {
+    vl = __riscv_vsetvlmax_e32m1();
+    vint16mf2_t v = *(vint16mf2_t*)(in1 + 1000);
+    *(vint16mf2_t*)(out + 1000) = v;
+  }
+  else
+    vl = 55;
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl);
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+    __riscv_vse32_v_i32m1(out, c, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c
new file mode 100644
index 00000000000..1b92cb876cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c
@@ -0,0 +1,27 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int cond) {
+  
+  size_t vl;
+  if (cond) {
+    vl = __riscv_vsetvlmax_e32m1();
+    vint8mf8_t v = *(vint8mf8_t*)(in1 + 1000);
+    *(vint8mf8_t*)(out + 1000) = v;
+  }
+  else
+    vl = 55;
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl);
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+    __riscv_vse32_v_i32m1(out, c, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c
new file mode 100644
index 00000000000..170172d17bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c
@@ -0,0 +1,18 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(int8_t *base, int8_t *out, size_t vl, size_t m) {
+  size_t avl = __riscv_vsetvlmax_e8mf8();
+
+  for (size_t i = 0; i < m; i++) {
+    vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, avl);
+    v0 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 100, avl);
+    __riscv_vse8_v_i8mf8(out + i, v0, avl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c
new file mode 100644
index 00000000000..12151bc519b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c
@@ -0,0 +1,23 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int cond) {
+  
+  size_t vl;
+  if (cond)
+    vl = __riscv_vsetvlmax_e32m1();
+  else
+    vl = __riscv_vsetvlmax_e16mf2() << 5;
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl);
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+    __riscv_vse32_v_i32m1(out, c, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*5} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c
new file mode 100644
index 00000000000..6cce6fe4282
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int cond) {
+  
+  vint32m1_t a = __riscv_vle32_v_i32m1(in1, __riscv_vsetvlmax_e8mf8 ());
+  vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, __riscv_vsetvlmax_e8mf4 ());
+  vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, __riscv_vsetvlmax_e8m1 ());
+  __riscv_vse32_v_i32m1(out, c, __riscv_vsetvlmax_e8mf2 ());
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c
new file mode 100644
index 00000000000..d28d6f866c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c
@@ -0,0 +1,16 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int cond) {
+  
+  for (int i = 0; i < n; i++){
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1 + i, __riscv_vsetvlmax_e8mf8 ());
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2 + i, __riscv_vsetvlmax_e8mf4 ());
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3 + i, __riscv_vsetvlmax_e8m1 ());
+    __riscv_vse32_v_i32m1(out + i, c, __riscv_vsetvlmax_e8mf2 ());
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c
new file mode 100644
index 00000000000..c1c18c3e13c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c
@@ -0,0 +1,19 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(int8_t *base, int8_t *out, size_t vl, size_t m, size_t n) {
+  vint8mf4_t v1 = *(vint8mf4_t*) (base + 100000);
+  size_t avl = __riscv_vsetvlmax_e8mf8();
+  for (size_t i = 0; i < m; i++) {
+    vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, avl);
+    if (n > 100) {
+      __riscv_vse8_v_i8mf4(out + i + 100, v1, avl);
+    } else {
+      __riscv_vse8_v_i8mf8(out + i, v0, avl);
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c
new file mode 100644
index 00000000000..1d77efb9539
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int cond) {
+  
+  size_t vl;
+  if (cond)
+    vl = __riscv_vsetvlmax_e32m1();
+  else
+    vl = __riscv_vsetvlmax_e32m1() << 5;
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl);
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+    __riscv_vse32_v_i32m1(out, c, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*5} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c
new file mode 100644
index 00000000000..482a48314e2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c
@@ -0,0 +1,21 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n) {
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, __riscv_vsetvlmax_e32m1());
+    __riscv_vse32_v_i32m1(out, a, __riscv_vsetvlmax_e32m1());
+  }
+  
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1 + 100, __riscv_vsetvlmax_e32m1());
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2 + 100, __riscv_vsetvlmax_e32m1());
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3 + 100, __riscv_vsetvlmax_e32m1());
+    __riscv_vse32_v_i32m1(out + 100, c, __riscv_vsetvlmax_e32m1());
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c
new file mode 100644
index 00000000000..1102d7ec830
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c
@@ -0,0 +1,19 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int cond) {
+  
+  for (size_t i = 0; i < n; i += 1) {
+    size_t vl = __riscv_vsetvlmax_e32m1();
+    vint16mf2_t v = *(vint16mf2_t*)(in1 + 1000);
+    *(vint16mf2_t*)(out + 1000) = v;
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl);
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+    __riscv_vse32_v_i32m1(out, c, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c
new file mode 100644
index 00000000000..cc0135ffb8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c
@@ -0,0 +1,16 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n) {
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, __riscv_vsetvlmax_e16mf2());
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, __riscv_vsetvlmax_e16mf2());
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, __riscv_vsetvlmax_e16mf2());
+    __riscv_vse32_v_i32m1(out, c, __riscv_vsetvlmax_e16mf2());
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c
new file mode 100644
index 00000000000..3b9865e3bab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c
@@ -0,0 +1,21 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n) {
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, __riscv_vsetvlmax_e16mf2());
+    __riscv_vse32_v_i32m1(out, a, __riscv_vsetvlmax_e16mf2());
+  }
+  
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1 + 100, __riscv_vsetvlmax_e16mf2());
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2 + 100, __riscv_vsetvlmax_e16mf2());
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3 + 100, __riscv_vsetvlmax_e16mf2());
+    __riscv_vse32_v_i32m1(out + 100, c, __riscv_vsetvlmax_e16mf2());
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c
new file mode 100644
index 00000000000..0a3a5a3d2d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c
@@ -0,0 +1,21 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(void *in1, void *in2, void *in3, void *out, size_t n) {
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, __riscv_vsetvlmax_e16mf2());
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, __riscv_vsetvlmax_e16mf2());
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, __riscv_vsetvlmax_e16mf2());
+    __riscv_vse32_v_i32m1(out, c, __riscv_vsetvlmax_e16mf2());
+    
+    vint8mf4_t a2 = __riscv_vle8_v_i8mf4(in1 + 100, __riscv_vsetvlmax_e32m1());
+    vint8mf4_t b2 = __riscv_vle8_v_i8mf4_tu(a2, in2 + 100, __riscv_vsetvlmax_e32m1());
+    vint8mf4_t c2 = __riscv_vle8_v_i8mf4_tu(b2, in3 + 100, __riscv_vsetvlmax_e32m1());
+    __riscv_vse8_v_i8mf4(out + 100, c2, __riscv_vsetvlmax_e32m1());
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c
new file mode 100644
index 00000000000..c32f15d8224
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(void *in1, void *in2, void *in3, void *out, size_t n) {
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, __riscv_vsetvlmax_e16mf2());
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, __riscv_vsetvlmax_e16mf2());
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, __riscv_vsetvlmax_e16mf2());
+    __riscv_vse32_v_i32m1(out, c, __riscv_vsetvlmax_e16mf2());
+    
+    vint8mf2_t a2 = __riscv_vle8_v_i8mf2(in1 + 100, __riscv_vsetvlmax_e8mf2());
+    vint8mf2_t b2 = __riscv_vle8_v_i8mf2_tu(a2, in2 + 100, __riscv_vsetvlmax_e8mf2());
+    vint8mf2_t c2 = __riscv_vle8_v_i8mf2_tu(b2, in3 + 100, __riscv_vsetvlmax_e8mf2());
+    __riscv_vse8_v_i8mf2(out + 100, c2, __riscv_vsetvlmax_e8mf2());
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c
new file mode 100644
index 00000000000..0ee04ee04c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c
@@ -0,0 +1,24 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(void *in1, void *in2, void *in3, void *out, size_t n) {
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, __riscv_vsetvlmax_e16m1());
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, __riscv_vsetvlmax_e16m1());
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, __riscv_vsetvlmax_e16m1());
+    __riscv_vse32_v_i32m1(out, c, __riscv_vsetvlmax_e16m1());
+    
+    vint8mf2_t a2 = __riscv_vle8_v_i8mf2(in1 + 100, __riscv_vsetvlmax_e8m1());
+    vint8mf2_t b2 = __riscv_vle8_v_i8mf2_tu(a2, in2 + 100, __riscv_vsetvlmax_e8m1());
+    vint8mf2_t c2 = __riscv_vle8_v_i8mf2_tu(b2, in3 + 100, __riscv_vsetvlmax_e8m1());
+    __riscv_vse8_v_i8mf2(out + 100, c2, __riscv_vsetvlmax_e8m1());
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c
new file mode 100644
index 00000000000..a0335a34645
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int cond) {
+  
+  size_t vl;
+  if (cond)
+    vl = __riscv_vsetvlmax_e32m1();
+  else
+    vl = __riscv_vsetvlmax_e16mf2();
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl);
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+    __riscv_vse32_v_i32m1(out, c, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c
new file mode 100644
index 00000000000..5b5a31b0eb6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c
@@ -0,0 +1,23 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int cond) {
+  
+  size_t vl;
+  if (cond)
+    vl = __riscv_vsetvlmax_e32m1();
+  else
+    vl = 3;
+  for (size_t i = 0; i < n; i += 1) {
+    vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl);
+    vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+    vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+    __riscv_vse32_v_i32m1(out, c, vl);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */