diff mbox series

RISC-V: Remove side effects of vsetvl pattern in RTL.

Message ID 20221220145649.232331-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Remove side effects of vsetvl pattern in RTL. |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai Dec. 20, 2022, 2:56 p.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

        * config/riscv/riscv-vector-builtins-bases.cc: Change it to no side effects.
        * config/riscv/vector.md (@vsetvl<mode>_no_side_effects): New pattern.

---
 .../riscv/riscv-vector-builtins-bases.cc      |  2 +-
 gcc/config/riscv/vector.md                    | 26 +++++++++++++++++++
 2 files changed, 27 insertions(+), 1 deletion(-)

Comments

Jeff Law Dec. 20, 2022, 3:58 p.m. UTC | #1 
On 12/20/22 07:56, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> 
> gcc/ChangeLog:
> 
>          * config/riscv/riscv-vector-builtins-bases.cc: Change it to no side effects.
>          * config/riscv/vector.md (@vsetvl<mode>_no_side_effects): New pattern.
OK
jeff
Kito Cheng Dec. 23, 2022, 5:43 a.m. UTC | #2 
Committed, thanks :)

On Tue, Dec 20, 2022 at 11:59 PM Jeff Law via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
>
>
> On 12/20/22 07:56, juzhe.zhong@rivai.ai wrote:
> > From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> >
> > gcc/ChangeLog:
> >
> >          * config/riscv/riscv-vector-builtins-bases.cc: Change it to no side effects.
> >          * config/riscv/vector.md (@vsetvl<mode>_no_side_effects): New pattern.
> OK
> jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 75879dea25a..c1193dbbfb5 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -75,7 +75,7 @@  public:
 
     /* MU.  */
     e.add_input_operand (Pmode, gen_int_mode (0, Pmode));
-    return e.generate_insn (code_for_vsetvl (Pmode));
+    return e.generate_insn (code_for_vsetvl_no_side_effects (Pmode));
   }
 };
 
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 84adbb9974a..98b8f701c92 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -565,6 +565,32 @@ 
   [(set_attr "type" "vsetvl")
    (set_attr "mode" "<MODE>")])
 
+;; It's emit by vsetvl/vsetvlmax intrinsics with no side effects.
+;; Since we have many optmization passes from "expand" to "reload_completed",
+;; such pattern can allow us gain benefits of these optimizations.
+(define_insn_and_split "@vsetvl<mode>_no_side_effects"
+  [(set (match_operand:P 0 "register_operand" "=r")
+	(unspec:P [(match_operand:P 1 "csr_operand" "rK")
+		   (match_operand 2 "const_int_operand" "i")
+		   (match_operand 3 "const_int_operand" "i")
+		   (match_operand 4 "const_int_operand" "i")
+		   (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))]
+  "TARGET_VECTOR"
+  "#"
+  "&& epilogue_completed"
+  [(parallel
+    [(set (match_dup 0)
+	  (unspec:P [(match_dup 1) (match_dup 2) (match_dup 3)
+		     (match_dup 4) (match_dup 5)] UNSPEC_VSETVL))
+     (set (reg:SI VL_REGNUM)
+	  (unspec:SI [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_VSETVL))
+     (set (reg:SI VTYPE_REGNUM)
+	  (unspec:SI [(match_dup 2) (match_dup 3) (match_dup 4)
+		      (match_dup 5)] UNSPEC_VSETVL))])]
+  ""
+  [(set_attr "type" "vsetvl")
+   (set_attr "mode" "SI")])
+
 ;; RVV machine description matching format
 ;; (define_insn ""
 ;;   [(set (match_operand:MODE 0)