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[8.43.85.97]) by mx.google.com with ESMTPS id hr20-20020a1709073f9400b007ae94428c13si13455440ejc.525.2022.12.14.22.24.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Dec 2022 22:24:41 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=wqr+yv2i; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 20F68382A206 for ; Thu, 15 Dec 2022 06:24:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 20F68382A206 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1671085475; bh=Zu8Tg6NcXa4YoEqrrFnTMdZGYOttFnSsTUKg5rVwpsE=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=wqr+yv2ikKqs3ZLg9nsduVUO74F5M9CvwUhzXq2WDr8y7Q9IeTQUqQDFTyuaCmfYs 70cVjc8URvTqQkkLzOa3Nasfu6LHQqAO2YHW5MxQGhrWkaGsh+Gzzuu7/mQ1yPqDAR 5Fh85OKP3hyXT7RmHaNQs72GWSuks8lS1B9O+qUc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by sourceware.org (Postfix) with ESMTPS id 864F0385B1BD for ; Thu, 15 Dec 2022 06:23:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 864F0385B1BD X-IronPort-AV: E=McAfee;i="6500,9779,10561"; a="320453183" X-IronPort-AV: E=Sophos;i="5.96,246,1665471600"; d="scan'208";a="320453183" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2022 22:23:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10561"; a="791517983" X-IronPort-AV: E=Sophos;i="5.96,246,1665471600"; d="scan'208";a="791517983" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga001.fm.intel.com with ESMTP; 14 Dec 2022 22:23:38 -0800 Received: from shliclel4051.sh.intel.com (shliclel4051.sh.intel.com [10.239.240.51]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 15487100562A; Thu, 15 Dec 2022 14:23:38 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com, hjl.tools@gmail.com, ubizjak@gmail.com Subject: [PATCH V2 2/2] [x86] x86: Add a new option -mdaz-ftz to enable FTZ and DAZ flags in MXCSR. Date: Thu, 15 Dec 2022 14:21:37 +0800 Message-Id: <20221215062137.3128845-2-hongtao.liu@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221215062137.3128845-1-hongtao.liu@intel.com> References: <20221215062137.3128845-1-hongtao.liu@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752260129884168968?= X-GMAIL-MSGID: =?utf-8?q?1752260129884168968?= Update in v2: 1. Support -mno-daz-ftz, and make the the option effectively three state as: if (mdaz-ftz) link crtfastmath.o else if ((Ofast || ffast-math || funsafe-math-optimizations) && !shared && !mno-daz-ftz) link crtfastmath.o else Don't link crtfastmath.o 2. Still make the option Target since a. cc1: error: command-line option ‘-mdaz-ftz’ is valid for the driver but not for C b. Since there's no real variable speicified by mdaz-ftz, I saw in options.h, it's marked as #ifndef GENERATOR_FILE int x_VAR_mdaz_ftz; #define x_VAR_mdaz_ftz do_not_use #endif and not be saved and restored in cl_target_option_save and cl_target_option_restore(am I missing something?) 3. Capital the first letter and add more descriptions about -mdaz-ftz and -shared. gcc/ChangeLog: PR target/55522 PR target/36821 * config/i386/gnu-user-common.h (GNU_USER_TARGET_MATHFILE_SPEC): Link crtfastmath.o whenever -mdaz-ftz is specified. Don't link crtfastmath.o when -share or -mno-daz-ftz is specified. * config/i386/i386.opt (mdaz-ftz): New option. * doc/invoke.texi (x86 options): Document mftz-daz. --- gcc/config/i386/gnu-user-common.h | 2 +- gcc/config/i386/i386.opt | 4 ++++ gcc/doc/invoke.texi | 12 +++++++++++- 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/gcc/config/i386/gnu-user-common.h b/gcc/config/i386/gnu-user-common.h index 9910cd64363..f910524a6c3 100644 --- a/gcc/config/i386/gnu-user-common.h +++ b/gcc/config/i386/gnu-user-common.h @@ -47,7 +47,7 @@ along with GCC; see the file COPYING3. If not see /* Similar to standard GNU userspace, but adding -ffast-math support. */ #define GNU_USER_TARGET_MATHFILE_SPEC \ - "%{Ofast|ffast-math|funsafe-math-optimizations:%{!shared:crtfastmath.o%s}} \ + "%{mdaz-ftz:crtfastmath.o%s;Ofast|ffast-math|funsafe-math-optimizations:%{!shared:%{!mno-daz-ftz:crtfastmath.o%s}}} \ %{mpc32:crtprec32.o%s} \ %{mpc64:crtprec64.o%s} \ %{mpc80:crtprec80.o%s}" diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index fb4e57ada7c..0b7df429734 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -420,6 +420,10 @@ mpc80 Target RejectNegative Set 80387 floating-point precision to 80-bit. +mdaz-ftz +Target +Set the FTZ and DAZ Flags. + mpreferred-stack-boundary= Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg) Attempt to keep stack aligned to this power of 2. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index cba4f19f4f4..7f1d002f228 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1433,7 +1433,7 @@ See RS/6000 and PowerPC Options. -m96bit-long-double -mlong-double-64 -mlong-double-80 -mlong-double-128 @gol -mregparm=@var{num} -msseregparm @gol -mveclibabi=@var{type} -mvect8-ret-in-mem @gol --mpc32 -mpc64 -mpc80 -mstackrealign @gol +-mpc32 -mpc64 -mpc80 -mdaz-ftz -mstackrealign @gol -momit-leaf-frame-pointer -mno-red-zone -mno-tls-direct-seg-refs @gol -mcmodel=@var{code-model} -mabi=@var{name} -maddress-mode=@var{mode} @gol -m32 -m64 -mx32 -m16 -miamcu -mlarge-data-threshold=@var{num} @gol @@ -32753,6 +32753,16 @@ are enabled by default; routines in such libraries could suffer significant loss of accuracy, typically through so-called ``catastrophic cancellation'', when this option is used to set the precision to less than extended precision. +@item -mdaz-ftz +@opindex mdaz-ftz + +The flush-to-zero (FTZ) and denormals-are-zero (DAZ) flags in the MXCSR register +are used to control floating-point calculations.SSE and AVX instructions +including scalar and vector instructions could benefit from enabling the FTZ +and DAZ flags when @option{-mdaz-ftz} is specified. Don't set FTZ/DAZ flags +when @option{-mno-daz-ftz} or @option{-shared} is specified, @option{-mdaz-ftz} +will set FTZ/DAZ flags even with @option{-shared}. + @item -mstackrealign @opindex mstackrealign Realign the stack at entry. On the x86, the @option{-mstackrealign}