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From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add testcases for VSETVL PASS 3 Date: Wed, 14 Dec 2022 16:15:48 +0800 Message-Id: <20221214081548.253313-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752176586176065614?= X-GMAIL-MSGID: =?utf-8?q?1752176586176065614?= From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c: New test. --- .../riscv/rvv/vsetvl/vlmax_miss_default-1.c | 32 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-10.c | 32 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-11.c | 32 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-12.c | 32 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-13.c | 32 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-14.c | 189 ++++++++++++++ .../riscv/rvv/vsetvl/vlmax_miss_default-15.c | 38 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-16.c | 38 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-17.c | 38 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-18.c | 38 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-19.c | 38 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-2.c | 32 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-20.c | 38 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-21.c | 38 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-22.c | 38 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-23.c | 38 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-24.c | 38 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-25.c | 38 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-26.c | 38 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-27.c | 38 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-28.c | 231 ++++++++++++++++++ .../riscv/rvv/vsetvl/vlmax_miss_default-3.c | 32 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-4.c | 32 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-5.c | 32 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-6.c | 32 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-7.c | 32 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-8.c | 32 +++ .../riscv/rvv/vsetvl/vlmax_miss_default-9.c | 32 +++ 28 files changed, 1330 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c new file mode 100644 index 00000000000..d801428004e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vint8mf8_t v = *(vint8mf8_t*)(in + 100); + *(vint8mf8_t*)(out + 100) = v; + } + else if (cond == 2) + { + vint8mf8_t v = *(vint8mf8_t*)(in + 200); + *(vint8mf8_t*)(out + 200) = v; + } + else if (cond == 3) + { + vint8mf8_t v = *(vint8mf8_t*)(in + 300); + *(vint8mf8_t*)(out + 300) = v; + } + for (int i = 0; i < n; i++) + { + vint8mf8_t v = *(vint8mf8_t*)(in + i); + *(vint8mf8_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c new file mode 100644 index 00000000000..d96e9b2d7ab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vuint16mf2_t v = *(vuint16mf2_t*)(in + 100); + *(vuint16mf2_t*)(out + 100) = v; + } + else if (cond == 2) + { + vuint16mf2_t v = *(vuint16mf2_t*)(in + 200); + *(vuint16mf2_t*)(out + 200) = v; + } + else if (cond == 3) + { + vuint16mf2_t v = *(vuint16mf2_t*)(in + 300); + *(vuint16mf2_t*)(out + 300) = v; + } + for (int i = 0; i < n; i++) + { + vuint16mf2_t v = *(vuint16mf2_t*)(in + i); + *(vuint16mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c new file mode 100644 index 00000000000..de967f78bc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vint32mf2_t v = *(vint32mf2_t*)(in + 100); + *(vint32mf2_t*)(out + 100) = v; + } + else if (cond == 2) + { + vint32mf2_t v = *(vint32mf2_t*)(in + 200); + *(vint32mf2_t*)(out + 200) = v; + } + else if (cond == 3) + { + vint32mf2_t v = *(vint32mf2_t*)(in + 300); + *(vint32mf2_t*)(out + 300) = v; + } + for (int i = 0; i < n; i++) + { + vint32mf2_t v = *(vint32mf2_t*)(in + i); + *(vint32mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c new file mode 100644 index 00000000000..8342edb353a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vuint32mf2_t v = *(vuint32mf2_t*)(in + 100); + *(vuint32mf2_t*)(out + 100) = v; + } + else if (cond == 2) + { + vuint32mf2_t v = *(vuint32mf2_t*)(in + 200); + *(vuint32mf2_t*)(out + 200) = v; + } + else if (cond == 3) + { + vuint32mf2_t v = *(vuint32mf2_t*)(in + 300); + *(vuint32mf2_t*)(out + 300) = v; + } + for (int i = 0; i < n; i++) + { + vuint32mf2_t v = *(vuint32mf2_t*)(in + i); + *(vuint32mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c new file mode 100644 index 00000000000..82cd0d36913 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 100); + *(vfloat32mf2_t*)(out + 100) = v; + } + else if (cond == 2) + { + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 200); + *(vfloat32mf2_t*)(out + 200) = v; + } + else if (cond == 3) + { + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 300); + *(vfloat32mf2_t*)(out + 300) = v; + } + for (int i = 0; i < n; i++) + { + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i); + *(vfloat32mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c new file mode 100644 index 00000000000..5e08b23178b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c @@ -0,0 +1,189 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vbool64_t v = *(vbool64_t*)(in + 100); + *(vbool64_t*)(out + 100) = v; + } + else if (cond == 2) + { + vbool64_t v = *(vbool64_t*)(in + 200); + *(vbool64_t*)(out + 200) = v; + } + else if (cond == 3) + { + vbool64_t v = *(vbool64_t*)(in + 300); + *(vbool64_t*)(out + 300) = v; + } + for (int i = 0; i < n; i++) + { + vbool64_t v = *(vbool64_t*)(in + i); + *(vbool64_t*)(out + i) = v; + } +} + +void f2 (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vbool32_t v = *(vbool32_t*)(in + 100); + *(vbool32_t*)(out + 100) = v; + } + else if (cond == 2) + { + vbool32_t v = *(vbool32_t*)(in + 200); + *(vbool32_t*)(out + 200) = v; + } + else if (cond == 3) + { + vbool32_t v = *(vbool32_t*)(in + 300); + *(vbool32_t*)(out + 300) = v; + } + for (int i = 0; i < n; i++) + { + vbool32_t v = *(vbool32_t*)(in + i); + *(vbool32_t*)(out + i) = v; + } +} + +void f3 (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vbool16_t v = *(vbool16_t*)(in + 100); + *(vbool16_t*)(out + 100) = v; + } + else if (cond == 2) + { + vbool16_t v = *(vbool16_t*)(in + 200); + *(vbool16_t*)(out + 200) = v; + } + else if (cond == 3) + { + vbool16_t v = *(vbool16_t*)(in + 300); + *(vbool16_t*)(out + 300) = v; + } + for (int i = 0; i < n; i++) + { + vbool16_t v = *(vbool16_t*)(in + i); + *(vbool16_t*)(out + i) = v; + } +} + +void f4 (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vbool8_t v = *(vbool8_t*)(in + 100); + *(vbool8_t*)(out + 100) = v; + } + else if (cond == 2) + { + vbool8_t v = *(vbool8_t*)(in + 200); + *(vbool8_t*)(out + 200) = v; + } + else if (cond == 3) + { + vbool8_t v = *(vbool8_t*)(in + 300); + *(vbool8_t*)(out + 300) = v; + } + for (int i = 0; i < n; i++) + { + vbool8_t v = *(vbool8_t*)(in + i); + *(vbool8_t*)(out + i) = v; + } +} + +void f5 (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vbool4_t v = *(vbool4_t*)(in + 100); + *(vbool4_t*)(out + 100) = v; + } + else if (cond == 2) + { + vbool4_t v = *(vbool4_t*)(in + 200); + *(vbool4_t*)(out + 200) = v; + } + else if (cond == 3) + { + vbool4_t v = *(vbool4_t*)(in + 300); + *(vbool4_t*)(out + 300) = v; + } + for (int i = 0; i < n; i++) + { + vbool4_t v = *(vbool4_t*)(in + i); + *(vbool4_t*)(out + i) = v; + } +} + +void f6 (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vbool2_t v = *(vbool2_t*)(in + 100); + *(vbool2_t*)(out + 100) = v; + } + else if (cond == 2) + { + vbool2_t v = *(vbool2_t*)(in + 200); + *(vbool2_t*)(out + 200) = v; + } + else if (cond == 3) + { + vbool2_t v = *(vbool2_t*)(in + 300); + *(vbool2_t*)(out + 300) = v; + } + for (int i = 0; i < n; i++) + { + vbool2_t v = *(vbool2_t*)(in + i); + *(vbool2_t*)(out + i) = v; + } +} + +void f7 (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vbool1_t v = *(vbool1_t*)(in + 100); + *(vbool1_t*)(out + 100) = v; + } + else if (cond == 2) + { + vbool1_t v = *(vbool1_t*)(in + 200); + *(vbool1_t*)(out + 200) = v; + } + else if (cond == 3) + { + vbool1_t v = *(vbool1_t*)(in + 300); + *(vbool1_t*)(out + 300) = v; + } + for (int i = 0; i < n; i++) + { + vbool1_t v = *(vbool1_t*)(in + i); + *(vbool1_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c new file mode 100644 index 00000000000..267d1bd5cf6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vint8mf8_t v = *(vint8mf8_t*)(in + 100); + *(vint8mf8_t*)(out + 100) = v; + break; + } + case 2:{ + vint8mf8_t v = *(vint8mf8_t*)(in + 200); + *(vint8mf8_t*)(out + 100) = v; + break; + } + case 3:{ + vint8mf8_t v = *(vint8mf8_t*)(in + 300); + *(vint8mf8_t*)(out + 100) = v; + break; + } + default:{ + break; + } + } + for (int i = 0; i < n; i++) + { + vint8mf8_t v = *(vint8mf8_t*)(in + i); + *(vint8mf8_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c new file mode 100644 index 00000000000..3e6c51ad9af --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vuint8mf8_t v = *(vuint8mf8_t*)(in + 100); + *(vuint8mf8_t*)(out + 100) = v; + break; + } + case 2:{ + vuint8mf8_t v = *(vuint8mf8_t*)(in + 200); + *(vuint8mf8_t*)(out + 100) = v; + break; + } + case 3:{ + vuint8mf8_t v = *(vuint8mf8_t*)(in + 300); + *(vuint8mf8_t*)(out + 100) = v; + break; + } + default:{ + break; + } + } + for (int i = 0; i < n; i++) + { + vuint8mf8_t v = *(vuint8mf8_t*)(in + i); + *(vuint8mf8_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c new file mode 100644 index 00000000000..ae2caedff27 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vint8mf4_t v = *(vint8mf4_t*)(in + 100); + *(vint8mf4_t*)(out + 100) = v; + break; + } + case 2:{ + vint8mf4_t v = *(vint8mf4_t*)(in + 200); + *(vint8mf4_t*)(out + 100) = v; + break; + } + case 3:{ + vint8mf4_t v = *(vint8mf4_t*)(in + 300); + *(vint8mf4_t*)(out + 100) = v; + break; + } + default:{ + break; + } + } + for (int i = 0; i < n; i++) + { + vint8mf4_t v = *(vint8mf4_t*)(in + i); + *(vint8mf4_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c new file mode 100644 index 00000000000..2378b4006c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vuint8mf4_t v = *(vuint8mf4_t*)(in + 100); + *(vuint8mf4_t*)(out + 100) = v; + break; + } + case 2:{ + vuint8mf4_t v = *(vuint8mf4_t*)(in + 200); + *(vuint8mf4_t*)(out + 100) = v; + break; + } + case 3:{ + vuint8mf4_t v = *(vuint8mf4_t*)(in + 300); + *(vuint8mf4_t*)(out + 100) = v; + break; + } + default:{ + break; + } + } + for (int i = 0; i < n; i++) + { + vuint8mf4_t v = *(vuint8mf4_t*)(in + i); + *(vuint8mf4_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c new file mode 100644 index 00000000000..1de8fc461dc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vint8mf2_t v = *(vint8mf2_t*)(in + 100); + *(vint8mf2_t*)(out + 100) = v; + break; + } + case 2:{ + vint8mf2_t v = *(vint8mf2_t*)(in + 200); + *(vint8mf2_t*)(out + 100) = v; + break; + } + case 3:{ + vint8mf2_t v = *(vint8mf2_t*)(in + 300); + *(vint8mf2_t*)(out + 100) = v; + break; + } + default:{ + break; + } + } + for (int i = 0; i < n; i++) + { + vint8mf2_t v = *(vint8mf2_t*)(in + i); + *(vint8mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c new file mode 100644 index 00000000000..6c77a94ae63 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vuint8mf8_t v = *(vuint8mf8_t*)(in + 100); + *(vuint8mf8_t*)(out + 100) = v; + } + else if (cond == 2) + { + vuint8mf8_t v = *(vuint8mf8_t*)(in + 200); + *(vuint8mf8_t*)(out + 200) = v; + } + else if (cond == 3) + { + vuint8mf8_t v = *(vuint8mf8_t*)(in + 300); + *(vuint8mf8_t*)(out + 300) = v; + } + for (int i = 0; i < n; i++) + { + vuint8mf8_t v = *(vuint8mf8_t*)(in + i); + *(vuint8mf8_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c new file mode 100644 index 00000000000..41100cb04a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vuint8mf2_t v = *(vuint8mf2_t*)(in + 100); + *(vuint8mf2_t*)(out + 100) = v; + break; + } + case 2:{ + vuint8mf2_t v = *(vuint8mf2_t*)(in + 200); + *(vuint8mf2_t*)(out + 100) = v; + break; + } + case 3:{ + vuint8mf2_t v = *(vuint8mf2_t*)(in + 300); + *(vuint8mf2_t*)(out + 100) = v; + break; + } + default:{ + break; + } + } + for (int i = 0; i < n; i++) + { + vuint8mf2_t v = *(vuint8mf2_t*)(in + i); + *(vuint8mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c new file mode 100644 index 00000000000..070899e6e49 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vint16mf4_t v = *(vint16mf4_t*)(in + 100); + *(vint16mf4_t*)(out + 100) = v; + break; + } + case 2:{ + vint16mf4_t v = *(vint16mf4_t*)(in + 200); + *(vint16mf4_t*)(out + 100) = v; + break; + } + case 3:{ + vint16mf4_t v = *(vint16mf4_t*)(in + 300); + *(vint16mf4_t*)(out + 100) = v; + break; + } + default:{ + break; + } + } + for (int i = 0; i < n; i++) + { + vint16mf4_t v = *(vint16mf4_t*)(in + i); + *(vint16mf4_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c new file mode 100644 index 00000000000..1e96191a9fc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vuint16mf4_t v = *(vuint16mf4_t*)(in + 100); + *(vuint16mf4_t*)(out + 100) = v; + break; + } + case 2:{ + vuint16mf4_t v = *(vuint16mf4_t*)(in + 200); + *(vuint16mf4_t*)(out + 100) = v; + break; + } + case 3:{ + vuint16mf4_t v = *(vuint16mf4_t*)(in + 300); + *(vuint16mf4_t*)(out + 100) = v; + break; + } + default:{ + break; + } + } + for (int i = 0; i < n; i++) + { + vuint16mf4_t v = *(vuint16mf4_t*)(in + i); + *(vuint16mf4_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c new file mode 100644 index 00000000000..fa6420822f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vint16mf2_t v = *(vint16mf2_t*)(in + 100); + *(vint16mf2_t*)(out + 100) = v; + break; + } + case 2:{ + vint16mf2_t v = *(vint16mf2_t*)(in + 200); + *(vint16mf2_t*)(out + 100) = v; + break; + } + case 3:{ + vint16mf2_t v = *(vint16mf2_t*)(in + 300); + *(vint16mf2_t*)(out + 100) = v; + break; + } + default:{ + break; + } + } + for (int i = 0; i < n; i++) + { + vint16mf2_t v = *(vint16mf2_t*)(in + i); + *(vint16mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c new file mode 100644 index 00000000000..d0352fccacf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vuint16mf2_t v = *(vuint16mf2_t*)(in + 100); + *(vuint16mf2_t*)(out + 100) = v; + break; + } + case 2:{ + vuint16mf2_t v = *(vuint16mf2_t*)(in + 200); + *(vuint16mf2_t*)(out + 100) = v; + break; + } + case 3:{ + vuint16mf2_t v = *(vuint16mf2_t*)(in + 300); + *(vuint16mf2_t*)(out + 100) = v; + break; + } + default:{ + break; + } + } + for (int i = 0; i < n; i++) + { + vuint16mf2_t v = *(vuint16mf2_t*)(in + i); + *(vuint16mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c new file mode 100644 index 00000000000..ad76c24d294 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vint32mf2_t v = *(vint32mf2_t*)(in + 100); + *(vint32mf2_t*)(out + 100) = v; + break; + } + case 2:{ + vint32mf2_t v = *(vint32mf2_t*)(in + 200); + *(vint32mf2_t*)(out + 100) = v; + break; + } + case 3:{ + vint32mf2_t v = *(vint32mf2_t*)(in + 300); + *(vint32mf2_t*)(out + 100) = v; + break; + } + default:{ + break; + } + } + for (int i = 0; i < n; i++) + { + vint32mf2_t v = *(vint32mf2_t*)(in + i); + *(vint32mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c new file mode 100644 index 00000000000..71a3f4a06f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vuint32mf2_t v = *(vuint32mf2_t*)(in + 100); + *(vuint32mf2_t*)(out + 100) = v; + break; + } + case 2:{ + vuint32mf2_t v = *(vuint32mf2_t*)(in + 200); + *(vuint32mf2_t*)(out + 100) = v; + break; + } + case 3:{ + vuint32mf2_t v = *(vuint32mf2_t*)(in + 300); + *(vuint32mf2_t*)(out + 100) = v; + break; + } + default:{ + break; + } + } + for (int i = 0; i < n; i++) + { + vuint32mf2_t v = *(vuint32mf2_t*)(in + i); + *(vuint32mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c new file mode 100644 index 00000000000..613a028089b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 100); + *(vfloat32mf2_t*)(out + 100) = v; + break; + } + case 2:{ + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 200); + *(vfloat32mf2_t*)(out + 100) = v; + break; + } + case 3:{ + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 300); + *(vfloat32mf2_t*)(out + 100) = v; + break; + } + default:{ + break; + } + } + for (int i = 0; i < n; i++) + { + vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i); + *(vfloat32mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c new file mode 100644 index 00000000000..6a2011b0290 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c @@ -0,0 +1,231 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vbool64_t v = *(vbool64_t*)(in + 100); + *(vbool64_t*)(out + 100) = v; + break; + } + case 2:{ + vbool64_t v = *(vbool64_t*)(in + 200); + *(vbool64_t*)(out + 100) = v; + break; + } + case 3:{ + vbool64_t v = *(vbool64_t*)(in + 300); + *(vbool64_t*)(out + 100) = v; + break; + } + default:{ + break; + } + } + for (int i = 0; i < n; i++) + { + vbool64_t v = *(vbool64_t*)(in + i); + *(vbool64_t*)(out + i) = v; + } +} + +void f2 (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vbool32_t v = *(vbool32_t*)(in + 100); + *(vbool32_t*)(out + 100) = v; + break; + } + case 2:{ + vbool32_t v = *(vbool32_t*)(in + 200); + *(vbool32_t*)(out + 100) = v; + break; + } + case 3:{ + vbool32_t v = *(vbool32_t*)(in + 300); + *(vbool32_t*)(out + 100) = v; + break; + } + default:{ + break; + } + } + for (int i = 0; i < n; i++) + { + vbool32_t v = *(vbool32_t*)(in + i); + *(vbool32_t*)(out + i) = v; + } +} + +void f3 (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vbool16_t v = *(vbool16_t*)(in + 100); + *(vbool16_t*)(out + 100) = v; + break; + } + case 2:{ + vbool16_t v = *(vbool16_t*)(in + 200); + *(vbool16_t*)(out + 100) = v; + break; + } + case 3:{ + vbool16_t v = *(vbool16_t*)(in + 300); + *(vbool16_t*)(out + 100) = v; + break; + } + default:{ + break; + } + } + for (int i = 0; i < n; i++) + { + vbool16_t v = *(vbool16_t*)(in + i); + *(vbool16_t*)(out + i) = v; + } +} + +void f4 (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vbool8_t v = *(vbool8_t*)(in + 100); + *(vbool8_t*)(out + 100) = v; + break; + } + case 2:{ + vbool8_t v = *(vbool8_t*)(in + 200); + *(vbool8_t*)(out + 100) = v; + break; + } + case 3:{ + vbool8_t v = *(vbool8_t*)(in + 300); + *(vbool8_t*)(out + 100) = v; + break; + } + default:{ + break; + } + } + for (int i = 0; i < n; i++) + { + vbool8_t v = *(vbool8_t*)(in + i); + *(vbool8_t*)(out + i) = v; + } +} + +void f5 (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vbool4_t v = *(vbool4_t*)(in + 100); + *(vbool4_t*)(out + 100) = v; + break; + } + case 2:{ + vbool4_t v = *(vbool4_t*)(in + 200); + *(vbool4_t*)(out + 100) = v; + break; + } + case 3:{ + vbool4_t v = *(vbool4_t*)(in + 300); + *(vbool4_t*)(out + 100) = v; + break; + } + default:{ + break; + } + } + for (int i = 0; i < n; i++) + { + vbool4_t v = *(vbool4_t*)(in + i); + *(vbool4_t*)(out + i) = v; + } +} + +void f6 (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vbool2_t v = *(vbool2_t*)(in + 100); + *(vbool2_t*)(out + 100) = v; + break; + } + case 2:{ + vbool2_t v = *(vbool2_t*)(in + 200); + *(vbool2_t*)(out + 100) = v; + break; + } + case 3:{ + vbool2_t v = *(vbool2_t*)(in + 300); + *(vbool2_t*)(out + 100) = v; + break; + } + default:{ + break; + } + } + for (int i = 0; i < n; i++) + { + vbool2_t v = *(vbool2_t*)(in + i); + *(vbool2_t*)(out + i) = v; + } +} + +void f7 (void * restrict in, void * restrict out, int n, int cond) +{ + switch (cond) + { + case 1:{ + vbool1_t v = *(vbool1_t*)(in + 100); + *(vbool1_t*)(out + 100) = v; + break; + } + case 2:{ + vbool1_t v = *(vbool1_t*)(in + 200); + *(vbool1_t*)(out + 100) = v; + break; + } + case 3:{ + vbool1_t v = *(vbool1_t*)(in + 300); + *(vbool1_t*)(out + 100) = v; + break; + } + default:{ + break; + } + } + for (int i = 0; i < n; i++) + { + vbool1_t v = *(vbool1_t*)(in + i); + *(vbool1_t*)(out + i) = v; + } +} +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c new file mode 100644 index 00000000000..a03f36ab1c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vint8mf4_t v = *(vint8mf4_t*)(in + 100); + *(vint8mf4_t*)(out + 100) = v; + } + else if (cond == 2) + { + vint8mf4_t v = *(vint8mf4_t*)(in + 200); + *(vint8mf4_t*)(out + 200) = v; + } + else if (cond == 3) + { + vint8mf4_t v = *(vint8mf4_t*)(in + 300); + *(vint8mf4_t*)(out + 300) = v; + } + for (int i = 0; i < n; i++) + { + vint8mf4_t v = *(vint8mf4_t*)(in + i); + *(vint8mf4_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c new file mode 100644 index 00000000000..ab16ef2e148 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vuint8mf4_t v = *(vuint8mf4_t*)(in + 100); + *(vuint8mf4_t*)(out + 100) = v; + } + else if (cond == 2) + { + vuint8mf4_t v = *(vuint8mf4_t*)(in + 200); + *(vuint8mf4_t*)(out + 200) = v; + } + else if (cond == 3) + { + vuint8mf4_t v = *(vuint8mf4_t*)(in + 300); + *(vuint8mf4_t*)(out + 300) = v; + } + for (int i = 0; i < n; i++) + { + vuint8mf4_t v = *(vuint8mf4_t*)(in + i); + *(vuint8mf4_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c new file mode 100644 index 00000000000..7722b9eef1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vint8mf2_t v = *(vint8mf2_t*)(in + 100); + *(vint8mf2_t*)(out + 100) = v; + } + else if (cond == 2) + { + vint8mf2_t v = *(vint8mf2_t*)(in + 200); + *(vint8mf2_t*)(out + 200) = v; + } + else if (cond == 3) + { + vint8mf2_t v = *(vint8mf2_t*)(in + 300); + *(vint8mf2_t*)(out + 300) = v; + } + for (int i = 0; i < n; i++) + { + vint8mf2_t v = *(vint8mf2_t*)(in + i); + *(vint8mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c new file mode 100644 index 00000000000..7ec497129b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vuint8mf2_t v = *(vuint8mf2_t*)(in + 100); + *(vuint8mf2_t*)(out + 100) = v; + } + else if (cond == 2) + { + vuint8mf2_t v = *(vuint8mf2_t*)(in + 200); + *(vuint8mf2_t*)(out + 200) = v; + } + else if (cond == 3) + { + vuint8mf2_t v = *(vuint8mf2_t*)(in + 300); + *(vuint8mf2_t*)(out + 300) = v; + } + for (int i = 0; i < n; i++) + { + vuint8mf2_t v = *(vuint8mf2_t*)(in + i); + *(vuint8mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c new file mode 100644 index 00000000000..2772de06151 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vint16mf4_t v = *(vint16mf4_t*)(in + 100); + *(vint16mf4_t*)(out + 100) = v; + } + else if (cond == 2) + { + vint16mf4_t v = *(vint16mf4_t*)(in + 200); + *(vint16mf4_t*)(out + 200) = v; + } + else if (cond == 3) + { + vint16mf4_t v = *(vint16mf4_t*)(in + 300); + *(vint16mf4_t*)(out + 300) = v; + } + for (int i = 0; i < n; i++) + { + vint16mf4_t v = *(vint16mf4_t*)(in + i); + *(vint16mf4_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c new file mode 100644 index 00000000000..124c09b485a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vuint16mf4_t v = *(vuint16mf4_t*)(in + 100); + *(vuint16mf4_t*)(out + 100) = v; + } + else if (cond == 2) + { + vuint16mf4_t v = *(vuint16mf4_t*)(in + 200); + *(vuint16mf4_t*)(out + 200) = v; + } + else if (cond == 3) + { + vuint16mf4_t v = *(vuint16mf4_t*)(in + 300); + *(vuint16mf4_t*)(out + 300) = v; + } + for (int i = 0; i < n; i++) + { + vuint16mf4_t v = *(vuint16mf4_t*)(in + i); + *(vuint16mf4_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c new file mode 100644 index 00000000000..7699a4408ad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32" } */ + +#include "riscv_vector.h" + +/* The for loop body should not have vsetvl instruction. */ +void f (void * restrict in, void * restrict out, int n, int cond) +{ + if (cond == 1) + { + vint16mf2_t v = *(vint16mf2_t*)(in + 100); + *(vint16mf2_t*)(out + 100) = v; + } + else if (cond == 2) + { + vint16mf2_t v = *(vint16mf2_t*)(in + 200); + *(vint16mf2_t*)(out + 200) = v; + } + else if (cond == 3) + { + vint16mf2_t v = *(vint16mf2_t*)(in + 300); + *(vint16mf2_t*)(out + 300) = v; + } + for (int i = 0; i < n; i++) + { + vint16mf2_t v = *(vint16mf2_t*)(in + i); + *(vint16mf2_t*)(out + i) = v; + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */