diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c
new file mode 100644
index 00000000000..1c32dc3f844
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 100);
+      *(vint8mf8_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 200);
+      *(vint8mf8_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 300);
+      *(vint8mf8_t*)(out + 300) = v;
+    }
+  else
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 400);
+      *(vint8mf8_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + i);
+      *(vint8mf8_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,\.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c
new file mode 100644
index 00000000000..e0cee66c2d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + 100);
+      *(vuint16mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + 200);
+      *(vuint16mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + 300);
+      *(vuint16mf2_t*)(out + 300) = v;
+    }
+  else
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + 400);
+      *(vuint16mf2_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + i);
+      *(vuint16mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c
new file mode 100644
index 00000000000..67867dbf4c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + 100);
+      *(vint32mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+      *(vint32mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + 300);
+      *(vint32mf2_t*)(out + 300) = v;
+    }
+  else
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + 400);
+      *(vint32mf2_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + i);
+      *(vint32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c
new file mode 100644
index 00000000000..530604218da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + 100);
+      *(vuint32mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + 200);
+      *(vuint32mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + 300);
+      *(vuint32mf2_t*)(out + 300) = v;
+    }
+  else
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + 400);
+      *(vuint32mf2_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + i);
+      *(vuint32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c
new file mode 100644
index 00000000000..3c7951ab67e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 100);
+      *(vfloat32mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 200);
+      *(vfloat32mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 300);
+      *(vfloat32mf2_t*)(out + 300) = v;
+    }
+  else
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+      *(vfloat32mf2_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i);
+      *(vfloat32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c
new file mode 100644
index 00000000000..b44d28fd77a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c
@@ -0,0 +1,217 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool64_t v = *(vbool64_t*)(in + 100);
+      *(vbool64_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool64_t v = *(vbool64_t*)(in + 200);
+      *(vbool64_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool64_t v = *(vbool64_t*)(in + 300);
+      *(vbool64_t*)(out + 300) = v;
+    }
+  else
+    {
+      vbool64_t v = *(vbool64_t*)(in + 400);
+      *(vbool64_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool64_t v = *(vbool64_t*)(in + i);
+      *(vbool64_t*)(out + i) = v;
+    }
+}
+
+void f2 (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool32_t v = *(vbool32_t*)(in + 100);
+      *(vbool32_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool32_t v = *(vbool32_t*)(in + 200);
+      *(vbool32_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool32_t v = *(vbool32_t*)(in + 300);
+      *(vbool32_t*)(out + 300) = v;
+    }
+  else
+    {
+      vbool32_t v = *(vbool32_t*)(in + 400);
+      *(vbool32_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool32_t v = *(vbool32_t*)(in + i);
+      *(vbool32_t*)(out + i) = v;
+    }
+}
+
+void f3 (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool16_t v = *(vbool16_t*)(in + 100);
+      *(vbool16_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool16_t v = *(vbool16_t*)(in + 200);
+      *(vbool16_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool16_t v = *(vbool16_t*)(in + 300);
+      *(vbool16_t*)(out + 300) = v;
+    }
+  else
+    {
+      vbool16_t v = *(vbool16_t*)(in + 400);
+      *(vbool16_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool16_t v = *(vbool16_t*)(in + i);
+      *(vbool16_t*)(out + i) = v;
+    }
+}
+
+void f4 (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool8_t v = *(vbool8_t*)(in + 100);
+      *(vbool8_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool8_t v = *(vbool8_t*)(in + 200);
+      *(vbool8_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool8_t v = *(vbool8_t*)(in + 300);
+      *(vbool8_t*)(out + 300) = v;
+    }
+  else
+    {
+      vbool8_t v = *(vbool8_t*)(in + 400);
+      *(vbool8_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool8_t v = *(vbool8_t*)(in + i);
+      *(vbool8_t*)(out + i) = v;
+    }
+}
+
+void f5 (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool4_t v = *(vbool4_t*)(in + 100);
+      *(vbool4_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool4_t v = *(vbool4_t*)(in + 200);
+      *(vbool4_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool4_t v = *(vbool4_t*)(in + 300);
+      *(vbool4_t*)(out + 300) = v;
+    }
+  else
+    {
+      vbool4_t v = *(vbool4_t*)(in + 400);
+      *(vbool4_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool4_t v = *(vbool4_t*)(in + i);
+      *(vbool4_t*)(out + i) = v;
+    }
+}
+
+void f6 (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool2_t v = *(vbool2_t*)(in + 100);
+      *(vbool2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool2_t v = *(vbool2_t*)(in + 200);
+      *(vbool2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool2_t v = *(vbool2_t*)(in + 300);
+      *(vbool2_t*)(out + 300) = v;
+    }
+  else
+    {
+      vbool2_t v = *(vbool2_t*)(in + 400);
+      *(vbool2_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool2_t v = *(vbool2_t*)(in + i);
+      *(vbool2_t*)(out + i) = v;
+    }
+}
+
+void f7 (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool1_t v = *(vbool1_t*)(in + 100);
+      *(vbool1_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool1_t v = *(vbool1_t*)(in + 200);
+      *(vbool1_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool1_t v = *(vbool1_t*)(in + 300);
+      *(vbool1_t*)(out + 300) = v;
+    }
+  else
+    {
+      vbool1_t v = *(vbool1_t*)(in + 400);
+      *(vbool1_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool1_t v = *(vbool1_t*)(in + i);
+      *(vbool1_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s+\.L[0-9]+\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 7 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c
new file mode 100644
index 00000000000..06d3ffd0020
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vint8mf8_t v = *(vint8mf8_t*)(in + 100);
+    *(vint8mf8_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vint8mf8_t v = *(vint8mf8_t*)(in + 200);
+    *(vint8mf8_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vint8mf8_t v = *(vint8mf8_t*)(in + 300);
+    *(vint8mf8_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vint8mf8_t v = *(vint8mf8_t*)(in + 400);
+    *(vint8mf8_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + i);
+      *(vint8mf8_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c
new file mode 100644
index 00000000000..141602b9239
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 100);
+    *(vuint8mf8_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 200);
+    *(vuint8mf8_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 300);
+    *(vuint8mf8_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 400);
+    *(vuint8mf8_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + i);
+      *(vuint8mf8_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c
new file mode 100644
index 00000000000..345d799bc6c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vint8mf4_t v = *(vint8mf4_t*)(in + 100);
+    *(vint8mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vint8mf4_t v = *(vint8mf4_t*)(in + 200);
+    *(vint8mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vint8mf4_t v = *(vint8mf4_t*)(in + 300);
+    *(vint8mf4_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vint8mf4_t v = *(vint8mf4_t*)(in + 400);
+    *(vint8mf4_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + i);
+      *(vint8mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c
new file mode 100644
index 00000000000..bce14e29791
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 100);
+    *(vuint8mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 200);
+    *(vuint8mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 300);
+    *(vuint8mf4_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 400);
+    *(vuint8mf4_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + i);
+      *(vuint8mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c
new file mode 100644
index 00000000000..a0e3b5703a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vint8mf2_t v = *(vint8mf2_t*)(in + 100);
+    *(vint8mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vint8mf2_t v = *(vint8mf2_t*)(in + 200);
+    *(vint8mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vint8mf2_t v = *(vint8mf2_t*)(in + 300);
+    *(vint8mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vint8mf2_t v = *(vint8mf2_t*)(in + 400);
+    *(vint8mf2_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + i);
+      *(vint8mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"   } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"   } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c
new file mode 100644
index 00000000000..01b9a50389d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + 100);
+      *(vuint8mf8_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + 200);
+      *(vuint8mf8_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + 300);
+      *(vuint8mf8_t*)(out + 300) = v;
+    }
+  else
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + 400);
+      *(vuint8mf8_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + i);
+      *(vuint8mf8_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"  no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c
new file mode 100644
index 00000000000..c41022dce3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 100);
+    *(vuint8mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 200);
+    *(vuint8mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 300);
+    *(vuint8mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 400);
+    *(vuint8mf2_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + i);
+      *(vuint8mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c
new file mode 100644
index 00000000000..d90a06ce544
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vint16mf4_t v = *(vint16mf4_t*)(in + 100);
+    *(vint16mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vint16mf4_t v = *(vint16mf4_t*)(in + 200);
+    *(vint16mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vint16mf4_t v = *(vint16mf4_t*)(in + 300);
+    *(vint16mf4_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vint16mf4_t v = *(vint16mf4_t*)(in + 400);
+    *(vint16mf4_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + i);
+      *(vint16mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c
new file mode 100644
index 00000000000..6527a0a67dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 100);
+    *(vuint16mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 200);
+    *(vuint16mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 300);
+    *(vuint16mf4_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 400);
+    *(vuint16mf4_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + i);
+      *(vuint16mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c
new file mode 100644
index 00000000000..dc09782eb2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vint16mf2_t v = *(vint16mf2_t*)(in + 100);
+    *(vint16mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vint16mf2_t v = *(vint16mf2_t*)(in + 200);
+    *(vint16mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vint16mf2_t v = *(vint16mf2_t*)(in + 300);
+    *(vint16mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vint16mf2_t v = *(vint16mf2_t*)(in + 400);
+    *(vint16mf2_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + i);
+      *(vint16mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c
new file mode 100644
index 00000000000..f566156a05e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 100);
+    *(vuint16mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 200);
+    *(vuint16mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 300);
+    *(vuint16mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 400);
+    *(vuint16mf2_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + i);
+      *(vuint16mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c
new file mode 100644
index 00000000000..4f2ca827705
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vint32mf2_t v = *(vint32mf2_t*)(in + 100);
+    *(vint32mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vint32mf2_t v = *(vint32mf2_t*)(in + 300);
+    *(vint32mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vint32mf2_t v = *(vint32mf2_t*)(in + 400);
+    *(vint32mf2_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + i);
+      *(vint32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c
new file mode 100644
index 00000000000..9c0a07bc05d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 100);
+    *(vuint32mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 200);
+    *(vuint32mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 300);
+    *(vuint32mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 400);
+    *(vuint32mf2_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + i);
+      *(vuint32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c
new file mode 100644
index 00000000000..6d78052cc61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 100);
+    *(vfloat32mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 200);
+    *(vfloat32mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 300);
+    *(vfloat32mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i);
+      *(vfloat32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c
new file mode 100644
index 00000000000..cdd1d3a2e19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c
@@ -0,0 +1,237 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool64_t v = *(vbool64_t*)(in + 100);
+    *(vbool64_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool64_t v = *(vbool64_t*)(in + 200);
+    *(vbool64_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool64_t v = *(vbool64_t*)(in + 300);
+    *(vbool64_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vbool64_t v = *(vbool64_t*)(in + 400);
+    *(vbool64_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool64_t v = *(vbool64_t*)(in + i);
+      *(vbool64_t*)(out + i) = v;
+    }
+}
+
+void f2 (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool32_t v = *(vbool32_t*)(in + 100);
+    *(vbool32_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool32_t v = *(vbool32_t*)(in + 200);
+    *(vbool32_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool32_t v = *(vbool32_t*)(in + 300);
+    *(vbool32_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vbool32_t v = *(vbool32_t*)(in + 400);
+    *(vbool32_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool32_t v = *(vbool32_t*)(in + i);
+      *(vbool32_t*)(out + i) = v;
+    }
+}
+
+void f3 (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool16_t v = *(vbool16_t*)(in + 100);
+    *(vbool16_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool16_t v = *(vbool16_t*)(in + 200);
+    *(vbool16_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool16_t v = *(vbool16_t*)(in + 300);
+    *(vbool16_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vbool16_t v = *(vbool16_t*)(in + 400);
+    *(vbool16_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool16_t v = *(vbool16_t*)(in + i);
+      *(vbool16_t*)(out + i) = v;
+    }
+}
+
+void f4 (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool8_t v = *(vbool8_t*)(in + 100);
+    *(vbool8_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool8_t v = *(vbool8_t*)(in + 200);
+    *(vbool8_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool8_t v = *(vbool8_t*)(in + 300);
+    *(vbool8_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vbool8_t v = *(vbool8_t*)(in + 400);
+    *(vbool8_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool8_t v = *(vbool8_t*)(in + i);
+      *(vbool8_t*)(out + i) = v;
+    }
+}
+
+void f5 (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool4_t v = *(vbool4_t*)(in + 100);
+    *(vbool4_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool4_t v = *(vbool4_t*)(in + 200);
+    *(vbool4_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool4_t v = *(vbool4_t*)(in + 300);
+    *(vbool4_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vbool4_t v = *(vbool4_t*)(in + 400);
+    *(vbool4_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool4_t v = *(vbool4_t*)(in + i);
+      *(vbool4_t*)(out + i) = v;
+    }
+}
+
+void f6 (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool2_t v = *(vbool2_t*)(in + 100);
+    *(vbool2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool2_t v = *(vbool2_t*)(in + 200);
+    *(vbool2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool2_t v = *(vbool2_t*)(in + 300);
+    *(vbool2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vbool2_t v = *(vbool2_t*)(in + 400);
+    *(vbool2_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool2_t v = *(vbool2_t*)(in + i);
+      *(vbool2_t*)(out + i) = v;
+    }
+}
+
+void f7 (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool1_t v = *(vbool1_t*)(in + 100);
+    *(vbool1_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool1_t v = *(vbool1_t*)(in + 200);
+    *(vbool1_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool1_t v = *(vbool1_t*)(in + 300);
+    *(vbool1_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vbool1_t v = *(vbool1_t*)(in + 400);
+    *(vbool1_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool1_t v = *(vbool1_t*)(in + i);
+      *(vbool1_t*)(out + i) = v;
+    }
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vlm\.v\s*(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 7 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c
new file mode 100644
index 00000000000..ddfc938bcc4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + 100);
+      *(vint8mf4_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + 200);
+      *(vint8mf4_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + 300);
+      *(vint8mf4_t*)(out + 300) = v;
+    }
+  else
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + 400);
+      *(vint8mf4_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + i);
+      *(vint8mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"   no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"   no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c
new file mode 100644
index 00000000000..a6cb700185f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + 100);
+      *(vuint8mf4_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + 200);
+      *(vuint8mf4_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + 300);
+      *(vuint8mf4_t*)(out + 300) = v;
+    }
+  else
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + 400);
+      *(vuint8mf4_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + i);
+      *(vuint8mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"  no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"  no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c
new file mode 100644
index 00000000000..1da94b4486d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + 100);
+      *(vint8mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + 200);
+      *(vint8mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + 300);
+      *(vint8mf2_t*)(out + 300) = v;
+    }
+  else
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + 400);
+      *(vint8mf2_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + i);
+      *(vint8mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c
new file mode 100644
index 00000000000..19d005f70ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + 100);
+      *(vuint8mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + 200);
+      *(vuint8mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + 300);
+      *(vuint8mf2_t*)(out + 300) = v;
+    }
+  else
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + 400);
+      *(vuint8mf2_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + i);
+      *(vuint8mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c
new file mode 100644
index 00000000000..6eabe9cb0ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 100);
+      *(vint16mf4_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 200);
+      *(vint16mf4_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 300);
+      *(vint16mf4_t*)(out + 300) = v;
+    }
+  else
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 400);
+      *(vint16mf4_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + i);
+      *(vint16mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c
new file mode 100644
index 00000000000..811f7b3f9a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + 100);
+      *(vuint16mf4_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + 200);
+      *(vuint16mf4_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + 300);
+      *(vuint16mf4_t*)(out + 300) = v;
+    }
+  else
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + 400);
+      *(vuint16mf4_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + i);
+      *(vuint16mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c
new file mode 100644
index 00000000000..a91eca7f3dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + 100);
+      *(vint16mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + 200);
+      *(vint16mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + 300);
+      *(vint16mf2_t*)(out + 300) = v;
+    }
+  else
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + 400);
+      *(vint16mf2_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + i);
+      *(vint16mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c
new file mode 100644
index 00000000000..023827b2ebc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vint16mf4_t v2 = *(vint16mf4_t*)(in + 2);
+  vint32mf2_t v3 = *(vint32mf2_t*)(in + 3);
+  vfloat32mf2_t v4 = *(vfloat32mf2_t*)(in + 4);
+  
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+  *(vint32mf2_t*)(out + 3) = v3;
+  *(vfloat32mf2_t*)(out + 4) = v4;
+  
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + i + 5);
+      *(vint8mf8_t*)(out + i + 5) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
new file mode 100644
index 00000000000..6c97f3c1cc3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond)
+{
+  vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000);
+  *(vfloat32mf2_t*)(out + 10000) = v;
+
+  if (cond)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 30000);
+      *(vfloat32mf2_t*)(out + 30000) = v;
+    }
+  else
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + 20000);
+      *(vint16mf2_t*)(out + 20000) = v;
+    }
+
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100);
+      
+      vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200);
+      vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300);
+      vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400);
+      vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500);
+      vbool1_t v5 = *(vbool1_t*)(in + i + 600);
+
+      vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700);
+
+      *(vint32mf2_t*)(out + i + 100) = v0;
+      *(vint16mf2_t*)(out + i + 200) = v1;
+      *(vint8mf2_t*)(out + i + 300) = v2;
+      *(vint8mf4_t*)(out + i + 400) = v3;
+      *(vint8mf8_t*)(out + i + 500) = v4;
+      *(vbool1_t*)(out + i + 600) = v5;
+      *(vint32mf2_t*)(out + i + 700) = v6;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {\s*\.L[0-9]+:\s*vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
new file mode 100644
index 00000000000..a6530a2712f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond1, int cond2)
+{
+  vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000);
+  *(vfloat32mf2_t*)(out + 10000) = v;
+
+  if (cond1)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 30000);
+      *(vfloat32mf2_t*)(out + 30000) = v;
+    }
+  else
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 20000);
+      *(vint8mf8_t*)(out + 20000) = v;
+    }
+
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100);
+      
+      vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200);
+      vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300);
+      vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400);
+      vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500);
+      vbool1_t v5 = *(vbool1_t*)(in + i + 600);
+
+      vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700);
+
+      *(vint32mf2_t*)(out + i + 100) = v0;
+      *(vint16mf2_t*)(out + i + 200) = v1;
+      *(vint8mf2_t*)(out + i + 300) = v2;
+      *(vint8mf4_t*)(out + i + 400) = v3;
+      *(vint8mf8_t*)(out + i + 500) = v4;
+      *(vbool1_t*)(out + i + 600) = v5;
+      *(vint32mf2_t*)(out + i + 700) = v6;
+    }
+  
+  if (cond2)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 40000);
+      *(vfloat32mf2_t*)(out + 40000) = v;
+    }
+  else
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 30000);
+      *(vint16mf4_t*)(out + 30000) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
new file mode 100644
index 00000000000..e96f246ece7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond1, int cond2)
+{
+  vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000);
+  *(vfloat32mf2_t*)(out + 10000) = v;
+
+  if (cond1)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 30000);
+      *(vfloat32mf2_t*)(out + 30000) = v;
+    }
+  else
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + 20000);
+      *(vint8mf2_t*)(out + 20000) = v;
+    }
+
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100);
+      
+      vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200);
+      vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300);
+      vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400);
+      vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500);
+      vbool1_t v5 = *(vbool1_t*)(in + i + 600);
+
+      vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700);
+
+      *(vint32mf2_t*)(out + i + 100) = v0;
+      *(vint16mf2_t*)(out + i + 200) = v1;
+      *(vint8mf2_t*)(out + i + 300) = v2;
+      *(vint8mf4_t*)(out + i + 400) = v3;
+      *(vint8mf8_t*)(out + i + 500) = v4;
+      *(vbool1_t*)(out + i + 600) = v5;
+      *(vint32mf2_t*)(out + i + 700) = v6;
+    }
+  
+  if (cond2)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 40000);
+      *(vfloat32mf2_t*)(out + 40000) = v;
+    }
+  else
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 30000);
+      *(vint16mf4_t*)(out + 30000) = v;
+    }
+}
+/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+j\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c
new file mode 100644
index 00000000000..f6ca90bb3a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n)
+{
+  vint8mf8_t v1;
+  vint16mf4_t v2;
+  
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c
new file mode 100644
index 00000000000..1bdb3626c86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int32_t * a, int32_t * b, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    a[i] = a[i] + b[i];
+  }
+  for (int i = 0; i < n; i++) {
+    a[i] = a[i] * b[i];
+  }
+  for (int i = 0; i < n; i++) {
+    a[i] = a[i] - b[i];
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v;
+    *(vint32mf2_t*)(out + i + 7000) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v;
+    *(vint64m1_t*)(out + i + 8000) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v;
+    *(vint8mf8_t*)(out + i + 9000) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c
new file mode 100644
index 00000000000..2b35de00a25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int32_t * a, int32_t * b, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    a[i] = a[i] + b[i];
+  }
+  for (int i = 0; i < n; i++) {
+    a[i] = a[i] * b[i];
+  }
+  for (int i = 0; i < n; i++) {
+    a[i] = a[i] - b[i];
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v;
+    *(vint32mf2_t*)(out + i + 7000) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint16mf2_t v;
+    *(vint16mf2_t*)(out + i + 777) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v;
+    *(vint64m1_t*)(out + i + 8000) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v;
+    *(vfloat32mf2_t*)(out + i + 7777) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vuint16mf2_t v;
+    *(vuint16mf2_t*)(out + i + 888) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v;
+    *(vint8mf8_t*)(out + i + 9000) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c
new file mode 100644
index 00000000000..a04ab3674b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c
@@ -0,0 +1,60 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int32_t * a, int32_t * b, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    a[i] = a[i] + b[i];
+  }
+  for (int i = 0; i < n; i++) {
+    a[i] = a[i] * b[i];
+  }
+  for (int i = 0; i < n; i++) {
+    a[i] = a[i] - b[i];
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v;
+    *(vint32mf2_t*)(out + i + 7000) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint16mf2_t v;
+    *(vint16mf2_t*)(out + i + 777) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v;
+    *(vint64m1_t*)(out + i + 8000) = v;
+  }
+  if (cond == 0) {
+    vbool64_t v;
+    *(vbool64_t*)(out + 1234) = v;
+  } else {
+    vuint8mf8_t v;
+    *(vuint8mf8_t*)(out + 5432) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v;
+    *(vfloat32mf2_t*)(out + i + 7777) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vuint16mf2_t v;
+    *(vuint16mf2_t*)(out + i + 888) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v;
+    *(vint8mf8_t*)(out + i + 9000) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 10 { target { no-opts "-O0" no-opts "-O1" no-opts "-funroll-loops" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c
new file mode 100644
index 00000000000..623978f27e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vint16mf4_t v2 = *(vint16mf4_t*)(in + 2);
+  vint32mf2_t v3 = *(vint32mf2_t*)(in + 3);
+  vfloat32mf2_t v4 = *(vfloat32mf2_t*)(in + 4);
+  
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+  *(vint32mf2_t*)(out + 3) = v3;
+  *(vfloat32mf2_t*)(out + 4) = v4;
+  
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + i + 5);
+      *(vint16mf4_t*)(out + i + 5) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c
new file mode 100644
index 00000000000..30c2e061c13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vint16mf4_t v2 = *(vint16mf4_t*)(in + 2);
+  vint32mf2_t v3 = *(vint32mf2_t*)(in + 3);
+  vfloat32mf2_t v4 = *(vfloat32mf2_t*)(in + 4);
+  
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+  *(vint32mf2_t*)(out + 3) = v3;
+  *(vfloat32mf2_t*)(out + 4) = v4;
+  
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + i + 5);
+      *(vint16mf2_t*)(out + i + 5) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
new file mode 100644
index 00000000000..280192aecb5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n)
+{
+  vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000);
+  *(vfloat32mf2_t*)(out + 10000) = v;
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 1);
+      vint32mf2_t v2 = *(vint32mf2_t*)(in + i + 2);
+      *(vint16mf2_t*)(out + i + 1) = v1;
+      *(vint32mf2_t*)(out + i + 2) = v2;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
new file mode 100644
index 00000000000..280192aecb5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n)
+{
+  vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000);
+  *(vfloat32mf2_t*)(out + 10000) = v;
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 1);
+      vint32mf2_t v2 = *(vint32mf2_t*)(in + i + 2);
+      *(vint16mf2_t*)(out + i + 1) = v1;
+      *(vint32mf2_t*)(out + i + 2) = v2;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
new file mode 100644
index 00000000000..52bb793a057
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void foo (void * restrict in, void * restrict out, int n)
+{
+  vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000);
+  *(vfloat32mf2_t*)(out + 10000) = v;
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100);
+      
+      vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200);
+      vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300);
+      vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400);
+      vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500);
+      vbool1_t v5 = *(vbool1_t*)(in + i + 600);
+
+      vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700);
+
+      *(vint32mf2_t*)(out + i + 100) = v0;
+      *(vint16mf2_t*)(out + i + 200) = v1;
+      *(vint8mf2_t*)(out + i + 300) = v2;
+      *(vint8mf4_t*)(out + i + 400) = v3;
+      *(vint8mf8_t*)(out + i + 500) = v4;
+      *(vbool1_t*)(out + i + 600) = v5;
+      *(vint32mf2_t*)(out + i + 700) = v6;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
new file mode 100644
index 00000000000..97df1e354db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void foo (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000);
+  *(vfloat32mf2_t*)(out + 10000) = v;
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100);
+      
+      vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200);
+      vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300);
+      vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400);
+      vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500);
+      vbool1_t v5 = *(vbool1_t*)(in + i + 600);
+
+      vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700);
+
+      *(vint32mf2_t*)(out + i + 100) = v0;
+      *(vint16mf2_t*)(out + i + 200) = v1;
+      *(vint8mf2_t*)(out + i + 300) = v2;
+      *(vint8mf4_t*)(out + i + 400) = v3;
+      *(vint8mf8_t*)(out + i + 500) = v4;
+      *(vbool1_t*)(out + i + 600) = v5;
+      *(vint32mf2_t*)(out + i + 700) = v6;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
new file mode 100644
index 00000000000..57c9dd839a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
@@ -0,0 +1,45 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond)
+{
+  vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000);
+  *(vfloat32mf2_t*)(out + 10000) = v;
+
+  if (cond)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 20000);
+      *(vfloat32mf2_t*)(out + 20000) = v;
+    }
+  else
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 20000);
+      *(vint16mf4_t*)(out + 20000) = v;
+    }
+
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100);
+      
+      vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200);
+      vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300);
+      vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400);
+      vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500);
+      vbool1_t v5 = *(vbool1_t*)(in + i + 600);
+
+      vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700);
+
+      *(vint32mf2_t*)(out + i + 100) = v0;
+      *(vint16mf2_t*)(out + i + 200) = v1;
+      *(vint8mf2_t*)(out + i + 300) = v2;
+      *(vint8mf4_t*)(out + i + 400) = v3;
+      *(vint8mf8_t*)(out + i + 500) = v4;
+      *(vbool1_t*)(out + i + 600) = v5;
+      *(vint32mf2_t*)(out + i + 700) = v6;
+    }
+}
+/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-not {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16\s*mf4,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
new file mode 100644
index 00000000000..57c9dd839a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
@@ -0,0 +1,45 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond)
+{
+  vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000);
+  *(vfloat32mf2_t*)(out + 10000) = v;
+
+  if (cond)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 20000);
+      *(vfloat32mf2_t*)(out + 20000) = v;
+    }
+  else
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 20000);
+      *(vint16mf4_t*)(out + 20000) = v;
+    }
+
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100);
+      
+      vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200);
+      vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300);
+      vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400);
+      vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500);
+      vbool1_t v5 = *(vbool1_t*)(in + i + 600);
+
+      vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700);
+
+      *(vint32mf2_t*)(out + i + 100) = v0;
+      *(vint16mf2_t*)(out + i + 200) = v1;
+      *(vint8mf2_t*)(out + i + 300) = v2;
+      *(vint8mf4_t*)(out + i + 400) = v3;
+      *(vint8mf8_t*)(out + i + 500) = v4;
+      *(vbool1_t*)(out + i + 600) = v5;
+      *(vint32mf2_t*)(out + i + 700) = v6;
+    }
+}
+/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-not {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16\s*mf4,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
