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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id m6-20020a056402510600b0046443638c9esi12850764edd.262.2022.12.13.23.02.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 23:02:35 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 35277384231F for ; Wed, 14 Dec 2022 07:02:31 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) by sourceware.org (Postfix) with ESMTPS id 298B8384F953 for ; Wed, 14 Dec 2022 07:02:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 298B8384F953 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp84t1671001318tzu31v15 Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 14 Dec 2022 15:01:57 +0800 (CST) X-QQ-SSF: 01400000000000D0L000000A0000000 X-QQ-FEAT: CR3LFp2JE4k6lLBiVl4JPBOaEZJqQItCV4q6CAJ8gTb+wNFu3M72xt3MrUTNt 2OySJryYz7s79p7yOxXBWVKNCuo5ytU+BiepETZyVaPBMq0nRGIIxw5noQVkk34nwzjmxFD TbPJFp9PjwnXZpYKQ2eMs0EvdOorLsjzo1bI5fmanyr8FPkP1NIpnTy57e89qSQaHZApyF9 CKduZ+oTp4SyIlM1K6NNJ6YhJzjgk2zgpDZmQittMr+EN5Uzdk/q2sB+APXYRM6BqdHm5xt wcydNPwYdQbeVumq9qmEYWYqbmtUgUImPD3cZCxjdo44BQZHGYeBUjKI7sAaEph62mqscJ6 5pV1VVO5Q9IR1VCIXxQe/z7GIDagWK5DnB1W2Ius0LwAHjOj9P0QgHn5WyoLjp3BaYKFvBB X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Fix RVV machine mode attribute configuration Date: Wed, 14 Dec 2022 15:01:56 +0800 Message-Id: <20221214070156.37689-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752171916594819032?= X-GMAIL-MSGID: =?utf-8?q?1752171916594819032?= From: Ju-Zhe Zhong The attribute configuration of each machine mode are support in the previous patch. I noticed some of them are not correct during VSETVL PASS testsing. Correct them in the single patch now. gcc/ChangeLog: * config/riscv/riscv-vector-switch.def (ENTRY): Correct attributes. --- gcc/config/riscv/riscv-vector-switch.def | 38 ++++++++++++------------ 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/riscv-vector-switch.def index a51f45be487..ec12be84661 100644 --- a/gcc/config/riscv/riscv-vector-switch.def +++ b/gcc/config/riscv/riscv-vector-switch.def @@ -95,16 +95,16 @@ TODO: FP16 vector needs support of 'zvfh', we don't support it yet. */ #endif /* Mask modes. Disable VNx64BImode when TARGET_MIN_VLEN == 32. */ -ENTRY (VNx64BI, TARGET_MIN_VLEN > 32, LMUL_F8, 64, LMUL_RESERVED, 0) -ENTRY (VNx32BI, true, LMUL_F4, 32, LMUL_RESERVED, 0) -ENTRY (VNx16BI, true, LMUL_F2, 16, LMUL_RESERVED, 0) -ENTRY (VNx8BI, true, LMUL_1, 8, LMUL_RESERVED, 0) -ENTRY (VNx4BI, true, LMUL_2, 4, LMUL_RESERVED, 0) -ENTRY (VNx2BI, true, LMUL_4, 2, LMUL_RESERVED, 0) -ENTRY (VNx1BI, true, LMUL_8, 1, LMUL_RESERVED, 0) +ENTRY (VNx64BI, TARGET_MIN_VLEN > 32, LMUL_RESERVED, 0, LMUL_8, 1) +ENTRY (VNx32BI, true, LMUL_8, 1, LMUL_4, 2) +ENTRY (VNx16BI, true, LMUL_4, 2, LMUL_2, 4) +ENTRY (VNx8BI, true, LMUL_2, 4, LMUL_1, 8) +ENTRY (VNx4BI, true, LMUL_1, 8, LMUL_F2, 16) +ENTRY (VNx2BI, true, LMUL_F2, 16, LMUL_F4, 32) +ENTRY (VNx1BI, true, LMUL_F4, 32, LMUL_F8, 64) /* SEW = 8. Disable VNx64QImode when TARGET_MIN_VLEN == 32. */ -ENTRY (VNx64QI, TARGET_MIN_VLEN > 32, LMUL_8, 1, LMUL_RESERVED, 0) +ENTRY (VNx64QI, TARGET_MIN_VLEN > 32, LMUL_RESERVED, 0, LMUL_8, 1) ENTRY (VNx32QI, true, LMUL_8, 1, LMUL_4, 2) ENTRY (VNx16QI, true, LMUL_4, 2, LMUL_2, 4) ENTRY (VNx8QI, true, LMUL_2, 4, LMUL_1, 8) @@ -113,7 +113,7 @@ ENTRY (VNx2QI, true, LMUL_F2, 16, LMUL_F4, 32) ENTRY (VNx1QI, true, LMUL_F4, 32, LMUL_F8, 64) /* SEW = 16. Disable VNx32HImode when TARGET_MIN_VLEN == 32. */ -ENTRY (VNx32HI, TARGET_MIN_VLEN > 32, LMUL_8, 2, LMUL_RESERVED, 0) +ENTRY (VNx32HI, TARGET_MIN_VLEN > 32, LMUL_RESERVED, 0, LMUL_8, 2) ENTRY (VNx16HI, true, LMUL_8, 2, LMUL_4, 4) ENTRY (VNx8HI, true, LMUL_4, 4, LMUL_2, 8) ENTRY (VNx4HI, true, LMUL_2, 8, LMUL_1, 16) @@ -121,7 +121,7 @@ ENTRY (VNx2HI, true, LMUL_1, 16, LMUL_F2, 32) ENTRY (VNx1HI, true, LMUL_F2, 32, LMUL_F4, 64) /* TODO:Disable all FP16 vector, enable them when 'zvfh' is supported. */ -ENTRY (VNx32HF, false, LMUL_8, 2, LMUL_RESERVED, 0) +ENTRY (VNx32HF, false, LMUL_RESERVED, 0, LMUL_8, 2) ENTRY (VNx16HF, false, LMUL_8, 2, LMUL_4, 4) ENTRY (VNx8HF, false, LMUL_4, 4, LMUL_2, 8) ENTRY (VNx4HF, false, LMUL_2, 8, LMUL_1, 16) @@ -131,18 +131,18 @@ ENTRY (VNx1HF, false, LMUL_F2, 32, LMUL_F4, 64) /* SEW = 32. Disable VNx16SImode when TARGET_MIN_VLEN == 32. For single-precision floating-point, we need TARGET_VECTOR_FP32 == RVV_ENABLE. */ -ENTRY (VNx16SI, TARGET_MIN_VLEN > 32, LMUL_8, 4, LMUL_RESERVED, 0) +ENTRY (VNx16SI, TARGET_MIN_VLEN > 32, LMUL_RESERVED, 0, LMUL_8, 4) ENTRY (VNx8SI, true, LMUL_8, 4, LMUL_4, 8) -ENTRY (VNx4SI, true, LMUL_4, 8, LMUL_2, 4) -ENTRY (VNx2SI, true, LMUL_2, 16, LMUL_1, 2) -ENTRY (VNx1SI, true, LMUL_1, 32, LMUL_F2, 1) +ENTRY (VNx4SI, true, LMUL_4, 8, LMUL_2, 16) +ENTRY (VNx2SI, true, LMUL_2, 16, LMUL_1, 32) +ENTRY (VNx1SI, true, LMUL_1, 32, LMUL_F2, 64) -ENTRY (VNx16SF, TARGET_VECTOR_FP32 && (TARGET_MIN_VLEN > 32), LMUL_8, 4, - LMUL_RESERVED, 0) +ENTRY (VNx16SF, TARGET_VECTOR_FP32 && (TARGET_MIN_VLEN > 32), LMUL_RESERVED, 0, + LMUL_8, 4) ENTRY (VNx8SF, TARGET_VECTOR_FP32, LMUL_8, 4, LMUL_4, 8) -ENTRY (VNx4SF, TARGET_VECTOR_FP32, LMUL_4, 8, LMUL_2, 4) -ENTRY (VNx2SF, TARGET_VECTOR_FP32, LMUL_2, 16, LMUL_1, 2) -ENTRY (VNx1SF, TARGET_VECTOR_FP32, LMUL_1, 32, LMUL_F2, 1) +ENTRY (VNx4SF, TARGET_VECTOR_FP32, LMUL_4, 8, LMUL_2, 16) +ENTRY (VNx2SF, TARGET_VECTOR_FP32, LMUL_2, 16, LMUL_1, 32) +ENTRY (VNx1SF, TARGET_VECTOR_FP32, LMUL_1, 32, LMUL_F2, 64) /* SEW = 64. Enable when TARGET_MIN_VLEN > 32. For double-precision floating-point, we need TARGET_VECTOR_FP64 ==