diff mbox series

RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst

Message ID 20221128142116.245036-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai Nov. 28, 2022, 2:21 p.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

Since mask instruction doesn't need policy, so remove it to make it look reasonable.
gcc/ChangeLog:

        * config/riscv/vector.md: Remove TA && MA operands.

---
 gcc/config/riscv/vector.md | 2 --
 1 file changed, 2 deletions(-)

Comments

Jeff Law Nov. 28, 2022, 4:48 p.m. UTC | #1 
On 11/28/22 07:21, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> Since mask instruction doesn't need policy, so remove it to make it look reasonable.
> gcc/ChangeLog:
>
>          * config/riscv/vector.md: Remove TA && MA operands.

Does this fix a known bug or is it just a cleanup?   I think the latter, 
but I want to be sure.



Jeff
juzhe.zhong@rivai.ai Nov. 28, 2022, 10:52 p.m. UTC | #2 
Yes, it's a cleanup.



juzhe.zhong@rivai.ai
 
From: Jeff Law
Date: 2022-11-29 00:48
To: juzhe.zhong; gcc-patches
CC: kito.cheng; palmer
Subject: Re: [PATCH] RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst
 
On 11/28/22 07:21, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> Since mask instruction doesn't need policy, so remove it to make it look reasonable.
> gcc/ChangeLog:
>
>          * config/riscv/vector.md: Remove TA && MA operands.
 
Does this fix a known bug or is it just a cleanup?   I think the latter, 
but I want to be sure.
 
 
 
Jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 3bb87232d3f..38da2f7f095 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -593,8 +593,6 @@ 
 	  (unspec:VB
 	    [(match_operand:VB 1 "vector_mask_operand"   "Wc1, Wc1, Wc1, Wc1, Wc1")
 	     (match_operand 4 "vector_length_operand"    " rK,  rK,  rK,  rK,  rK")
-	     (match_operand 5 "const_int_operand"        "  i,   i,   i,   i,   i")
-	     (match_operand 6 "const_int_operand"        "  i,   i,   i,   i,   i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (match_operand:VB 3 "vector_move_operand"      "  m,  vr,  vr, Wc0, Wc1")