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Thu, 24 Nov 2022 09:16:57 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DEB9D42041; Thu, 24 Nov 2022 09:16:56 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DF2D94203F; Thu, 24 Nov 2022 09:16:55 +0000 (GMT) Received: from trout.aus.stglabs.ibm.com (unknown [9.40.194.100]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 24 Nov 2022 09:16:55 +0000 (GMT) To: gcc-patches@gcc.gnu.org Cc: Kewen Lin , segher@kernel.crashing.org, dje.gcc@gmail.com, bergner@linux.ibm.com, meissner@linux.ibm.com Subject: [PATCH 4/9] rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p4 Date: Thu, 24 Nov 2022 03:15:52 -0600 Message-Id: <20221124091557.514727-5-linkw@linux.ibm.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221124091557.514727-1-linkw@linux.ibm.com> References: <20221124091557.514727-1-linkw@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 1be5JGENicuoZmHIz53vpBgZq1fS2HXJ X-Proofpoint-GUID: uNA_bIOz9sUWsCc8HQZSw4INBZghHRkA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-24_06,2022-11-23_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 adultscore=0 suspectscore=0 spamscore=0 mlxscore=0 bulkscore=0 phishscore=0 malwarescore=0 mlxlogscore=999 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2211240072 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Kewen Lin via Gcc-patches From: "Kewen.Lin" Reply-To: Kewen Lin Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750368712024078849?= X-GMAIL-MSGID: =?utf-8?q?1750368712024078849?= All kinds of vector float comparison operators have been supported in a rtl comparison pattern as vector.md, we can just emit an rtx comparison insn with the given comparison operator in function rs6000_emit_vector_compare instead of checking and handling the reverse condition cases. This is part 4, it further checks for comparison opeators LT/UNGE. In rs6000_emit_vector_compare, for the handling of LT, it switches to use code GT, swaps operands and try again, it's exactly the same as what we have in vector.md: ; lt(a,b) = gt(b,a) As to UNGE, in rs6000_emit_vector_compare, it uses reversed code LT and further operates on the result with one_cmpl, it's also the same as what's in vector.md: ; unge(a,b) = ~lt(a,b) This patch should not have any functionality change too. gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_vector_compare_inner): Emit rtx comparison for operators LT/UNGE of MODE_VECTOR_FLOAT directly. (rs6000_emit_vector_compare): Move assertion of no MODE_VECTOR_FLOAT to function beginning. --- gcc/config/rs6000/rs6000.cc | 24 ++++-------------------- 1 file changed, 4 insertions(+), 20 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 98754805bd2..94e039649f5 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -15645,6 +15645,7 @@ static rtx rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1) { machine_mode mode = GET_MODE (op0); + gcc_assert (GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT); switch (code) { @@ -15654,7 +15655,6 @@ rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1) case EQ: case GT: case GTU: - gcc_assert (GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT); rtx mask = gen_reg_rtx (mode); emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, mode, op0, op1))); return mask; @@ -15679,18 +15679,8 @@ rs6000_emit_vector_compare (enum rtx_code rcode, comparison operators in a comparison rtl pattern, we can just emit the comparison rtx insn directly here. Besides, we should have a centralized place to handle the possibility - of raising invalid exception. For EQ/GT/GE/UNORDERED/ - ORDERED/LTGT/UNEQ, they are handled equivalently as before; - for NE/UNLE/UNLT, they are handled with reversed code - and inverting, it's the same as before; for LE/UNGT, they - are handled with LE ior EQ previously, emitting directly - here will make use of GE later, it's slightly better; - - FIXME: Handle the remaining vector float comparison operators - here. */ - if (GET_MODE_CLASS (dmode) == MODE_VECTOR_FLOAT - && rcode != LT - && rcode != UNGE) + of raising invalid exception. */ + if (GET_MODE_CLASS (dmode) == MODE_VECTOR_FLOAT) { mask = gen_reg_rtx (dmode); emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (rcode, dmode, op0, op1))); @@ -15718,23 +15708,17 @@ rs6000_emit_vector_compare (enum rtx_code rcode, try_again = true; break; case NE: - case UNGE: /* Invert condition and try again. e.g., A != B becomes ~(A==B). */ { - enum rtx_code rev_code; enum insn_code nor_code; rtx mask2; - rev_code = reverse_condition_maybe_unordered (rcode); - if (rev_code == UNKNOWN) - return NULL_RTX; - nor_code = optab_handler (one_cmpl_optab, dmode); if (nor_code == CODE_FOR_nothing) return NULL_RTX; - mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode); + mask2 = rs6000_emit_vector_compare (EQ, op0, op1, dmode); if (!mask2) return NULL_RTX;