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Thu, 24 Nov 2022 09:16:45 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1031542045; Thu, 24 Nov 2022 09:16:45 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0EFE74203F; Thu, 24 Nov 2022 09:16:44 +0000 (GMT) Received: from trout.aus.stglabs.ibm.com (unknown [9.40.194.100]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 24 Nov 2022 09:16:43 +0000 (GMT) To: gcc-patches@gcc.gnu.org Cc: Kewen Lin , segher@kernel.crashing.org, dje.gcc@gmail.com, bergner@linux.ibm.com, meissner@linux.ibm.com Subject: [PATCH 1/9] rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p1 Date: Thu, 24 Nov 2022 03:15:49 -0600 Message-Id: <20221124091557.514727-2-linkw@linux.ibm.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221124091557.514727-1-linkw@linux.ibm.com> References: <20221124091557.514727-1-linkw@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: TMWSeFyQLLKJO82sq6Nr7fGCiZpM57LK X-Proofpoint-ORIG-GUID: VZSd3TZIcHwYJi3WMBrdcJ9rCF6TrEdX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-24_05,2022-11-23_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=999 phishscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 mlxscore=0 adultscore=0 malwarescore=0 impostorscore=0 suspectscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2211240072 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Kewen Lin via Gcc-patches From: "Kewen.Lin" Reply-To: Kewen Lin Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750368618186738599?= X-GMAIL-MSGID: =?utf-8?q?1750368618186738599?= All kinds of vector float comparison operators have been supported in a rtl comparison pattern as vector.md, we can just emit an rtx comparison insn with the given comparison operator in function rs6000_emit_vector_compare instead of checking and handling the reverse condition cases. This is part 1, it only handles the operators which are already emitted with an rtx comparison previously in function rs6000_emit_vector_compare_inner, they are EQ/GT/GE/ORDERED/ UNORDERED/UNEQ/LTGT. There is no functionality change. With this change, rs6000_emit_vector_compare_inner would only work for vector integer comparison handling, it would be cleaned up later in vector integer comparison rework. gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_vector_compare_inner): Move MODE_VECTOR_FLOAT handlings out. (rs6000_emit_vector_compare): Emit rtx comparison for operators EQ/GT/ GE/UNORDERED/ORDERED/UNEQ/LTGT of MODE_VECTOR_FLOAT directly, and adjust one call site of rs6000_emit_vector_compare_inner to rs6000_emit_vector_compare. --- gcc/config/rs6000/rs6000.cc | 47 ++++++++++++++++++++++++------------- 1 file changed, 31 insertions(+), 16 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index d2743f7bce6..5a8f7ff3bf8 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -15644,7 +15644,6 @@ output_cbranch (rtx op, const char *label, int reversed, rtx_insn *insn) static rtx rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1) { - rtx mask; machine_mode mode = GET_MODE (op0); switch (code) @@ -15652,19 +15651,11 @@ rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1) default: break; - case GE: - if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT) - return NULL_RTX; - /* FALLTHRU */ - case EQ: case GT: case GTU: - case ORDERED: - case UNORDERED: - case UNEQ: - case LTGT: - mask = gen_reg_rtx (mode); + gcc_assert (GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT); + rtx mask = gen_reg_rtx (mode); emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, mode, op0, op1))); return mask; } @@ -15680,18 +15671,42 @@ rs6000_emit_vector_compare (enum rtx_code rcode, rtx op0, rtx op1, machine_mode dmode) { - rtx mask; - bool swap_operands = false; - bool try_again = false; - gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode)); gcc_assert (GET_MODE (op0) == GET_MODE (op1)); + rtx mask; + + /* In vector.md, we support all kinds of vector float point + comparison operators in a comparison rtl pattern, we can + just emit the comparison rtx insn directly here. Besides, + we should have a centralized place to handle the possibility + of raising invalid exception. As the first step, only check + operators EQ/GT/GE/UNORDERED/ORDERED/LTGT/UNEQ for now, they + are handled equivalently as before. + + FIXME: Handle the remaining vector float comparison operators + here. */ + if (GET_MODE_CLASS (dmode) == MODE_VECTOR_FLOAT + && (rcode == EQ + || rcode == GT + || rcode == GE + || rcode == UNORDERED + || rcode == ORDERED + || rcode == LTGT + || rcode == UNEQ)) + { + mask = gen_reg_rtx (dmode); + emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (rcode, dmode, op0, op1))); + return mask; + } /* See if the comparison works as is. */ mask = rs6000_emit_vector_compare_inner (rcode, op0, op1); if (mask) return mask; + bool swap_operands = false; + bool try_again = false; + switch (rcode) { case LT: @@ -15791,7 +15806,7 @@ rs6000_emit_vector_compare (enum rtx_code rcode, if (swap_operands) std::swap (op0, op1); - mask = rs6000_emit_vector_compare_inner (rcode, op0, op1); + mask = rs6000_emit_vector_compare (rcode, op0, op1, dmode); if (mask) return mask; }