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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id y21-20020ac24215000000b004947984b385sm618291lfh.87.2022.11.18.03.14.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Nov 2022 03:14:35 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Kito Cheng , Palmer Dabbelt , Vineet Gupta , Jeff Law , Christoph Muellner , Philipp Tomsich Subject: [PATCH v2 2/2] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs Date: Fri, 18 Nov 2022 12:10:01 +0100 Message-Id: <20221118111001.1488517-3-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221118111001.1488517-1-philipp.tomsich@vrull.eu> References: <20221118111001.1488517-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749832308615735707?= X-GMAIL-MSGID: =?utf-8?q?1749832308615735707?= Use Zbs when generating a sequence for "if ((a & twobits) == singlebit) ..." that can be expressed as bexti + bexti + andn. gcc/ChangeLog: * config/riscv/bitmanip.md (*branch_mask_twobits_equals_singlebit): Handle "if ((a & T) == C)" using Zbs, when T has 2 bits set and C has one of these tow bits set. * config/riscv/predicates.md (const_twobits_not_arith_operand): New predicate. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbs-if_then_else-01.c: New test. Signed-off-by: Philipp Tomsich --- Changes in v2: - Convert the FAIL into a gcc_assert. - Merge the !SMALL_OPERAND check into a new predicate. - Some of the predicates moved into the other patch of the series due to the order the reviews were processed. gcc/config/riscv/bitmanip.md | 42 +++++++++++++++++++ gcc/config/riscv/predicates.md | 5 +++ .../gcc.target/riscv/zbs-if_then_else-01.c | 20 +++++++++ 3 files changed, 67 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index d7c64270c00..be53aecbb13 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -517,3 +517,45 @@ (define_insn_and_split "*andi_extrabit" operands[3] = GEN_INT (bits | topbit); operands[4] = GEN_INT (~topbit); }) + +;; IF_THEN_ELSE: test for 2 bits of opposite polarity +(define_insn_and_split "*branch_mask_twobits_equals_singlebit" + [(set (pc) + (if_then_else + (match_operator 1 "equality_operator" + [(and:X (match_operand:X 2 "register_operand" "r") + (match_operand:X 3 "const_twobits_not_arith_operand" "i")) + (match_operand:X 4 "single_bit_mask_operand" "i")]) + (label_ref (match_operand 0 "" "")) + (pc))) + (clobber (match_scratch:X 5 "=&r")) + (clobber (match_scratch:X 6 "=&r"))] + "TARGET_ZBS && TARGET_ZBB" + "#" + "&& reload_completed" + [(set (match_dup 5) (zero_extract:X (match_dup 2) + (const_int 1) + (match_dup 8))) + (set (match_dup 6) (zero_extract:X (match_dup 2) + (const_int 1) + (match_dup 9))) + (set (match_dup 6) (and:X (not:X (match_dup 6)) (match_dup 5))) + (set (pc) (if_then_else (match_op_dup 1 [(match_dup 6) (const_int 0)]) + (label_ref (match_dup 0)) + (pc)))] +{ + unsigned HOST_WIDE_INT twobits_mask = UINTVAL (operands[3]); + unsigned HOST_WIDE_INT singlebit_mask = UINTVAL (operands[4]); + + /* We should never see an unsatisfiable condition. */ + gcc_assert (twobits_mask & singlebit_mask); + + int setbit = ctz_hwi (singlebit_mask); + int clearbit = ctz_hwi (twobits_mask & ~singlebit_mask); + + operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == NE ? EQ : NE, + mode, operands[6], GEN_INT(0)); + + operands[8] = GEN_INT (setbit); + operands[9] = GEN_INT (clearbit); +}) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 3300c0e36eb..9e2f7c9b6b3 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -296,6 +296,11 @@ (define_predicate "const_twobits_operand" (and (match_code "const_int") (match_test "popcount_hwi (UINTVAL (op)) == 2"))) +(define_predicate "const_twobits_not_arith_operand" + (and (match_code "const_int") + (and (not (match_operand 0 "arith_operand")) + (match_operand 0 "const_twobits_operand")))) + ;; A CONST_INT operand that fits into the unsigned half of a ;; signed-immediate after the top bit has been cleared (define_predicate "uimm_extra_bit_operand" diff --git a/gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c b/gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c new file mode 100644 index 00000000000..d249a841ff9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbb_zbs -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */ + +void g(); + +void f1 (long a) +{ + if ((a & ((1ul << 33) | (1 << 4))) == (1ul << 33)) + g(); +} + +void f2 (long a) +{ + if ((a & 0x12) == 0x10) + g(); +} + +/* { dg-final { scan-assembler-times "bexti\t" 2 } } */ +/* { dg-final { scan-assembler-times "andn\t" 1 } } */