From patchwork Thu Nov 17 16:37:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Corallo X-Patchwork-Id: 21804 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp501255wrr; Thu, 17 Nov 2022 08:40:49 -0800 (PST) X-Google-Smtp-Source: AA0mqf7WBvP33xrn1Mqw/VzTlwtlgiDIFylr9mqDaSNp7E9R3JteXkBWWDVOtHvOtRNUKfstyPuq X-Received: by 2002:a17:906:8455:b0:7aa:97c7:2c04 with SMTP id e21-20020a170906845500b007aa97c72c04mr2908430ejy.191.1668703248697; Thu, 17 Nov 2022 08:40:48 -0800 (PST) Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id i14-20020a05640242ce00b0046751a6076bsi1334446edc.318.2022.11.17.08.40.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 08:40:48 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=gDtedrlb; arc=fail (signature failed); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4A5AD3AA9818 for ; Thu, 17 Nov 2022 16:39:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4A5AD3AA9818 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668703195; bh=PJ80kCTQW88ozTLEkMSxIjwzoYxUAoD316wdWW2UXiQ=; h=To:CC:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=gDtedrlbXkPE+s5BNswMOBoQ7Xfo6krCvhNMLG5hWMzSR5+c1E2mRvN5dqX738e41 049yzsM0q+YUXYLScmRltnBTWXBuz6/9Y6MQK+vAMswzmzKdo7NwQl63az7h3BD9hW m9GDg+h3RhJSx7ZtMpsrwgHFed2ICQix7w9OzunI= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR03-DBA-obe.outbound.protection.outlook.com (mail-dbaeur03on2074.outbound.protection.outlook.com [40.107.104.74]) by sourceware.org (Postfix) with ESMTPS id 887023AA9407 for ; Thu, 17 Nov 2022 16:38:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 887023AA9407 Received: from AM0PR06CA0079.eurprd06.prod.outlook.com (2603:10a6:208:fa::20) by DU2PR08MB10088.eurprd08.prod.outlook.com (2603:10a6:10:49b::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5834.9; Thu, 17 Nov 2022 16:38:31 +0000 Received: from VI1EUR03FT045.eop-EUR03.prod.protection.outlook.com (2603:10a6:208:fa:cafe::b7) by AM0PR06CA0079.outlook.office365.com (2603:10a6:208:fa::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.19 via Frontend Transport; Thu, 17 Nov 2022 16:38:30 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by VI1EUR03FT045.mail.protection.outlook.com (100.127.144.205) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5834.8 via Frontend Transport; Thu, 17 Nov 2022 16:38:30 +0000 Received: ("Tessian outbound 58faf9791229:v130"); Thu, 17 Nov 2022 16:38:30 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: df88eb10b0b530cc X-CR-MTA-TID: 64aa7808 Received: from 5f22070b3e78.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id FFE002EE-DF1B-4A23-AC97-A15DE11E98FD.1; Thu, 17 Nov 2022 16:38:23 +0000 Received: from EUR01-VE1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 5f22070b3e78.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Thu, 17 Nov 2022 16:38:23 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=i+p+qRg3Ar3jRtfc8kuvXcZFqTBSRgLIxfsR/wXu+KuqE1x1q13d5A7FA9DGEl6jwtlOrj2i/5iHkRMAxqzMv6xxEpERrh4HTX35lvwsn37zz6xOPG7ORoBJfrnP035GrGrsez79bDU2o1HI9psuYgIOFQaM0PnficLYbWxlr0mFpjO1OSDHZS2etDENQNliyl9JbC+IfFzidqpfOu++uza900ubYaxAft3Y05A9gCR6EXoCxH7vnPSYzoPVK8bwYD5wyH/TrVhg6a3WhAgzrI0E1B5V+oE2ZofkKh1WmqvoHU28bOTVjb0xJqlA1sll+tQdGdKAfq/kOyBlEbrsGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PJ80kCTQW88ozTLEkMSxIjwzoYxUAoD316wdWW2UXiQ=; b=AHcEfAZAfOkQQdpwrb0zIw4DYX0I8SzRr7OhYsJZSk8n3GERnG6fax6Rpu9WNMIaHXVHEECZX08c0QUPj+6UGz74D1msOQwVOwgcyrKDW0IlFcbqxm7Ki0fdYkaxUAZgjv/vigK1GLpIkc7f0Ok6wf9t5E9WqaIkPXfMsDWxE8ejcTcKiaGeE0NlgZBRD986uzwP/3i2i8lm09BzQvDvkpjQSITnNCwFZ34OYC0KvLtR+v539/lk0aj33rK4UBmvIrL0S9eS5vQQcg0GRnxednSKYPkMsPqacNtGtSi+of/rQ3M3K0l7mdWotlLA5qXqSBABeOq7lcGEBM3QUxGuUQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none Received: from DB6PR1001CA0042.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:4:55::28) by AS8PR08MB8112.eurprd08.prod.outlook.com (2603:10a6:20b:54e::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5834.6; Thu, 17 Nov 2022 16:38:18 +0000 Received: from DBAEUR03FT013.eop-EUR03.prod.protection.outlook.com (2603:10a6:4:55:cafe::c7) by DB6PR1001CA0042.outlook.office365.com (2603:10a6:4:55::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.18 via Frontend Transport; Thu, 17 Nov 2022 16:38:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by DBAEUR03FT013.mail.protection.outlook.com (100.127.142.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5834.8 via Frontend Transport; Thu, 17 Nov 2022 16:38:18 +0000 Received: from AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Thu, 17 Nov 2022 16:38:17 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Thu, 17 Nov 2022 16:38:17 +0000 Received: from e124257.nice.arm.com (10.34.105.24) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Thu, 17 Nov 2022 16:38:17 +0000 To: CC: , , Andrea Corallo Subject: [PATCH 04/35] arm: improve tests and fix vdwdupq* Date: Thu, 17 Nov 2022 17:37:38 +0100 Message-ID: <20221117163809.1009526-5-andrea.corallo@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117163809.1009526-1-andrea.corallo@arm.com> References: <20221117163809.1009526-1-andrea.corallo@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DBAEUR03FT013:EE_|AS8PR08MB8112:EE_|VI1EUR03FT045:EE_|DU2PR08MB10088:EE_ X-MS-Office365-Filtering-Correlation-Id: 48ad8e1f-e723-49de-868e-08dac8ba2930 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: n6qheLs88w/O1mBBpupPS2p3AmcXS/TsjVQtKPjgqpG2g9xhLHlBtbLOdKqq68SQur50Bw3UpF3B4eWQqzzehCa1FxoHhhNF6tdXW4V3DvEDLfzUSrFHGS3wU4efuz6TyA4g5UUgNcojf4xaQh8gceUmh7jSPlZaOj0N1o2WgjElizNLj7w5MEEdXlxw5EqNcSxIWtu0Az12Fu4cT6prE/nNlDUod+a4X7wkqJhtq+yoyYRJ4JJvqare89dT6HU8pABFkegNs+SR1WqvehpuyuD1Kld4Fuykl5jNZBnlGQrmxba9xL8cJ/koVUs/mPDw2c71traxKO8aXuIxgk/GbtbOuWFpbl6EdlfMZbu1K37YocKJyt8oIr599HAkleLJJJno18pAN6uTQFsr7yYwAfOUFAwskY0vd9zC9f7ECMKqQWaP1TsgCbwiWIKOi9EJgDjeL+/cS8SuYMT4uzYTfEaJP0fwo4WYkKs6NDW3FE3E5YOgAOIlKwJ5XpndkV5glrCUAoNq/AnJ3UaOBE04lyusxoYL2AxC0MmhtTYGg0WRkuYrqS4L/mr/KxdwqnSMl2th7IYLPz5w9Pl/eO8V74awADy2QsUcUwHpN22hC0Sab/CSp8XuGC3AtFA4HZtGGEpSMpjrq/8ZaIY0Zoo6WZ6hGP6c2avlIxVYXEG1Va1pdudEyYcNuHonUDjHopKr9kHVLKg+WSJE7DDWr5JrXHMfEupqputwK1on/oAHPUEuHsUqilQ0VQ1DLtpd1c0UmcJ1nmH61TK5zfEFNAoP30AI9gAA4K6xTO65fwz8jdcsk5r4arcPVx7KrVfXKZtz X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(346002)(136003)(376002)(39860400002)(396003)(451199015)(46966006)(40470700004)(36840700001)(8936002)(5660300002)(84970400001)(30864003)(41300700001)(8676002)(44832011)(4326008)(70586007)(316002)(54906003)(40480700001)(36756003)(36860700001)(7696005)(6916009)(6666004)(70206006)(26005)(82310400005)(47076005)(426003)(336012)(186003)(2906002)(478600001)(2616005)(356005)(83380400001)(1076003)(86362001)(82740400003)(81166007)(40460700003)(36900700001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB8112 X-MS-Exchange-Transport-CrossTenantHeadersStripped: VI1EUR03FT045.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: ec2992d5-1ba8-41e9-5146-08dac8ba21cd X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: eis4/2muiLfribpr0WTGE3o0P8nbvx1/SMNfEryF8X1bbeasYOWWuxfstBDdE09oejoxaFd8QMTc3dB9YCBiYW6CSWjGJGDvD9kx7JwOgOwBXjyZaQ119eDd6cG2SRblaOGBrdnlWr/P3QyKdD1wufYjjOcM8QncP6GiwmtVukvGRf8JzAxmIFXuau3huYJHg72ynOVY/AYoXGX56vZpSad7dHiPw4UPuoufGu8jkRoWFqfJEiN0KklRE2UWGZdUoWx5N/Dw5PMR9+fa997POSJ5pgGez8SncWBVV77x/9Yu6VLTu0n9voATU+sRcTXWpsCeD7VKPeoNZk9NBSGiWcp2O5gCUiGyUcF1BeZPFbLVyYGgeAwyPf/ucFpDQLDHnnJy24YYhPedopZZMbKan84CSjUDLYtscSSvLGEvuSA/PRw2ftII1m4kiHcKh8YdkRwi9dRB3PIzyEViN5S6430LQYSaPH9Mk/qvsv3A43qME39oyU26yhcsLPPb59v75d6bkewVRp4riTNptHOZEqU7J3YAjfVm3aeZuRemgd0iFTzfWTIv/Cu4I3ZNcuofeh8wytfr5E/AYBqiBNw/rRUpxuYHS+rdR2IN5cWfIZzKK1TxMHO+RKgAuOod0XfIq3uJp09TlcnNE09i0A1dcvZuhyJamvF0wXvfnuHf7F2XhrbywJagQUQVh2DB8olYUmThYUD2SaR3waFyxiquZVnyHMzBHI8g9hI3Qdm79uA5d9tb/cx24d/B7aAjckfmWCUGvPdkYMpbg66zVI2whQ== X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230022)(4636009)(346002)(136003)(376002)(396003)(39860400002)(451199015)(40470700004)(46966006)(36840700001)(36756003)(84970400001)(82740400003)(2906002)(36860700001)(4326008)(8936002)(81166007)(86362001)(83380400001)(1076003)(6916009)(316002)(54906003)(2616005)(426003)(186003)(336012)(478600001)(47076005)(30864003)(40480700001)(44832011)(8676002)(5660300002)(82310400005)(40460700003)(41300700001)(6666004)(7696005)(26005)(70206006)(70586007); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2022 16:38:30.5302 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 48ad8e1f-e723-49de-868e-08dac8ba2930 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VI1EUR03FT045.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR08MB10088 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749762177383056637?= X-GMAIL-MSGID: =?utf-8?q?1749762177383056637?= gcc/ChangeLog: * config/arm/mve.md (mve_vdwdupq_m_wb_u_insn): Fix spacing. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c : Improve test. * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c : Likewise. --- gcc/config/arm/mve.md | 2 +- .../arm/mve/intrinsics/vdwdupq_m_n_u16.c | 44 ++++++++++++++-- .../arm/mve/intrinsics/vdwdupq_m_n_u32.c | 46 ++++++++++++++--- .../arm/mve/intrinsics/vdwdupq_m_n_u8.c | 46 ++++++++++++++--- .../arm/mve/intrinsics/vdwdupq_m_wb_u16.c | 50 ++++++++++++++++--- .../arm/mve/intrinsics/vdwdupq_m_wb_u32.c | 48 +++++++++++++++--- .../arm/mve/intrinsics/vdwdupq_m_wb_u8.c | 50 ++++++++++++++++--- .../arm/mve/intrinsics/vdwdupq_n_u16.c | 32 ++++++++++-- .../arm/mve/intrinsics/vdwdupq_n_u32.c | 32 ++++++++++-- .../arm/mve/intrinsics/vdwdupq_n_u8.c | 32 ++++++++++-- .../arm/mve/intrinsics/vdwdupq_wb_u16.c | 32 ++++++++++-- .../arm/mve/intrinsics/vdwdupq_wb_u32.c | 32 ++++++++++-- .../arm/mve/intrinsics/vdwdupq_wb_u8.c | 32 ++++++++++-- .../arm/mve/intrinsics/vdwdupq_x_n_u16.c | 42 ++++++++++++++-- .../arm/mve/intrinsics/vdwdupq_x_n_u32.c | 46 ++++++++++++++--- .../arm/mve/intrinsics/vdwdupq_x_n_u8.c | 46 ++++++++++++++--- .../arm/mve/intrinsics/vdwdupq_x_wb_u16.c | 50 ++++++++++++++++--- .../arm/mve/intrinsics/vdwdupq_x_wb_u32.c | 46 ++++++++++++++--- .../arm/mve/intrinsics/vdwdupq_x_wb_u8.c | 50 ++++++++++++++++--- 19 files changed, 655 insertions(+), 103 deletions(-) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 1215f845388..58ffe03c499 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -9195,7 +9195,7 @@ (define_insn "mve_vdwdupq_m_wb_u_insn" VDWDUPQ_M)) ] "TARGET_HAVE_MVE" - "vpst\;\tvdwdupt.u%#\t%q2, %3, %R4, %5" + "vpst\;vdwdupt.u%#\t%q2, %3, %R4, %5" [(set_attr "type" "mve_move") (set_attr "length""8")]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c index 5303fd7d361..8f53f5ef0cb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) { - return vdwdupq_m (inactive, a, b, 1, p); + return vdwdupq_m_n_u16 (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) { return vdwdupq_m (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u16" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 (uint16x8_t inactive, mve_pred16_t p) +{ + return vdwdupq_m (inactive, 1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c index 9f22bd7f852..30e971fb733 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) { - return vdwdupq_m (inactive, a, b, 4, p); + return vdwdupq_m_n_u32 (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) { - return vdwdupq_m (inactive, a, b, 4, p); + return vdwdupq_m (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u32" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 (uint32x4_t inactive, mve_pred16_t p) +{ + return vdwdupq_m (inactive, 1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c index 0591e731958..0abc19a2318 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) { - return vdwdupq_m (inactive, a, b, 4, p); + return vdwdupq_m_n_u8 (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) { - return vdwdupq_m (inactive, a, b, 4, p); + return vdwdupq_m (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u8" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 (uint8x16_t inactive, mve_pred16_t p) +{ + return vdwdupq_m (inactive, 1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c index e4e7b47e082..b3e6affbf8f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t -foo (uint16x8_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) +foo (uint16x8_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) { - return vdwdupq_m (inactive, a, b, 8, p); + return vdwdupq_m_wb_u16 (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t -foo1 (uint16x8_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) +foo1 (uint16x8_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) { - return vdwdupq_m (inactive, a, b, 8, p); + return vdwdupq_m (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u16" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 (uint16x8_t inactive, mve_pred16_t p) +{ + return vdwdupq_m (inactive, 1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c index 42917dc9886..60c52b0d850 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t -foo (uint32x4_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) +foo (uint32x4_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) { - return vdwdupq_m (inactive, a, b, 1, p); + return vdwdupq_m_wb_u32 (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t -foo1 (uint32x4_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) +foo1 (uint32x4_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) { return vdwdupq_m (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u32" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 (uint32x4_t inactive, mve_pred16_t p) +{ + return vdwdupq_m (inactive, 1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c index 32c3153ffb3..459321a7984 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t -foo (uint8x16_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) +foo (uint8x16_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) { - return vdwdupq_m (inactive, a, b, 2, p); + return vdwdupq_m_wb_u8 (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t -foo1 (uint8x16_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) +foo1 (uint8x16_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) { - return vdwdupq_m (inactive, a, b, 2, p); + return vdwdupq_m (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u8" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 (uint8x16_t inactive, mve_pred16_t p) +{ + return vdwdupq_m (inactive, 1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c index 725a6e4bc0e..9f76dbf35eb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vdwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint32_t a, uint32_t b) { - return vdwdupq_n_u16 (a, b, 2); + return vdwdupq_n_u16 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u16" } } */ +/* +**foo1: +** ... +** vdwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint32_t a, uint32_t b) { - return vdwdupq_u16 (a, b, 2); + return vdwdupq_u16 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u16" } } */ +/* +**foo2: +** ... +** vdwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 () +{ + return vdwdupq_u16 (1, 1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c index 6ceaadb984d..962f766b496 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vdwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32_t a, uint32_t b) { - return vdwdupq_n_u32 (a, b, 8); + return vdwdupq_n_u32 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u32" } } */ +/* +**foo1: +** ... +** vdwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32_t a, uint32_t b) { - return vdwdupq_u32 (a, b, 8); + return vdwdupq_u32 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u32" } } */ +/* +**foo2: +** ... +** vdwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 () +{ + return vdwdupq_u32 (1, 1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c index a1712e418be..c73b1b69661 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vdwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint32_t a, uint32_t b) { - return vdwdupq_n_u8 (a, b, 4); + return vdwdupq_n_u8 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u8" } } */ +/* +**foo1: +** ... +** vdwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint32_t a, uint32_t b) { - return vdwdupq_u8 (a, b, 4); + return vdwdupq_u8 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u8" } } */ +/* +**foo2: +** ... +** vdwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 () +{ + return vdwdupq_u8 (1, 1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c index 0164ea9502c..3b1968d78aa 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vdwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint32_t *a, uint32_t b) { - return vdwdupq_wb_u16 (a, b, 2); + return vdwdupq_wb_u16 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u16" } } */ +/* +**foo1: +** ... +** vdwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint32_t *a, uint32_t b) { - return vdwdupq_u16 (a, b, 2); + return vdwdupq_u16 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u16" } } */ +/* +**foo2: +** ... +** vdwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 () +{ + return vdwdupq_u16 (1, 1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c index 7681371b016..8554f62ee6b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vdwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32_t *a, uint32_t b) { - return vdwdupq_wb_u32 (a, b, 8); + return vdwdupq_wb_u32 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u32" } } */ +/* +**foo1: +** ... +** vdwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32_t *a, uint32_t b) { - return vdwdupq_u32 (a, b, 8); + return vdwdupq_u32 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u32" } } */ +/* +**foo2: +** ... +** vdwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 () +{ + return vdwdupq_u32 (1, 1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c index 6f60bb09b24..eb91a80daf5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vdwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint32_t *a, uint32_t b) { - return vdwdupq_wb_u8 (a, b, 4); + return vdwdupq_wb_u8 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u8" } } */ +/* +**foo1: +** ... +** vdwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint32_t *a, uint32_t b) { - return vdwdupq_u8 (a, b, 4); + return vdwdupq_u8 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u8" } } */ +/* +**foo2: +** ... +** vdwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 () +{ + return vdwdupq_u8 (1, 1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c index ce975267531..9c0fd1e253c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint32_t a, uint32_t b, mve_pred16_t p) { return vdwdupq_x_n_u16 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint32_t a, uint32_t b, mve_pred16_t p) { return vdwdupq_x_u16 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u16" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 (mve_pred16_t p) +{ + return vdwdupq_x_u16 (1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c index 9ed75d292d8..3107e2fdbbe 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32_t a, uint32_t b, mve_pred16_t p) { - return vdwdupq_x_n_u32 (a, b, 4, p); + return vdwdupq_x_n_u32 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32_t a, uint32_t b, mve_pred16_t p) { - return vdwdupq_x_u32 (a, b, 4, p); + return vdwdupq_x_u32 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u32" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 (mve_pred16_t p) +{ + return vdwdupq_x_u32 (1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c index 3705094c4df..03d01e0dd43 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint32_t a, uint32_t b, mve_pred16_t p) { - return vdwdupq_x_n_u8 (a, b, 4, p); + return vdwdupq_x_n_u8 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint32_t a, uint32_t b, mve_pred16_t p) { - return vdwdupq_x_u8 (a, b, 4, p); + return vdwdupq_x_u8 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u8" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 (mve_pred16_t p) +{ + return vdwdupq_x_u8 (1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c index caf744d7255..f7dca660c03 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t -foo (uint32_t * a, uint32_t b, mve_pred16_t p) +foo (uint32_t *a, uint32_t b, mve_pred16_t p) { - return vdwdupq_x_wb_u16 (a, b, 8, p); + return vdwdupq_x_wb_u16 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t -foo1 (uint32_t * a, uint32_t b, mve_pred16_t p) +foo1 (uint32_t *a, uint32_t b, mve_pred16_t p) { - return vdwdupq_x_u16 (a, b, 8, p); + return vdwdupq_x_u16 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u16" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 (mve_pred16_t p) +{ + return vdwdupq_x_u16 (1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c index 8c8be86bce6..032ae94e8c3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t -foo (uint32_t * a, uint32_t b, mve_pred16_t p) +foo (uint32_t *a, uint32_t b, mve_pred16_t p) { return vdwdupq_x_wb_u32 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t -foo1 (uint32_t * a, uint32_t b, mve_pred16_t p) +foo1 (uint32_t *a, uint32_t b, mve_pred16_t p) { return vdwdupq_x_u32 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u32" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 (mve_pred16_t p) +{ + return vdwdupq_x_u32 (1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c index 1c6ef4ed33f..5d238a7a865 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t -foo (uint32_t * a, uint32_t b, mve_pred16_t p) +foo (uint32_t *a, uint32_t b, mve_pred16_t p) { - return vdwdupq_x_wb_u8 (a, b, 2, p); + return vdwdupq_x_wb_u8 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t -foo1 (uint32_t * a, uint32_t b, mve_pred16_t p) +foo1 (uint32_t *a, uint32_t b, mve_pred16_t p) { - return vdwdupq_x_u8 (a, b, 2, p); + return vdwdupq_x_u8 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u8" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 (mve_pred16_t p) +{ + return vdwdupq_x_u8 (1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file