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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id b9-20020a0565120b8900b004a4251c7f75sm1042967lfv.202.2022.11.12.13.29.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 13:29:49 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Vineet Gupta , Palmer Dabbelt , Christoph Muellner , Kito Cheng , Jeff Law , Philipp Tomsich Subject: [PATCH 2/7] RISC-V: Generate vt.maskc on noce_try_store_flag_mask if-conversion Date: Sat, 12 Nov 2022 22:29:38 +0100 Message-Id: <20221112212943.3068249-3-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221112212943.3068249-1-philipp.tomsich@vrull.eu> References: <20221112212943.3068249-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749327475147067340?= X-GMAIL-MSGID: =?utf-8?q?1749327475147067340?= Adds a pattern to map the output of noce_try_store_flag_mask if-conversion in the combiner onto vt.maskc; the input patterns supported are similar to the following: (set (reg/v/f:DI 75 [ ]) (and:DI (neg:DI (ne:DI (reg:DI 82) (const_int 0 [0]))) (reg/v/f:DI 75 [ ]))) This reduces dynamic instruction counts for the perlbench-workload in SPEC CPU2017 by 0.8230%, 0.4689%, and 0.2332% (respectively, for the each of the 3 workloads in the 'ref'-workload). To ensure that the combine-pass doesn't get confused about profitability, we recognize the idiom as requiring a single instruction when the XVentanaCondOps extension is present. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_rtx_costs): Recognize idiom for vt.maskc as a single insn with TARGET_XVENTANACONDOPS. * config/riscv/riscv.md: Include xventanacondops.md. * config/riscv/xventanacondops.md: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/xventanacondops-ne-03.c: New test. * gcc.target/riscv/xventanacondops-ne-04.c: New test. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/riscv.cc | 14 +++++++++ gcc/config/riscv/riscv.md | 1 + gcc/config/riscv/xventanacondops.md | 30 +++++++++++++++++++ .../gcc.target/riscv/xventanacondops-ne-03.c | 15 ++++++++++ .../gcc.target/riscv/xventanacondops-ne-04.c | 15 ++++++++++ 5 files changed, 75 insertions(+) create mode 100644 gcc/config/riscv/xventanacondops.md create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 2a94482b8ed..1883b5b13a7 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2269,6 +2269,20 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN return false; case AND: + /* vt.maskc/vt.maskcn for XVentanaCondOps */ + if (TARGET_XVENTANACONDOPS && mode == word_mode + && GET_CODE (XEXP (x, 0)) == NEG) + { + rtx inner = XEXP (XEXP (x, 0), 0); + + if ((GET_CODE (inner) == EQ || GET_CODE (inner) == NE) + && CONST_INT_P (XEXP (inner, 1)) + && INTVAL (XEXP (inner, 1)) == 0) + { + *total = COSTS_N_INSNS (1); + return true; + } + } /* slli.uw pattern for zba. */ if (TARGET_ZBA && TARGET_64BIT && mode == DImode && GET_CODE (XEXP (x, 0)) == ASHIFT) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 1514e10dbd1..4331842b7b2 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -3196,3 +3196,4 @@ (include "generic.md") (include "sifive-7.md") (include "vector.md") +(include "xventanacondops.md") diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md new file mode 100644 index 00000000000..641cef0e44e --- /dev/null +++ b/gcc/config/riscv/xventanacondops.md @@ -0,0 +1,30 @@ +;; Machine description for X-Ventana-CondOps +;; Copyright (C) 2022 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_code_iterator eq_or_ne [eq ne]) +(define_code_attr n [(eq "n") (ne "")]) + +(define_insn "*vt.maskc" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (neg:DI (eq_or_ne:DI + (match_operand:DI 1 "register_operand" "r") + (const_int 0))) + (match_operand:DI 2 "register_operand" "r")))] + "TARGET_XVENTANACONDOPS" + "vt.maskc\t%0,%2,%1") diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c new file mode 100644 index 00000000000..87cc69480ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long ne3(long long a, long long b) +{ + if (a != 0) + return b; + + return 0; +} + +/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */ + + diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c new file mode 100644 index 00000000000..3a04f7e52e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +long long ne4(long long a, long long b) +{ + if (a != 0) + return 0; + + return b; +} + +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */ + +