x86: Enable 256 move by pieces for ALDERLAKE and AVX2.

Message ID 20221111090838.7194-1-lili.cui@intel.com
State Accepted
Headers
Series x86: Enable 256 move by pieces for ALDERLAKE and AVX2. |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Li, Pan2 via Gcc-patches Nov. 11, 2022, 9:08 a.m. UTC
  From: Lili Cui <lili.cui@intel.com>

Hi Hontao,

This patch is to enable 256 move by pieces for ALDERLAKE and AVX2.
Bootstrap is ok, and no regressions for i386/x86-64 testsuite.

OK for master?


gcc/Changelog:

	* config/i386/x86-tune.def
	(X86_TUNE_AVX256_MOVE_BY_PIECES): Add alderlake and avx2.
	(X86_TUNE_AVX256_STORE_BY_PIECES): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pieces-memset-50.c: New test.
---
 gcc/config/i386/x86-tune.def                     |  4 ++--
 gcc/testsuite/gcc.target/i386/pieces-memset-50.c | 12 ++++++++++++
 2 files changed, 14 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-50.c
  

Comments

Hongtao Liu Nov. 17, 2022, 2:30 a.m. UTC | #1
On Fri, Nov 11, 2022 at 5:09 PM Cui,Lili via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Lili Cui <lili.cui@intel.com>
>
> Hi Hontao,
>
> This patch is to enable 256 move by pieces for ALDERLAKE and AVX2.
> Bootstrap is ok, and no regressions for i386/x86-64 testsuite.
>
> OK for master?
Ok.
>
>
> gcc/Changelog:
>
>         * config/i386/x86-tune.def
>         (X86_TUNE_AVX256_MOVE_BY_PIECES): Add alderlake and avx2.
>         (X86_TUNE_AVX256_STORE_BY_PIECES): Ditto.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/i386/pieces-memset-50.c: New test.
> ---
>  gcc/config/i386/x86-tune.def                     |  4 ++--
>  gcc/testsuite/gcc.target/i386/pieces-memset-50.c | 12 ++++++++++++
>  2 files changed, 14 insertions(+), 2 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/i386/pieces-memset-50.c
>
> diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def
> index 58e29e7806a..cd66f335113 100644
> --- a/gcc/config/i386/x86-tune.def
> +++ b/gcc/config/i386/x86-tune.def
> @@ -536,12 +536,12 @@ DEF_TUNE (X86_TUNE_AVX256_OPTIMAL, "avx256_optimal", m_CORE_AVX512)
>  /* X86_TUNE_AVX256_MOVE_BY_PIECES: Optimize move_by_pieces with 256-bit
>     AVX instructions.  */
>  DEF_TUNE (X86_TUNE_AVX256_MOVE_BY_PIECES, "avx256_move_by_pieces",
> -         m_CORE_AVX512)
> +         m_ALDERLAKE | m_CORE_AVX2)
>
>  /* X86_TUNE_AVX256_STORE_BY_PIECES: Optimize store_by_pieces with 256-bit
>     AVX instructions.  */
>  DEF_TUNE (X86_TUNE_AVX256_STORE_BY_PIECES, "avx256_store_by_pieces",
> -         m_CORE_AVX512)
> +         m_ALDERLAKE | m_CORE_AVX2)
>
>  /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
>     AVX instructions.  */
> diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-50.c b/gcc/testsuite/gcc.target/i386/pieces-memset-50.c
> new file mode 100644
> index 00000000000..c09e7c3649c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-50.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=alderlake" } */
> +
> +extern char *dst;
> +
> +void
> +foo (int x)
> +{
> +  __builtin_memset (dst, x, 64);
> +}
> +
> +/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 2 } } */
> --
> 2.17.1
>
> Thanks,
> Lili.
  

Patch

diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def
index 58e29e7806a..cd66f335113 100644
--- a/gcc/config/i386/x86-tune.def
+++ b/gcc/config/i386/x86-tune.def
@@ -536,12 +536,12 @@  DEF_TUNE (X86_TUNE_AVX256_OPTIMAL, "avx256_optimal", m_CORE_AVX512)
 /* X86_TUNE_AVX256_MOVE_BY_PIECES: Optimize move_by_pieces with 256-bit
    AVX instructions.  */
 DEF_TUNE (X86_TUNE_AVX256_MOVE_BY_PIECES, "avx256_move_by_pieces",
-	  m_CORE_AVX512)
+	  m_ALDERLAKE | m_CORE_AVX2)
 
 /* X86_TUNE_AVX256_STORE_BY_PIECES: Optimize store_by_pieces with 256-bit
    AVX instructions.  */
 DEF_TUNE (X86_TUNE_AVX256_STORE_BY_PIECES, "avx256_store_by_pieces",
-	  m_CORE_AVX512)
+	  m_ALDERLAKE | m_CORE_AVX2)
 
 /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
    AVX instructions.  */
diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-50.c b/gcc/testsuite/gcc.target/i386/pieces-memset-50.c
new file mode 100644
index 00000000000..c09e7c3649c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pieces-memset-50.c
@@ -0,0 +1,12 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=alderlake" } */
+
+extern char *dst;
+
+void
+foo (int x)
+{
+  __builtin_memset (dst, x, 64);
+}
+
+/* { dg-final { scan-assembler-times "vmovdqu\[ \\t\]+\[^\n\]*%ymm" 2 } } */