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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id mp6-20020a1709071b0600b0079800b8172bsi1140814ejc.450.2022.11.10.18.46.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Nov 2022 18:46:21 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=H0OW6DEn; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 400C13858C00 for ; Fri, 11 Nov 2022 02:46:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 400C13858C00 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668134780; bh=dWYp3NI7x3ALrSZM1PZvqPmB3xTBXbQl5GNXa4vYyDo=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=H0OW6DEn4cYcgbDeDkU6D+t2dQPgVRDokZ5CTjCHnZ7wTrSLRv3OHMyMYKfg6nRio xXShjNuRd4YY+tepV+SaeHTRtscWRJagVzSESos6lfq2hu4v8BfjYBhcLUuHgnJVdv HPro3EgTphE0c55Z8v5YIpnW+PIcRg2PWSPjJglQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id D454B3858D20 for ; Fri, 11 Nov 2022 02:45:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D454B3858D20 X-IronPort-AV: E=McAfee;i="6500,9779,10527"; a="373633104" X-IronPort-AV: E=Sophos;i="5.96,155,1665471600"; d="scan'208";a="373633104" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2022 18:45:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10527"; a="639859042" X-IronPort-AV: E=Sophos;i="5.96,155,1665471600"; d="scan'208";a="639859042" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga007.fm.intel.com with ESMTP; 10 Nov 2022 18:45:30 -0800 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 5C2631005707; Fri, 11 Nov 2022 10:45:30 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hongtao.liu@intel.com Subject: [PATCH] i386: Add AMX-TILE dependency for AMX related ISAs Date: Fri, 11 Nov 2022 10:43:30 +0800 Message-Id: <20221111024330.87663-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Gcc-patches From: "Jiang, Haochen" Reply-To: Haochen Jiang Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749166097075847110?= X-GMAIL-MSGID: =?utf-8?q?1749166097075847110?= Hi all, For all AMX related ISAs, we have a potential dependency on AMX-TILE or we even won't have the basic support on AMX. This patch added those dependency. Ok for trunk? BRs, Haochen gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_INT8_SET): Add AMX-TILE dependency. (OPTION_MASK_ISA2_AMX_BF16_SET): Ditto. (OPTION_MASK_ISA2_AMX_FP16_SET): Ditto. (OPTION_MASK_ISA2_AMX_TILE_UNSET): Disable AMX_{INT8, BF16, FP16} when disable AMX_TILE. gcc/testsuite/ChangeLog: * gcc.target/i386/amxbf16-dpbf16ps-2.c: Remove -amx-tile. * gcc.target/i386/amxfp16-dpfp16ps-2.c: Ditto. * gcc.target/i386/amxint8-dpbssd-2.c: Ditto. * gcc.target/i386/amxint8-dpbsud-2.c: Ditto. * gcc.target/i386/amxint8-dpbusd-2.c: Ditto. * gcc.target/i386/amxint8-dpbuud-2.c: Ditto. --- gcc/common/config/i386/i386-common.cc | 13 +++++++++---- gcc/testsuite/gcc.target/i386/amxbf16-dpbf16ps-2.c | 3 +-- gcc/testsuite/gcc.target/i386/amxfp16-dpfp16ps-2.c | 3 +-- gcc/testsuite/gcc.target/i386/amxint8-dpbssd-2.c | 3 +-- gcc/testsuite/gcc.target/i386/amxint8-dpbsud-2.c | 3 +-- gcc/testsuite/gcc.target/i386/amxint8-dpbusd-2.c | 3 +-- gcc/testsuite/gcc.target/i386/amxint8-dpbuud-2.c | 3 +-- 7 files changed, 15 insertions(+), 16 deletions(-) diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 431fd0d3ad1..5e6d3da0306 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -106,12 +106,15 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT #define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE -#define OPTION_MASK_ISA2_AMX_INT8_SET OPTION_MASK_ISA2_AMX_INT8 -#define OPTION_MASK_ISA2_AMX_BF16_SET OPTION_MASK_ISA2_AMX_BF16 +#define OPTION_MASK_ISA2_AMX_INT8_SET \ + (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_INT8) +#define OPTION_MASK_ISA2_AMX_BF16_SET \ + (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_BF16) #define OPTION_MASK_ISA2_AVXVNNIINT8_SET OPTION_MASK_ISA2_AVXVNNIINT8 #define OPTION_MASK_ISA2_AVXNECONVERT_SET OPTION_MASK_ISA2_AVXNECONVERT #define OPTION_MASK_ISA2_CMPCCXADD_SET OPTION_MASK_ISA2_CMPCCXADD -#define OPTION_MASK_ISA2_AMX_FP16_SET OPTION_MASK_ISA2_AMX_FP16 +#define OPTION_MASK_ISA2_AMX_FP16_SET \ + (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_FP16) #define OPTION_MASK_ISA2_PREFETCHI_SET OPTION_MASK_ISA2_PREFETCHI #define OPTION_MASK_ISA2_RAOINT_SET OPTION_MASK_ISA2_RAOINT @@ -277,7 +280,9 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT #define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK -#define OPTION_MASK_ISA2_AMX_TILE_UNSET OPTION_MASK_ISA2_AMX_TILE +#define OPTION_MASK_ISA2_AMX_TILE_UNSET \ + (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_INT8_UNSET \ + | OPTION_MASK_ISA2_AMX_BF16_UNSET | OPTION_MASK_ISA2_AMX_FP16_UNSET) #define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8 #define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16 #define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR diff --git a/gcc/testsuite/gcc.target/i386/amxbf16-dpbf16ps-2.c b/gcc/testsuite/gcc.target/i386/amxbf16-dpbf16ps-2.c index b00bc13ec78..35881e7682a 100644 --- a/gcc/testsuite/gcc.target/i386/amxbf16-dpbf16ps-2.c +++ b/gcc/testsuite/gcc.target/i386/amxbf16-dpbf16ps-2.c @@ -1,7 +1,6 @@ /* { dg-do run { target { ! ia32 } } } */ -/* { dg-require-effective-target amx_tile } */ /* { dg-require-effective-target amx_bf16 } */ -/* { dg-options "-O2 -mamx-tile -mamx-bf16" } */ +/* { dg-options "-O2 -mamx-bf16" } */ #include #define AMX_BF16 diff --git a/gcc/testsuite/gcc.target/i386/amxfp16-dpfp16ps-2.c b/gcc/testsuite/gcc.target/i386/amxfp16-dpfp16ps-2.c index 2d359a689ea..a1fafbcbfeb 100644 --- a/gcc/testsuite/gcc.target/i386/amxfp16-dpfp16ps-2.c +++ b/gcc/testsuite/gcc.target/i386/amxfp16-dpfp16ps-2.c @@ -1,8 +1,7 @@ /* { dg-do run { target { ! ia32 } } } */ -/* { dg-require-effective-target amx_tile } */ /* { dg-require-effective-target amx_fp16 } */ /* { dg-require-effective-target avx512fp16 } */ -/* { dg-options "-O2 -mamx-tile -mamx-fp16 -mavx512fp16" } */ +/* { dg-options "-O2 -mamx-fp16 -mavx512fp16" } */ #define AMX_FP16 #define DO_TEST test_amx_fp16_dpfp16ps void test_amx_fp16_dpfp16ps (); diff --git a/gcc/testsuite/gcc.target/i386/amxint8-dpbssd-2.c b/gcc/testsuite/gcc.target/i386/amxint8-dpbssd-2.c index 74ad71be5c5..d7efb3d20c2 100644 --- a/gcc/testsuite/gcc.target/i386/amxint8-dpbssd-2.c +++ b/gcc/testsuite/gcc.target/i386/amxint8-dpbssd-2.c @@ -1,7 +1,6 @@ /* { dg-do run { target { ! ia32 } } } */ -/* { dg-require-effective-target amx_tile } */ /* { dg-require-effective-target amx_int8 } */ -/* { dg-options "-O2 -mamx-tile -mamx-int8" } */ +/* { dg-options "-O2 -mamx-int8" } */ #include #define AMX_INT8 diff --git a/gcc/testsuite/gcc.target/i386/amxint8-dpbsud-2.c b/gcc/testsuite/gcc.target/i386/amxint8-dpbsud-2.c index e7241bdd860..c8bf89d738b 100644 --- a/gcc/testsuite/gcc.target/i386/amxint8-dpbsud-2.c +++ b/gcc/testsuite/gcc.target/i386/amxint8-dpbsud-2.c @@ -1,7 +1,6 @@ /* { dg-do run { target { ! ia32 } } } */ -/* { dg-require-effective-target amx_tile } */ /* { dg-require-effective-target amx_int8 } */ -/* { dg-options "-O2 -mamx-tile -mamx-int8" } */ +/* { dg-options "-O2 -mamx-int8" } */ #include #define AMX_INT8 diff --git a/gcc/testsuite/gcc.target/i386/amxint8-dpbusd-2.c b/gcc/testsuite/gcc.target/i386/amxint8-dpbusd-2.c index f0b9f97aec9..bb8777d920a 100644 --- a/gcc/testsuite/gcc.target/i386/amxint8-dpbusd-2.c +++ b/gcc/testsuite/gcc.target/i386/amxint8-dpbusd-2.c @@ -1,7 +1,6 @@ /* { dg-do run { target { ! ia32 } } } */ -/* { dg-require-effective-target amx_tile } */ /* { dg-require-effective-target amx_int8 } */ -/* { dg-options "-O2 -mamx-tile -mamx-int8" } */ +/* { dg-options "-O2 -mamx-int8" } */ #include #define AMX_INT8 diff --git a/gcc/testsuite/gcc.target/i386/amxint8-dpbuud-2.c b/gcc/testsuite/gcc.target/i386/amxint8-dpbuud-2.c index eb70b2f9259..d30f46d8de3 100644 --- a/gcc/testsuite/gcc.target/i386/amxint8-dpbuud-2.c +++ b/gcc/testsuite/gcc.target/i386/amxint8-dpbuud-2.c @@ -1,7 +1,6 @@ /* { dg-do run { target { ! ia32 } } } */ -/* { dg-require-effective-target amx_tile } */ /* { dg-require-effective-target amx_int8 } */ -/* { dg-options "-O2 -mamx-tile -mamx-int8" } */ +/* { dg-options "-O2 -mamx-int8" } */ #include #define AMX_INT8