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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id u26-20020ac25bda000000b004aab0ca795csm27911lfn.211.2022.11.10.13.34.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Nov 2022 13:34:47 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Vineet Gupta , Jeff Law , Christoph Muellner , Palmer Dabbelt , Kito Cheng , Philipp Tomsich Subject: [PATCH] RISC-V: Use bseti to cover more immediates than with ori alone Date: Thu, 10 Nov 2022 22:34:45 +0100 Message-Id: <20221110213445.3592438-1-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749146530060419862?= X-GMAIL-MSGID: =?utf-8?q?1749146530060419862?= Sequences of the form "a | C" with C being the positive half of a signed immediate's range with one extra bit set in addtion are mapped to ori and one binvi to avoid using a temporary (and a multi-insn sequence to load C into that temporary). gcc/ChangeLog: * config/riscv/bitmanip.md (*bseti_extrabit): New pattern gcc/testsuite/ChangeLog: * gcc.target/riscv/zbs-bseti.c: New test. Signed-off-by: Philipp Tomsich --- - Depends on a predicate posted in "RISC-V: Optimize branches testing a bit-range or a shifted immediate". Depending on the order of applying these, I'll take care to pull that part out of the other patch if needed. gcc/config/riscv/bitmanip.md | 19 +++++++++++++++ gcc/testsuite/gcc.target/riscv/zbs-bseti.c | 27 ++++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bseti.c diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 06126ac4819..436ff4ba958 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -512,6 +512,25 @@ "bseti\t%0,%1,%S2" [(set_attr "type" "bitmanip")]) +; Catch those cases where we can use a bseti + ori or bseti + bseti +; instead of a lui + addi + or sequence. +(define_insn_and_split "*bseti_extrabit" + [(set (match_operand:X 0 "register_operand" "=r") + (ior:X (match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "uimm_extra_bit_operand" "i")))] + "TARGET_ZBS" + "#" + "&& reload_completed" + [(set (match_dup 0) (ior:X (match_dup 1) (match_dup 3))) + (set (match_dup 0) (ior:X (match_dup 0) (match_dup 4)))] +{ + unsigned HOST_WIDE_INT bits = UINTVAL (operands[2]); + unsigned HOST_WIDE_INT topbit = HOST_WIDE_INT_1U << floor_log2 (bits); + + operands[3] = GEN_INT (bits &~ topbit); + operands[4] = GEN_INT (topbit); +}) + ;; As long as the SImode operand is not a partial subreg, we can use a ;; bseti without postprocessing, as the middle end is smart enough to ;; stay away from the signbit. diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bseti.c b/gcc/testsuite/gcc.target/riscv/zbs-bseti.c new file mode 100644 index 00000000000..5738add6348 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbs-bseti.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +long long foo1 (long long a) +{ + return a | 0x1100; +} + +long long foo2 (long long a) +{ + return a | 0x80000000000000ffull; +} + +long long foo3 (long long a) +{ + return a | 0x8000000100000000ull; +} + +long long foo4 (long long a) +{ + return a | 0xfff; +} + +/* { dg-final { scan-assembler-times "bseti\t" 5 } } */ +/* { dg-final { scan-assembler-times "ori\t" 3 } } */ +