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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id a17-20020a19ca11000000b00492aefd73a5sm31925lfg.132.2022.11.10.13.34.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Nov 2022 13:34:05 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Palmer Dabbelt , Vineet Gupta , Jeff Law , Christoph Muellner , Kito Cheng , Philipp Tomsich Subject: [PATCH v2] RISC-V: costs: support shift-and-add in strength-reduction Date: Thu, 10 Nov 2022 22:34:03 +0100 Message-Id: <20221110213403.3592364-1-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748959061032937259?= X-GMAIL-MSGID: =?utf-8?q?1749146484088975122?= The strength-reduction implementation in expmed.cc will assess the profitability of using shift-and-add using a RTL expression that wraps a MULT (with a power-of-2) in a PLUS. Unless the RISC-V rtx_costs function recognizes this as expressing a sh[123]add instruction, we will return an inflated cost---thus defeating the optimization. This change adds the necessary idiom recognition to provide an accurate cost for this for of expressing sh[123]add. Instead on expanding to li a5,200 mulw a0,a5,a0 with this change, the expression 'a * 200' is sythesized as: sh2add a0,a0,a0 // *5 = a + 4 * a sh2add a0,a0,a0 // *5 = a + 4 * a slli a0,a0,3 // *8 gcc/ChangeLog: * config/riscv/riscv.c (riscv_rtx_costs): Recognize shNadd, if expressed as a plus and multiplication with a power-of-2. Split costing for MINUS from PLUS. gcc/testsuite/ChangeLog: * gcc.target/riscv/zba-shNadd-07.c: New test. Signed-off-by: Philipp Tomsich --- Changes in v2: - Split rtx_costs calculation for MINUS from PLUS to ensure that (minus reg (ashift reg SHAMT)) is not mistaken for a shNadd - Add testcase gcc/config/riscv/riscv.cc | 19 ++++++++++++ .../gcc.target/riscv/zba-shNadd-07.c | 31 +++++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-07.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 3e2dc8192e4..2a94482b8ed 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2428,6 +2428,12 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN return false; case MINUS: + if (float_mode_p) + *total = tune_param->fp_add[mode == DFmode]; + else + *total = riscv_binary_cost (x, 1, 4); + return false; + case PLUS: /* add.uw pattern for zba. */ if (TARGET_ZBA @@ -2451,6 +2457,19 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN *total = COSTS_N_INSNS (1); return true; } + /* Before strength-reduction, the shNadd can be expressed as the addition + of a multiplication with a power-of-two. If this case is not handled, + the strength-reduction in expmed.c will calculate an inflated cost. */ + if (TARGET_ZBA + && mode == word_mode + && GET_CODE (XEXP (x, 0)) == MULT + && REG_P (XEXP (XEXP (x, 0), 0)) + && CONST_INT_P (XEXP (XEXP (x, 0), 1)) + && IN_RANGE (pow2p_hwi (INTVAL (XEXP (XEXP (x, 0), 1))), 1, 3)) + { + *total = COSTS_N_INSNS (1); + return true; + } /* shNadd.uw pattern for zba. [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-07.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-07.c new file mode 100644 index 00000000000..98d35e1da9b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-07.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */ + +unsigned long +f1 (unsigned long i) +{ + return i * 200; +} + +unsigned long +f2 (unsigned long i) +{ + return i * 783; +} + +unsigned long +f3 (unsigned long i) +{ + return i * 784; +} + +unsigned long +f4 (unsigned long i) +{ + return i * 1574; +} + +/* { dg-final { scan-assembler-times "sh2add" 2 } } */ +/* { dg-final { scan-assembler-times "sh1add" 2 } } */ +/* { dg-final { scan-assembler-times "slli" 5 } } */ +/* { dg-final { scan-assembler-times "mul" 1 } } */