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[8.43.85.97]) by mx.google.com with ESMTPS id nd18-20020a170907629200b007ae417013desi12813217ejc.324.2022.11.07.17.18.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Nov 2022 17:18:44 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=VZw5LHEi; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 26F5C3858427 for ; Tue, 8 Nov 2022 01:18:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 26F5C3858427 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1667870323; bh=Kp/i/MnSH6kBZpSga9n9zHuHTdk5RnOwLCXUNS6jQHg=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=VZw5LHEioVwiVB+8MxVmja5TUg7ta3b4IdmnLo5hYsiczJQPta9LMmaXsDZC38Gel TtYnlVijgopz6VFmG2d2SgUKUKM6Y+haBxMWtnHwwiuksbGbn9yWLozeMEAU0JoPwr 4TNzDqsuALWXoRaz0lC5j1P1e1XAUX/Gej5CK0Xo= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id B5BD53858409 for ; Tue, 8 Nov 2022 01:17:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B5BD53858409 X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="308191792" X-IronPort-AV: E=Sophos;i="5.96,145,1665471600"; d="scan'208";a="308191792" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2022 17:17:54 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="587184909" X-IronPort-AV: E=Sophos;i="5.96,145,1665471600"; d="scan'208";a="587184909" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga003.jf.intel.com with ESMTP; 07 Nov 2022 17:17:52 -0800 Received: from shliclel4051.sh.intel.com (shliclel4051.sh.intel.com [10.239.240.51]) by shvmail03.sh.intel.com (Postfix) with ESMTP id B659B10056BA; Tue, 8 Nov 2022 09:17:51 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com, hjl.tools@gmail.com, ubizjak@gmail.com Subject: [PATCH] Fix incorrect insn type to avoid ICE in memory attr auto-detection. Date: Tue, 8 Nov 2022 09:17:51 +0800 Message-Id: <20221108011751.286433-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748888792703406499?= X-GMAIL-MSGID: =?utf-8?q?1748888792703406499?= Memory attribute auto detection will check operand 2 for type sselog, and check operand 1 for type sselog1. For below 2 insns, there's no operand 2. Change type to sselog1. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ok for trunk? gcc/ChangeLog: PR target/107540 * config/i386/sse.md (avx512f_movddup512): Change type from sselog to sselog1. (avx_movddup256): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr107540.c: New test. --- gcc/config/i386/sse.md | 4 ++-- gcc/testsuite/gcc.target/i386/pr107540.c | 12 ++++++++++++ 2 files changed, 14 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr107540.c diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index fa93ae7bf21..4e8463addc3 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -12203,7 +12203,7 @@ (define_insn "avx512f_movddup512" (const_int 6) (const_int 14)])))] "TARGET_AVX512F" "vmovddup\t{%1, %0|%0, %1}" - [(set_attr "type" "sselog") + [(set_attr "type" "sselog1") (set_attr "prefix" "evex") (set_attr "mode" "V8DF")]) @@ -12234,7 +12234,7 @@ (define_insn "avx_movddup256" (const_int 2) (const_int 6)])))] "TARGET_AVX && " "vmovddup\t{%1, %0|%0, %1}" - [(set_attr "type" "sselog") + [(set_attr "type" "sselog1") (set_attr "prefix" "") (set_attr "mode" "V4DF")]) diff --git a/gcc/testsuite/gcc.target/i386/pr107540.c b/gcc/testsuite/gcc.target/i386/pr107540.c new file mode 100644 index 00000000000..a0351ff9cb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr107540.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-flive-range-shrinkage -mavx" } */ + +typedef double __attribute__((__vector_size__ (32))) V; + +V v; + +void +foo (void) +{ + v = __builtin_ia32_movddup256 (v); +}