From patchwork Mon Oct 24 14:24:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 9516 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp482293wru; Mon, 24 Oct 2022 07:24:54 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6tdcYSCv7lU02qfcF16h6vGcjXCn05jKiaUzWiKt5UDDQSDx6kJPLK4oS0pV2PE2Yss7Vo X-Received: by 2002:a17:907:2e19:b0:78e:281d:91fe with SMTP id ig25-20020a1709072e1900b0078e281d91femr28266137ejc.482.1666621493990; Mon, 24 Oct 2022 07:24:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666621493; cv=none; d=google.com; s=arc-20160816; b=jnaknPLHSOIUMTJS7SMilcace6XwY4ph6qvpk5RwKFh6d/yFdQe7hOn6QWcRwX5xe3 CnC6u/XI+rWoWhiiobTm5IezRbDE279czuSQ8xn2Qoz1j4NZ8lu3SfMeDlHQ3mlMaG/H ehVd13WkLcTZDSvtA3Fz6qBcGTb600f4Kw2yinpT7A/uo5cQZ78678LToKgIi4OmXYuV YeCM9SLtTLDTDnLH5M9sHEl6VslcwCSu1DB4oVPYwpQgF2YSabRXiwlxM9IakvZkA4Ct Ousm4JoC1iVdXHzPk5IfG2wRHVwcfk53OUp4uDQA1GWtPclvhiDw1lpMddoQG1IpdEvc 4f8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:feedback-id :content-transfer-encoding:mime-version:message-id:date:subject:to :from:dmarc-filter:delivered-to; bh=LiG5gKzpiEeB3RpMtupGMICnPSVlBzEWtad/f4ZoEl0=; b=Ki0w9ecbTe43qFaDG14vhElMR/O4IeCopBRIZ/RgGgNBdXNyRofk40s8m76pjuAmIv zKt3m5ii8revUdvbJKGDwNzFBN28W4h9c4VY5NHc/oZ16oo6Fac+pw0Q2j5mwb4bnXEr YbpGkmg6BlNPq00f48ZJ7tlD55JtsiwZ402dTdpmHefZUEOn8SW8zUZdf8zYwd/ekC7a kRpuITDJRlL2U7ocPdPocJooEAjcQXR8CHceN5FSxeLPg+LvZ7RXjWGlc+Gb2g6zZeaV 41uHi0+w1iVFqLBA3VhGsfFzoC4ujm/vQCtVDEj02Ms+7UI5NBUuGVPaU+XAEQdu3PVP r21w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id q6-20020a17090676c600b0078da414a7cesi23659705ejn.149.2022.10.24.07.24.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Oct 2022 07:24:53 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0C8B03856DC3 for ; Mon, 24 Oct 2022 14:24:50 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130]) by sourceware.org (Postfix) with ESMTPS id 788B0385840C for ; Mon, 24 Oct 2022 14:24:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 788B0385840C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp72t1666621459tws7xvai Received: from rios-cad5.localdomain ( [42.247.22.66]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 24 Oct 2022 22:24:17 +0800 (CST) X-QQ-SSF: 01400000002000D0K000B00A0000000 X-QQ-FEAT: pMHwdq3i9JPmrzAQsWSEQ162e61PG/F3JlesaQubawoUeW3URopnTvP6HFHIi yQ6mJRz8naDcnpnglvmBV9TKcwSgaxmsM7mQOpU8qUupP+49RjFtmisF+ECkJ8Ie03iPNzP j5MHdMDHfrLpGeyiNlEKzBqeHO+2F2hasqnubVaQNiT0LXvb0p/abhM+mm0stU2DC92KpLO 3RAqAVaV+ZVqBRDkEgDI2VjbgA8G68nd5969kSVF+4yvdsimdw0vWgsuXpfK1SF6O3s56IE ioK4IG7S4YXkyRoDsrEA9wrHo+ZGGInf8nA4pbhMpxbOBYvqOiMcoS7aTf6uLOO0oexEuvs rvjQlsJoqmzCWqZYzgTm3vT92o71lJD3eOMbSoobpvoj1bamCyxmtoWW2U/UW8QFyuywV5s hrM7BSuxkog= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Fix typo. Date: Mon, 24 Oct 2022 22:24:14 +0800 Message-Id: <20221024142414.161380-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747579299848076575?= X-GMAIL-MSGID: =?utf-8?q?1747579299848076575?= From: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/riscv-modes.def (ADJUST_BYTESIZE): Fix typo. --- gcc/config/riscv/riscv-modes.def | 46 ++++++++++++++++---------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def index 95f69e87e23..ea88442e117 100644 --- a/gcc/config/riscv/riscv-modes.def +++ b/gcc/config/riscv/riscv-modes.def @@ -71,29 +71,29 @@ ADJUST_BYTESIZE (VNx64BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); /* | Mode | MIN_VLEN=32 | MIN_VLEN=32 | MIN_VLEN=64 | MIN_VLEN=64 | - | | LMUL | SEW/LMUL | LMUL | SEW/LMUL | - | VNx1QI | MF4 | 32 | MF8 | 64 | - | VNx2QI | MF2 | 16 | MF4 | 32 | - | VNx4QI | M1 | 8 | MF2 | 16 | - | VNx8QI | M2 | 4 | M1 | 8 | - | VNx16QI | M4 | 2 | M2 | 4 | - | VNx32QI | M8 | 1 | M4 | 2 | - | VNx64QI | N/A | N/A | M8 | 1 | - | VNx1(HI|HF) | MF2 | 32 | MF4 | 64 | - | VNx2(HI|HF) | M1 | 16 | MF2 | 32 | - | VNx4(HI|HF) | M2 | 8 | M1 | 16 | - | VNx8(HI|HF) | M4 | 4 | M2 | 8 | - | VNx16(HI|HF)| M8 | 2 | M4 | 4 | - | VNx32(HI|HF)| N/A | N/A | M8 | 2 | - | VNx1(SI|SF) | M1 | 32 | MF2 | 64 | - | VNx2(SI|SF) | M2 | 16 | M1 | 32 | - | VNx4(SI|SF) | M4 | 8 | M2 | 16 | - | VNx8(SI|SF) | M8 | 4 | M4 | 8 | - | VNx16(SI|SF)| N/A | N/A | M8 | 4 | - | VNx1(DI|DF) | N/A | N/A | M1 | 64 | - | VNx2(DI|DF) | N/A | N/A | M2 | 32 | - | VNx4(DI|DF) | N/A | N/A | M4 | 16 | - | VNx8(DI|DF) | N/A | N/A | M8 | 8 | + | | LMUL | SEW/LMUL | LMUL | SEW/LMUL | + | VNx1QI | MF4 | 32 | MF8 | 64 | + | VNx2QI | MF2 | 16 | MF4 | 32 | + | VNx4QI | M1 | 8 | MF2 | 16 | + | VNx8QI | M2 | 4 | M1 | 8 | + | VNx16QI | M4 | 2 | M2 | 4 | + | VNx32QI | M8 | 1 | M4 | 2 | + | VNx64QI | N/A | N/A | M8 | 1 | + | VNx1(HI|HF) | MF2 | 32 | MF4 | 64 | + | VNx2(HI|HF) | M1 | 16 | MF2 | 32 | + | VNx4(HI|HF) | M2 | 8 | M1 | 16 | + | VNx8(HI|HF) | M4 | 4 | M2 | 8 | + | VNx16(HI|HF)| M8 | 2 | M4 | 4 | + | VNx32(HI|HF)| N/A | N/A | M8 | 2 | + | VNx1(SI|SF) | M1 | 32 | MF2 | 64 | + | VNx2(SI|SF) | M2 | 16 | M1 | 32 | + | VNx4(SI|SF) | M4 | 8 | M2 | 16 | + | VNx8(SI|SF) | M8 | 4 | M4 | 8 | + | VNx16(SI|SF)| N/A | N/A | M8 | 4 | + | VNx1(DI|DF) | N/A | N/A | M1 | 64 | + | VNx2(DI|DF) | N/A | N/A | M2 | 32 | + | VNx4(DI|DF) | N/A | N/A | M4 | 16 | + | VNx8(DI|DF) | N/A | N/A | M8 | 8 | */ /* Define RVV modes whose sizes are multiples of 64-bit chunks. */