Message ID | 20221024020524.27704-1-juzhe.zhong@rivai.ai |
---|---|
State | Accepted |
Headers |
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[8.43.85.97]) by mx.google.com with ESMTPS id ml21-20020a170906cc1500b007a1d4f0e7fcsi4873898ejb.655.2022.10.23.19.06.21 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 19:06:21 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2B6A3385AE5F for <ouuuleilei@gmail.com>; Mon, 24 Oct 2022 02:06:20 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22]) by sourceware.org (Postfix) with ESMTPS id 0824038582A8 for <gcc-patches@gcc.gnu.org>; Mon, 24 Oct 2022 02:05:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0824038582A8 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp82t1666577126tjlcqdzu Received: from server1.localdomain ( [42.247.22.65]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 24 Oct 2022 10:05:24 +0800 (CST) X-QQ-SSF: 01400000000000D0K000000A0000000 X-QQ-FEAT: ALw5QuVtm4WC7WQd6A6ihrVzLER2vbD1ERfujk7p4Yjh4dv206HS5/mdyji9N kZ5LJd+srNf8RlHApxwWJAeWyXkVYRRjUDjXWjjJ5TI2TGebYXnUHlGnNYXfCgnpRnQ7xVS UIwc0c2ttr2h+hEJCGKexsCNScjgK/pzLglS1+fK87q8mhjXAtRnU2Mdn3vfrqVs34sT5DH G3R4F7Za+PqxK3lHb2B6ep4Hl/Dy/p+cfPzLXgrpi6pZ91se3mxg75Nj5ahvfSf6k4fttHs jqFcDW5nzW0KTFsILmhNscjVAKMDbmda92yZAlUbxllZ3OT/fru8chQZ2d7FkqXPCVvkpj1 uf+FfG4E5D+mmkYMYlA5k99aV/f5tvqwUgvSl1EQtQ7k1t10W3oMA/255mVUg== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Remove unused TI/TF vector modes. Date: Mon, 24 Oct 2022 10:05:24 +0800 Message-Id: <20221024020524.27704-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> Cc: kito.cheng@gmail.com, Ju-Zhe Zhong <juzhe.zhong@rivai.ai> Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org> X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747532834723727602?= X-GMAIL-MSGID: =?utf-8?q?1747532834723727602?= |
Series |
RISC-V: Remove unused TI/TF vector modes.
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Checks
Context | Check | Description |
---|---|---|
snail/gcc-patch-check | success | Github commit url |
Commit Message
juzhe.zhong@rivai.ai
Oct. 24, 2022, 2:05 a.m. UTC
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv-vector-switch.def (ENTRY): Remove unused TI/TF vector modes.
---
gcc/config/riscv/riscv-vector-switch.def | 4 ----
1 file changed, 4 deletions(-)
Comments
Committed, thanks :) On Mon, Oct 24, 2022 at 10:06 AM <juzhe.zhong@rivai.ai> wrote: > > From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai> > > gcc/ChangeLog: > > * config/riscv/riscv-vector-switch.def (ENTRY): Remove unused TI/TF vector modes. > > --- > gcc/config/riscv/riscv-vector-switch.def | 4 ---- > 1 file changed, 4 deletions(-) > > diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/riscv-vector-switch.def > index cacfccb6d29..ee8ebd5f1cc 100644 > --- a/gcc/config/riscv/riscv-vector-switch.def > +++ b/gcc/config/riscv/riscv-vector-switch.def > @@ -155,10 +155,6 @@ ENTRY (VNx4DF, TARGET_VECTOR_FP64) > ENTRY (VNx2DF, TARGET_VECTOR_FP64) > ENTRY (VNx1DF, TARGET_VECTOR_FP64) > > -/* SEW = 128. Disable all of them. */ > -ENTRY (VNx2TI, false) > -ENTRY (VNx2TF, false) > - > #undef TARGET_VECTOR_FP32 > #undef TARGET_VECTOR_FP64 > #undef ENTRY > -- > 2.36.1 >
diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/riscv-vector-switch.def index cacfccb6d29..ee8ebd5f1cc 100644 --- a/gcc/config/riscv/riscv-vector-switch.def +++ b/gcc/config/riscv/riscv-vector-switch.def @@ -155,10 +155,6 @@ ENTRY (VNx4DF, TARGET_VECTOR_FP64) ENTRY (VNx2DF, TARGET_VECTOR_FP64) ENTRY (VNx1DF, TARGET_VECTOR_FP64) -/* SEW = 128. Disable all of them. */ -ENTRY (VNx2TI, false) -ENTRY (VNx2TF, false) - #undef TARGET_VECTOR_FP32 #undef TARGET_VECTOR_FP64 #undef ENTRY