diff mbox series

RISC-V: Support (set (mem) (const_poly_int))

Message ID 20221024020312.26851-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Support (set (mem) (const_poly_int)) |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai Oct. 24, 2022, 2:03 a.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem) (const_poly_int)).

---
 gcc/config/riscv/riscv.cc | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

Comments

Andrew Pinski Oct. 24, 2022, 2:14 a.m. UTC | #1 
On Sun, Oct 23, 2022 at 7:04 PM <juzhe.zhong@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem) (const_poly_int)).
>
> ---
>  gcc/config/riscv/riscv.cc | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 90a39047dd7..f7694ba043c 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -1958,6 +1958,20 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
>  {
>    if (CONST_POLY_INT_P (src))
>      {
> +      /*
> +       Handle:
> +         (insn 183 182 184 6 (set (mem:QI (plus:DI (reg/f:DI 156)
> +                 (const_int 96 [0x60])) [0  S1 A8])
> +         (const_poly_int:QI [8, 8]))
> +       "../../../../riscv-gcc/libgcc/unwind-dw2.c":1579:3 -1 (nil))
> +      */
> +      if (MEM_P (dest))
> +       {
> +         rtx tmp = gen_reg_rtx (mode);
> +         emit_move_insn (tmp, src);
> +         emit_move_insn (dest, tmp);

Couldn't you just use force_reg here instead of the above?
Something like:
emit_move_insn (dest, force_reg (mode, src));

Thanks,
Andrew Pinski

> +         return true;
> +       }
>        poly_int64 value = rtx_to_poly_int64 (src);
>        if (!value.is_constant () && !TARGET_VECTOR)
>         {
> --
> 2.36.1
>
juzhe.zhong@rivai.ai Oct. 24, 2022, 2:22 a.m. UTC | #2 
Address comments. Fix it soon.



juzhe.zhong@rivai.ai
 
From: Andrew Pinski
Date: 2022-10-24 10:14
To: juzhe.zhong
CC: gcc-patches; kito.cheng
Subject: Re: [PATCH] RISC-V: Support (set (mem) (const_poly_int))
On Sun, Oct 23, 2022 at 7:04 PM <juzhe.zhong@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem) (const_poly_int)).
>
> ---
>  gcc/config/riscv/riscv.cc | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 90a39047dd7..f7694ba043c 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -1958,6 +1958,20 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
>  {
>    if (CONST_POLY_INT_P (src))
>      {
> +      /*
> +       Handle:
> +         (insn 183 182 184 6 (set (mem:QI (plus:DI (reg/f:DI 156)
> +                 (const_int 96 [0x60])) [0  S1 A8])
> +         (const_poly_int:QI [8, 8]))
> +       "../../../../riscv-gcc/libgcc/unwind-dw2.c":1579:3 -1 (nil))
> +      */
> +      if (MEM_P (dest))
> +       {
> +         rtx tmp = gen_reg_rtx (mode);
> +         emit_move_insn (tmp, src);
> +         emit_move_insn (dest, tmp);
 
Couldn't you just use force_reg here instead of the above?
Something like:
emit_move_insn (dest, force_reg (mode, src));
 
Thanks,
Andrew Pinski
 
> +         return true;
> +       }
>        poly_int64 value = rtx_to_poly_int64 (src);
>        if (!value.is_constant () && !TARGET_VECTOR)
>         {
> --
> 2.36.1
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 90a39047dd7..f7694ba043c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1958,6 +1958,20 @@  riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
 {
   if (CONST_POLY_INT_P (src))
     {
+      /*
+	Handle:
+	  (insn 183 182 184 6 (set (mem:QI (plus:DI (reg/f:DI 156)
+		  (const_int 96 [0x60])) [0  S1 A8])
+	  (const_poly_int:QI [8, 8]))
+	"../../../../riscv-gcc/libgcc/unwind-dw2.c":1579:3 -1 (nil))
+      */
+      if (MEM_P (dest))
+	{
+	  rtx tmp = gen_reg_rtx (mode);
+	  emit_move_insn (tmp, src);
+	  emit_move_insn (dest, tmp);
+	  return true;
+	}
       poly_int64 value = rtx_to_poly_int64 (src);
       if (!value.is_constant () && !TARGET_VECTOR)
 	{