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[8.43.85.97]) by mx.google.com with ESMTPS id d7-20020a056402144700b0046042016d8bsi1160257edx.447.2022.10.20.02.46.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 02:46:44 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D75AA3865C29 for ; Thu, 20 Oct 2022 09:35:47 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) by sourceware.org (Postfix) with ESMTP id 694373AA9829 for ; Thu, 20 Oct 2022 09:33:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 694373AA9829 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.113.87.88]) by APP-05 (Coremail) with SMTP id zQCowAB3jnfCFVFjiiDzBQ--.8085S5; Thu, 20 Oct 2022 17:32:52 +0800 (CST) From: jiawei To: gcc-patches@gcc.gnu.org Subject: [v4 PATCH 3/4] RISC-V: Limit regs use for z*inx extension. Date: Thu, 20 Oct 2022 17:32:34 +0800 Message-Id: <20221020093235.5071-4-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221020093235.5071-1-jiawei@iscas.ac.cn> References: <20221020093235.5071-1-jiawei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowAB3jnfCFVFjiiDzBQ--.8085S5 X-Coremail-Antispam: 1UD129KBjvJXoWxGr15CFW7CF1DAr4fuw4fGrg_yoWrWw17pa 1UGwsYvFn5JFySgF4ftF18Gw1fZws7Kr1rCryxZ3y7AanxGrWkJFsFya4akFZrWan8Cry7 Zws3Ca13Cw4Uua7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUB214x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JrWl82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE174l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjTRCq2MDUUUU X-Originating-IP: [47.113.87.88] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiCQMFAGNQ8XSI3QAAss X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@sifive.com, wuwei2016@iscas.ac.cn, Jiawei Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747199411727543302?= X-GMAIL-MSGID: =?utf-8?q?1747199411727543302?= From: Jiawei Limit z*inx abi support with 'ilp32','ilp32e','lp64' only. Use GPR instead FPR when 'zfinx' enable, Only use even registers in RV32 when 'zdinx' enable. Enable FLOAT16 when Zhinx/Zhinxmin enabled. Co-Authored-By: Sinan Lin. gcc/ChangeLog: * config/riscv/constraints.md (TARGET_ZFINX ? GR_REGS): Set GPRS use while Zfinx is enable. * config/riscv/riscv.cc (riscv_hard_regno_mode_ok): Limit odd registers use when Zdinx enable in RV32 cases. (riscv_option_override): New target enable MASK_FDIV. (riscv_libgcc_floating_mode_supported_p): New error info when use incompatible arch&abi. (riscv_excess_precision): New target enable FLOAT16. --- gcc/config/riscv/constraints.md | 5 +++-- gcc/config/riscv/riscv.cc | 21 +++++++++++++++++---- 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 8997284f32e..c53e0f38920 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -21,8 +21,9 @@ ;; Register constraints -(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS" - "A floating-point register (if available).") +(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : + (TARGET_ZFINX ? GR_REGS) : NO_REGS" + "A floating-point register (if available, reuse GPR as FPR when use zfinx).") (define_register_constraint "j" "SIBCALL_REGS" "@internal") diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index ad57b995e7b..38631605b2c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5356,6 +5356,13 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) != call_used_or_fixed_reg_p (regno + i)) return false; + /* Only use even registers in RV32 ZDINX */ + if (!TARGET_64BIT && TARGET_ZDINX){ + if (GET_MODE_CLASS (mode) == MODE_FLOAT && + GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DFmode)) + return !(regno & 1); + } + return true; } @@ -5595,7 +5602,7 @@ riscv_option_override (void) error ("%<-mdiv%> requires %<-march%> to subsume the % extension"); /* Likewise floating-point division and square root. */ - if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0) + if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & MASK_FDIV) == 0) target_flags |= MASK_FDIV; /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune @@ -5641,6 +5648,11 @@ riscv_option_override (void) if (TARGET_RVE && riscv_abi != ABI_ILP32E) error ("rv32e requires ilp32e ABI"); + // Zfinx require abi ilp32,ilp32e or lp64. + if (TARGET_ZFINX && riscv_abi != ABI_ILP32 + && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E) + error ("z*inx requires ABI ilp32, ilp32e or lp64"); + /* We do not yet support ILP32 on RV64. */ if (BITS_PER_WORD != POINTER_SIZE) error ("ABI requires %<-march=rv%d%>", POINTER_SIZE); @@ -6273,7 +6285,7 @@ riscv_libgcc_floating_mode_supported_p (scalar_float_mode mode) precision of the _FloatN type; evaluate all other operations and constants to the range and precision of the semantic type; - If we have the zfh extensions then we support _Float16 in native + If we have the zfh/zhinx extensions then we support _Float16 in native precision, so we should set this to 16. */ static enum flt_eval_method riscv_excess_precision (enum excess_precision_type type) @@ -6282,8 +6294,9 @@ riscv_excess_precision (enum excess_precision_type type) { case EXCESS_PRECISION_TYPE_FAST: case EXCESS_PRECISION_TYPE_STANDARD: - return (TARGET_ZFH ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 - : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT); + return ((TARGET_ZFH || TARGET_ZHINX || TARGET_ZHINXMIN) + ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 + : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT); case EXCESS_PRECISION_TYPE_IMPLICIT: case EXCESS_PRECISION_TYPE_FLOAT16: return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16;